Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915785
Jun Han, Zhidan He
With the rapid development of integrated circuits, flip-chip has become the mainstream packaging technology. The solder bumps in the connection area between the chip and the substrate mainly play the role of electrical connection, mechanical connection and heat exchange. Due to the miniaturization and multi-function development of electronic products, electronic packaging solder joints are becoming denser and smaller in size. Therefore, it is also exposed to higher electrical, mechanical and thermal stresses. According to statistics, solder joint failure accounts for more than half of the failure of electronic products. Therefore, in this study, we have extracted the classic failure cases of packaged products through daily failure analysis work, and explained the failure reasons. The open failure of solder joints mainly involves foreign material flux leading to solder joint rejection, and thermal expansion and contraction effect leading to the crack of the solder IMC on the substrate side; the short failure of solder joints mainly involves the bridging of adjacent solder joints caused by foreign material back gold; in addition, it is also found that abnormal circuit at the die level lead to leakage failure. All in all, finding the root cause for these failure will significantly help improve the manufacturing process.
{"title":"Flip Chip Typical Failure Case Analysis Research","authors":"Jun Han, Zhidan He","doi":"10.1109/IPFA55383.2022.9915785","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915785","url":null,"abstract":"With the rapid development of integrated circuits, flip-chip has become the mainstream packaging technology. The solder bumps in the connection area between the chip and the substrate mainly play the role of electrical connection, mechanical connection and heat exchange. Due to the miniaturization and multi-function development of electronic products, electronic packaging solder joints are becoming denser and smaller in size. Therefore, it is also exposed to higher electrical, mechanical and thermal stresses. According to statistics, solder joint failure accounts for more than half of the failure of electronic products. Therefore, in this study, we have extracted the classic failure cases of packaged products through daily failure analysis work, and explained the failure reasons. The open failure of solder joints mainly involves foreign material flux leading to solder joint rejection, and thermal expansion and contraction effect leading to the crack of the solder IMC on the substrate side; the short failure of solder joints mainly involves the bridging of adjacent solder joints caused by foreign material back gold; in addition, it is also found that abnormal circuit at the die level lead to leakage failure. All in all, finding the root cause for these failure will significantly help improve the manufacturing process.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127928929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915778
Hsu Li khoo, L.L. Goh, Y. G., Kok Heng Lau, C. N. Liew, Siew Ming Lim
Failure analysis in scale down devices becoming very much intricate by following Moore’s law concept for current technology trend. Thus, this indirectly bring a very challenging task for failure analyst (FA) to identify the real defect in complex integrated circuit effectively (IC). Metal insulator- metal (MIM) capacitor has become popular choice for designers to select in the different signal devices as it is well known to stabilize a voltage reduction that ultimately leads to drastically improved product and transistor performance [1]. In this paper, we did come out an excellent technique to isolate MIMCAP defects effectively by characterizing comprehensive phase angle measurement that can be performed by using Enhance Lock in Thermal Emission (ELITE) machine. Through the established fault isolation (FI) methods carried out, we can isolate the defect accuracy and physical failure analyst (PFA) is able to reveal the real defects in shorten time and achieve higher success rate in findings. This is mainly because MIMCAP is a very thin parasitic layer about 50X thinner than next metal layer that sandwiched in between top metal layer 1 and top metal layer 0 which PFA might missed out during inspection by following conventional PFA approached to find out the defects.
{"title":"Failure analysis on MIMCAP failures of 10nm devices using phase angle measurement method","authors":"Hsu Li khoo, L.L. Goh, Y. G., Kok Heng Lau, C. N. Liew, Siew Ming Lim","doi":"10.1109/IPFA55383.2022.9915778","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915778","url":null,"abstract":"Failure analysis in scale down devices becoming very much intricate by following Moore’s law concept for current technology trend. Thus, this indirectly bring a very challenging task for failure analyst (FA) to identify the real defect in complex integrated circuit effectively (IC). Metal insulator- metal (MIM) capacitor has become popular choice for designers to select in the different signal devices as it is well known to stabilize a voltage reduction that ultimately leads to drastically improved product and transistor performance [1]. In this paper, we did come out an excellent technique to isolate MIMCAP defects effectively by characterizing comprehensive phase angle measurement that can be performed by using Enhance Lock in Thermal Emission (ELITE) machine. Through the established fault isolation (FI) methods carried out, we can isolate the defect accuracy and physical failure analyst (PFA) is able to reveal the real defects in shorten time and achieve higher success rate in findings. This is mainly because MIMCAP is a very thin parasitic layer about 50X thinner than next metal layer that sandwiched in between top metal layer 1 and top metal layer 0 which PFA might missed out during inspection by following conventional PFA approached to find out the defects.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133795009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915743
Edward Bryan T. Pineda
Soft defect failures are challenging, especially when dealing with the bias condition at the specific failing temperature. Fault localization of temperature-dependent digital circuit functional failures utilizing the scan-based bench Testing and the Dynamic Analysis by Laser Simulation (DALS) will employ a failure analysis flow based on the dynamic power dissipation theory. This study presents an alternative approach to solving temperature-dependent failures using the power dissipation equation by varying variables like voltage supply level and frequency or the speed instead of varying the temperature. The design principles of scan-based testing, which the design engineers utilize during the initial manufacturing phase, were used to solve failures on the digital block. During fault localization, the laser scanning microscope provides a temperature change proportional to the temperature dependency of the failing device. The objective is to bring the device to the failing state whenever the laser scans across the temperature-sensitive area of the die. The study showcases failure analysis cases that showed a significant improvement in the level of the analysis process, a drastic cycle time reduction in the analysis, and an almost 100% success rate in identifying the root cause compared with the conventional analysis.
{"title":"Fault Localization of Temperature-Dependent Digital Circuit Functional Failures Utilizing the Scan-based Bench Testing and the Dynamic Analysis by Laser Simulation (DALS)","authors":"Edward Bryan T. Pineda","doi":"10.1109/IPFA55383.2022.9915743","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915743","url":null,"abstract":"Soft defect failures are challenging, especially when dealing with the bias condition at the specific failing temperature. Fault localization of temperature-dependent digital circuit functional failures utilizing the scan-based bench Testing and the Dynamic Analysis by Laser Simulation (DALS) will employ a failure analysis flow based on the dynamic power dissipation theory. This study presents an alternative approach to solving temperature-dependent failures using the power dissipation equation by varying variables like voltage supply level and frequency or the speed instead of varying the temperature. The design principles of scan-based testing, which the design engineers utilize during the initial manufacturing phase, were used to solve failures on the digital block. During fault localization, the laser scanning microscope provides a temperature change proportional to the temperature dependency of the failing device. The objective is to bring the device to the failing state whenever the laser scans across the temperature-sensitive area of the die. The study showcases failure analysis cases that showed a significant improvement in the level of the analysis process, a drastic cycle time reduction in the analysis, and an almost 100% success rate in identifying the root cause compared with the conventional analysis.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133844611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915736
Jack Yi Jie Ng, Kok Heng Lau, C. N. Liew, L.L. Goh, Chia-Li Song, Lee Kean Yong
This paper presents two case studies, which are based on 10nm Field Programmable Logic Array (FPGA) technology, to highlight the approach of defect localization for scan Automated Test Pattern Generation (ATPG) failure through additional layout aware analysis, and the combination of layout study, photon emission analysis (PEM), parallel lapping, nanoprobing and Scanning Emission Microscope (SEM) inspection.
{"title":"Effective Defect Localization for Scan ATPG Failure through Layout Aware Analysis","authors":"Jack Yi Jie Ng, Kok Heng Lau, C. N. Liew, L.L. Goh, Chia-Li Song, Lee Kean Yong","doi":"10.1109/IPFA55383.2022.9915736","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915736","url":null,"abstract":"This paper presents two case studies, which are based on 10nm Field Programmable Logic Array (FPGA) technology, to highlight the approach of defect localization for scan Automated Test Pattern Generation (ATPG) failure through additional layout aware analysis, and the combination of layout study, photon emission analysis (PEM), parallel lapping, nanoprobing and Scanning Emission Microscope (SEM) inspection.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125533511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915744
P. T. Ng, F. Rivai, A. Quah, J. C. Alag, P. K. Tan, C. Q. Chen
Electron Beam (EB) irradiation with high acceleration voltage is widely reported to cause significant degradation on transistor parametric performance. Thus, low acceleration voltage EB is preferred in standard failure analysis process to minimize these unwanted transistors degradations, in the expense of poorer SEM image resolution. Unknowingly, these undesirable high voltage EB effects can be leveraged for good use to enhance the EBAC detection on Gate Oxide breakdown defects. In this paper, two successful case studies on P-type and N-type MOSFET gate oxide defect isolation were described to demonstrate this enhancement through the suppression on the gate leakage by high voltage EB induced charge trapping mechanism.
{"title":"Enhanced EBAC Detection on Gate Oxide Breakdown Isolation after High Voltage Electron Beam Irradiation","authors":"P. T. Ng, F. Rivai, A. Quah, J. C. Alag, P. K. Tan, C. Q. Chen","doi":"10.1109/IPFA55383.2022.9915744","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915744","url":null,"abstract":"Electron Beam (EB) irradiation with high acceleration voltage is widely reported to cause significant degradation on transistor parametric performance. Thus, low acceleration voltage EB is preferred in standard failure analysis process to minimize these unwanted transistors degradations, in the expense of poorer SEM image resolution. Unknowingly, these undesirable high voltage EB effects can be leveraged for good use to enhance the EBAC detection on Gate Oxide breakdown defects. In this paper, two successful case studies on P-type and N-type MOSFET gate oxide defect isolation were described to demonstrate this enhancement through the suppression on the gate leakage by high voltage EB induced charge trapping mechanism.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129240183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As an increasing number of Commercial-Off-the-Shelf (COTS) integrated circuits are employed in space missions, radiation-induced failures become an obvious risk to these missions. Various radiation effects on COTS in space applications are reviewed and discussed. Among various radiation effects, Single Event Latchup (SEL) and Single Event Upset (SEU) are the two most critical effects severely impacting power reliability and data integrity of COTS, respectively. To protect COTS in space missions against these radiation-induced failures, a design philosophy is proposed in this paper, with the aim of fundamentally ascertaining power reliability and data integrity. The design philosophy embodies two radiation hardened products, LDAP (Latchup Detection And Protection) and Voter, which are invented and produced by Zero-Error Systems. Specifically, LDAP serves to intelligently detect the occurrence of SEL and rapidly mitigate it by power cycling, hence enhancing power reliability. Voter, on the other hand, serves as the last checkpoint of a Triple Modular Redundancy system and mitigates SEU by always outputting the correct data, hence improving data integrity. The proposed design philosophy embodying LDAP and Voter collectively and significantly enhances COTS’ reliability, desirably allowing satellite manufacturers to select and employ COTS freely.
{"title":"Radiation-Induced Failures for Integrated Circuits in Space and Design Philosophy","authors":"Yuchen He, Junkai Zhao, Juanda, Wei Shu, Kwen-Siong Chong, Joseph Chang","doi":"10.1109/IPFA55383.2022.9915726","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915726","url":null,"abstract":"As an increasing number of Commercial-Off-the-Shelf (COTS) integrated circuits are employed in space missions, radiation-induced failures become an obvious risk to these missions. Various radiation effects on COTS in space applications are reviewed and discussed. Among various radiation effects, Single Event Latchup (SEL) and Single Event Upset (SEU) are the two most critical effects severely impacting power reliability and data integrity of COTS, respectively. To protect COTS in space missions against these radiation-induced failures, a design philosophy is proposed in this paper, with the aim of fundamentally ascertaining power reliability and data integrity. The design philosophy embodies two radiation hardened products, LDAP (Latchup Detection And Protection) and Voter, which are invented and produced by Zero-Error Systems. Specifically, LDAP serves to intelligently detect the occurrence of SEL and rapidly mitigate it by power cycling, hence enhancing power reliability. Voter, on the other hand, serves as the last checkpoint of a Triple Modular Redundancy system and mitigates SEU by always outputting the correct data, hence improving data integrity. The proposed design philosophy embodying LDAP and Voter collectively and significantly enhances COTS’ reliability, desirably allowing satellite manufacturers to select and employ COTS freely.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121111939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915742
Xiangyu Liu, Yongsheng Sun, Junlin Huang, Xiaolu Shang, Changze Liu
In this work, TDDB characteristics in sub-16nm FinFET technology are investigated. The MTTF of N/PMOSFET under AC stress increases about one order of magnitude compared with the DC results under same voltage and the AC margin of N/PMOSFET are equal to 85mV and 89mV based on the fitting voltage coefficient. The TDDB characteristics under off-state stress are studied, the results indicate that the MTTF of NMOSFET in on-state and PMOSFET in off-state is lower since the majority carriers in the channel. Moreover, the dependence of on-state TDDB on Vds is studied and the results indicate that the MTTF increases first and then decreases with the increment of Vds.
{"title":"Gate oxide TDDB reliability under various stress in sub-16nm FinFET technology","authors":"Xiangyu Liu, Yongsheng Sun, Junlin Huang, Xiaolu Shang, Changze Liu","doi":"10.1109/IPFA55383.2022.9915742","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915742","url":null,"abstract":"In this work, TDDB characteristics in sub-16nm FinFET technology are investigated. The MTTF of N/PMOSFET under AC stress increases about one order of magnitude compared with the DC results under same voltage and the AC margin of N/PMOSFET are equal to 85mV and 89mV based on the fitting voltage coefficient. The TDDB characteristics under off-state stress are studied, the results indicate that the MTTF of NMOSFET in on-state and PMOSFET in off-state is lower since the majority carriers in the channel. Moreover, the dependence of on-state TDDB on Vds is studied and the results indicate that the MTTF increases first and then decreases with the increment of Vds.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122286867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915719
Guangan Yang, Ting-Hui Huang, Wangran Wu, Hao Tian, Zuoxu Yu, Siyang Liu, Weifeng Sun
We fabricated the a-IGZO transistors with the symmetrical stair gate-dielectric structure. The electrical properties of the studied devices are examined in detail. Both the source and drain breakdown voltage (VBD, GS and VBD, GD) of over 60 V are obtained with the Lstair of 3 μm. It is observed that the threshold voltage (Vth) and subthreshold voltage have a negligible variation with the length of the stair region (Lstair). The transconductance (gm) slightly decreases with the Lstair because the gate capacitance is smaller in the device with the symmetrical stair structure. The distribution of the on-resistance (Ron) of the stair region (Mstair) is demonstrated. The simulation is performed to further understand the operation mechanism of the symmetrical stair structure a-IGZO TFTs.
{"title":"High-Voltage a-IGZO Thin Film Transistor with the Symmetrical Stair Gate-Dielectric Structure","authors":"Guangan Yang, Ting-Hui Huang, Wangran Wu, Hao Tian, Zuoxu Yu, Siyang Liu, Weifeng Sun","doi":"10.1109/IPFA55383.2022.9915719","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915719","url":null,"abstract":"We fabricated the a-IGZO transistors with the symmetrical stair gate-dielectric structure. The electrical properties of the studied devices are examined in detail. Both the source and drain breakdown voltage (V<inf>BD, GS</inf> and V<inf>BD, GD</inf>) of over 60 V are obtained with the L<inf>stair</inf> of 3 μm. It is observed that the threshold voltage (V<inf>th</inf>) and subthreshold voltage have a negligible variation with the length of the stair region (L<inf>stair</inf>). The transconductance (g<inf>m</inf>) slightly decreases with the L<inf>stair</inf> because the gate capacitance is smaller in the device with the symmetrical stair structure. The distribution of the on-resistance (R<inf>on</inf>) of the stair region (M<inf>stair</inf>) is demonstrated. The simulation is performed to further understand the operation mechanism of the symmetrical stair structure a-IGZO TFTs.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121563398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, to the best of our knowledge, it is the first time to report the high-frequency switching stabilities (up to 300kHz) under a 800V of Vds during hard switching (HSW) and zero voltage switching (ZVS) operations in SiC power devices. The switching dependencies, i.e., temperature, frequency, current, and duty cycle, are evaluated based on the proposed topology, showing the flexible design to effectively investigate the circuit-level switching stability. Furthermore, the high-frequency switching stability in GaN power devices is also evaluated for the comparison, indicating that SiC power device shows a better Rdson stability under ZVS and HSW during the high-frequency switching.
{"title":"Comprehensive Investigation of the Switching Stability in SiC and GaN Power Devices","authors":"Shun-Wei Tang, Chao-Ta Fan, Ming-Cheng Lin, Tian-Li Wu","doi":"10.1109/IPFA55383.2022.9915772","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915772","url":null,"abstract":"In this work, to the best of our knowledge, it is the first time to report the high-frequency switching stabilities (up to 300kHz) under a 800V of Vds during hard switching (HSW) and zero voltage switching (ZVS) operations in SiC power devices. The switching dependencies, i.e., temperature, frequency, current, and duty cycle, are evaluated based on the proposed topology, showing the flexible design to effectively investigate the circuit-level switching stability. Furthermore, the high-frequency switching stability in GaN power devices is also evaluated for the comparison, indicating that SiC power device shows a better Rdson stability under ZVS and HSW during the high-frequency switching.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132857464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915759
L. Magnarin, M. Agati, A. Belmonte, S. Subhechha, N. Rassoul, C. Drijbooms, H. Dekkers, U. Celano
We report on a custom sample preparation flow for correlative metrology. This is applied here to the electrical, structural, and compositional analysis of Indium-Gallium-Zinc- Oxide thin film transistors (IGZO TFTs). Here, conductive atomic force microscopy (C-AFM) and transmission electron microscopy (TEM) are repeatedly combined on the same structure to maximize the amount of site-specific device information. First, the analysis-flow is described in detail, describing the specimen preparation that enables both electron transparency and mechanical stability. Second, the direct correlation of structural and electrical information is provided with emphasis on the channel and contacts regions, where additional insights are provided by combining multiple measurement techniques. This opens new possibilities in the evaluation of process development for complex samples, well beyond what is reported here.
{"title":"A Correlative Analysis Flow for Electrical and Structural Characterization of IGZO Transistors","authors":"L. Magnarin, M. Agati, A. Belmonte, S. Subhechha, N. Rassoul, C. Drijbooms, H. Dekkers, U. Celano","doi":"10.1109/IPFA55383.2022.9915759","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915759","url":null,"abstract":"We report on a custom sample preparation flow for correlative metrology. This is applied here to the electrical, structural, and compositional analysis of Indium-Gallium-Zinc- Oxide thin film transistors (IGZO TFTs). Here, conductive atomic force microscopy (C-AFM) and transmission electron microscopy (TEM) are repeatedly combined on the same structure to maximize the amount of site-specific device information. First, the analysis-flow is described in detail, describing the specimen preparation that enables both electron transparency and mechanical stability. Second, the direct correlation of structural and electrical information is provided with emphasis on the channel and contacts regions, where additional insights are provided by combining multiple measurement techniques. This opens new possibilities in the evaluation of process development for complex samples, well beyond what is reported here.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127748110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：