Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915710
Jian-Hsing Lee, K. Nidhi, Tingyou Lin, Hsueh-Chun Liao, Scott Lee, M. Ker
The mechanism of electrostatic-discharge (ESD) performance discrepancy between the floating gate and grounded-gate NMOS power transistors is analyzed in this work. A power transistor uses the bipolar current to discharge ESD current as the gate is grounded, while the channel current to discharge ESD current as the gate is floating since the gate voltage is couped up by the ESD. Under the time-varying ESD current induced magnetic field (B), the Lorentz force (J×B) has the less effect on the channel current of power transistor since it is controlled by the gate electric field. However, the Lorentz force can push the bipolar current to the finger edge of power transistor as all electrons are the free electrons after injected from the source into the p-substrate from the TCAD simulation. This is different from the classic model that ESD couples up the gate voltage of the floating-gate NMOS to turn-on all channels to give rise to the substrate currents on whole drain junction. So, the current crowded at the first turn-on region is prevented.
{"title":"Analyze the ESD Discrepancy between Grounded-Gate and Floating-Gate Power Transistors with Gate Electric Field and Magnetic Field Induced by ESD","authors":"Jian-Hsing Lee, K. Nidhi, Tingyou Lin, Hsueh-Chun Liao, Scott Lee, M. Ker","doi":"10.1109/IPFA55383.2022.9915710","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915710","url":null,"abstract":"The mechanism of electrostatic-discharge (ESD) performance discrepancy between the floating gate and grounded-gate NMOS power transistors is analyzed in this work. A power transistor uses the bipolar current to discharge ESD current as the gate is grounded, while the channel current to discharge ESD current as the gate is floating since the gate voltage is couped up by the ESD. Under the time-varying ESD current induced magnetic field (B), the Lorentz force (J×B) has the less effect on the channel current of power transistor since it is controlled by the gate electric field. However, the Lorentz force can push the bipolar current to the finger edge of power transistor as all electrons are the free electrons after injected from the source into the p-substrate from the TCAD simulation. This is different from the classic model that ESD couples up the gate voltage of the floating-gate NMOS to turn-on all channels to give rise to the substrate currents on whole drain junction. So, the current crowded at the first turn-on region is prevented.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116438345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915708
Hee-Beom Lee, M. Ishimaru, J. Mcphillips, R. Alvis, Timothy A. Johnson, C. H. Kang, Inchang Choi, Youngjin Cho, Kiju Choi
A high stack structure is being developed to increase the 3D NAND Flash storage capacity. However, problems such as bowing, incomplete etching, and twisting occur during the channel hole etching process. For the analysis of these process problems, cross-sectional analysis of devices with high stacks is essential.However, it is difficult to uniformly measure the top and bottom layers of the source line contact and V-NAND string area. Therefore, distortion occurs through cross section analysis. The reasons include the focused ion beam incident beam angle relative to the sample coordinate system, beam current profile, and differential milling.The listed physical parameters can be adjusted in a way to obtain distortion-improved, uniform, and perpendicular image data; however, this time-consuming task is a hindrance when trying to increase the reliability of the analysis.In order to address this problem, we propose an efficient processing technique, abbreviated tomography, which is an efficient data reconstruction method.In this study, 248 images were prepared to set up the tomography algorithm data set. The data was reconstructed in a significantly reduced time using the abbreviated tomography technique. Although it took an average of 5 h to obtain 248 new 2D images, we were able to reconstruct the data in 4 min using the abbreviated tomography technique. This abbreviated tomography algorithm can be used as an efficient reconstruction tool for studying structure at the most basic level.
{"title":"Abbreviated tomography techniques for quick correction of slides in 3-Dimensional NAND Flash architectures","authors":"Hee-Beom Lee, M. Ishimaru, J. Mcphillips, R. Alvis, Timothy A. Johnson, C. H. Kang, Inchang Choi, Youngjin Cho, Kiju Choi","doi":"10.1109/IPFA55383.2022.9915708","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915708","url":null,"abstract":"A high stack structure is being developed to increase the 3D NAND Flash storage capacity. However, problems such as bowing, incomplete etching, and twisting occur during the channel hole etching process. For the analysis of these process problems, cross-sectional analysis of devices with high stacks is essential.However, it is difficult to uniformly measure the top and bottom layers of the source line contact and V-NAND string area. Therefore, distortion occurs through cross section analysis. The reasons include the focused ion beam incident beam angle relative to the sample coordinate system, beam current profile, and differential milling.The listed physical parameters can be adjusted in a way to obtain distortion-improved, uniform, and perpendicular image data; however, this time-consuming task is a hindrance when trying to increase the reliability of the analysis.In order to address this problem, we propose an efficient processing technique, abbreviated tomography, which is an efficient data reconstruction method.In this study, 248 images were prepared to set up the tomography algorithm data set. The data was reconstructed in a significantly reduced time using the abbreviated tomography technique. Although it took an average of 5 h to obtain 248 new 2D images, we were able to reconstruct the data in 4 min using the abbreviated tomography technique. This abbreviated tomography algorithm can be used as an efficient reconstruction tool for studying structure at the most basic level.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122703029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915748
I. Matacena, L. Maresca, M. Riccio, A. Irace, G. Breglio, A. Castellazzi, S. Daliento
In this paper the effects of SiC/SiO2 interface traps on SiC MOSFETs Gate Capacitance are investigated when a positive bias is applied at the Drain terminal. The Gate capacitance arising from this configuration shows an unexpected sharp peak, exceeding the oxide capacitance, for a Gate voltage close to the threshold voltage. The properties of such peak are studied through numerical analysis. Results affirm that the peak is related to the displacement current, and its origin lies in the channel region. The so-measured Gate capacitance can allow the extraction of important interface properties, such as traps concentration at the SiC/SiO2 interface. Also the effects of temperature on this peak are investigated through experimental and numerical analysis
{"title":"SiC/SiO2 interface traps effect on SiC MOSFETs Gate capacitance with biased Drain","authors":"I. Matacena, L. Maresca, M. Riccio, A. Irace, G. Breglio, A. Castellazzi, S. Daliento","doi":"10.1109/IPFA55383.2022.9915748","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915748","url":null,"abstract":"In this paper the effects of SiC/SiO2 interface traps on SiC MOSFETs Gate Capacitance are investigated when a positive bias is applied at the Drain terminal. The Gate capacitance arising from this configuration shows an unexpected sharp peak, exceeding the oxide capacitance, for a Gate voltage close to the threshold voltage. The properties of such peak are studied through numerical analysis. Results affirm that the peak is related to the displacement current, and its origin lies in the channel region. The so-measured Gate capacitance can allow the extraction of important interface properties, such as traps concentration at the SiC/SiO2 interface. Also the effects of temperature on this peak are investigated through experimental and numerical analysis","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123346581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915764
J. Bow, Jay Wang, W. Lai, Tien Y. Wang, Syuan-Yu Sie, Sheng-Po Chang, C. Kuo, J. Sheu
Optoelectrical properties of AlGaN-based DUV LEDs were improved by forming gallium oxide and aluminum-gallium oxide layers around sidewalls of GaN and AlGaN epitaxial layers by thermal annealing at temperature high than 850°C. Microstructure of oxide layers were investigated by TEM. Three oxide phases are observed on GaN and AlGaN epitaxial layers. They are all identified to be crystalline phases, one dense and two porous, by SADPs and TEM/STEM images. Combined with data of STEM/EDS analysis, these oxides are designated to be Ga2O3(I), Ga2O3(II), AlxGa2-xO3(I) and AlxGa2-xO3(II) respectively. The gallium oxide is suspected to be β-Ga2O3 by comparing experimental SADPs with simulated SADPs.
{"title":"Characterization of Oxide Layers on AlGaN Based DUV LEDs by TEM/STEM Analysis","authors":"J. Bow, Jay Wang, W. Lai, Tien Y. Wang, Syuan-Yu Sie, Sheng-Po Chang, C. Kuo, J. Sheu","doi":"10.1109/IPFA55383.2022.9915764","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915764","url":null,"abstract":"Optoelectrical properties of AlGaN-based DUV LEDs were improved by forming gallium oxide and aluminum-gallium oxide layers around sidewalls of GaN and AlGaN epitaxial layers by thermal annealing at temperature high than 850°C. Microstructure of oxide layers were investigated by TEM. Three oxide phases are observed on GaN and AlGaN epitaxial layers. They are all identified to be crystalline phases, one dense and two porous, by SADPs and TEM/STEM images. Combined with data of STEM/EDS analysis, these oxides are designated to be Ga2O3(I), Ga2O3(II), AlxGa2-xO3(I) and AlxGa2-xO3(II) respectively. The gallium oxide is suspected to be β-Ga2O3 by comparing experimental SADPs with simulated SADPs.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122878666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915784
S. L. Ting, P. K. Tan, M. Seungje, J. C. Alag, Yanlin Pan, Hnin Hnin, T. T. Yu, K. Kang, A. Quah, C. Chen
The evolution of packaging requirements and innovations drives the constant need for improvement in package level failure analysis. For silicon backside dynamic electrical fault isolation, partial decapsulation is done to remove signal blocking materials and assess the silicon backside of the chip, while maintaining the electrical components and connections of the package. The control of such selective backside opening technique is an intricate process. Any damage can easily be induced to the package connections and silicon substrate without proper control. In this paper, we introduce a novel method with the combination of laser ablation and chemical etch to selectively open die in QFN packages where the package backside is a metallic Cu heatsink.
{"title":"A novel method combining laser ablation and chemical etch to expose packaged silicon backside for electrical fault isolation","authors":"S. L. Ting, P. K. Tan, M. Seungje, J. C. Alag, Yanlin Pan, Hnin Hnin, T. T. Yu, K. Kang, A. Quah, C. Chen","doi":"10.1109/IPFA55383.2022.9915784","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915784","url":null,"abstract":"The evolution of packaging requirements and innovations drives the constant need for improvement in package level failure analysis. For silicon backside dynamic electrical fault isolation, partial decapsulation is done to remove signal blocking materials and assess the silicon backside of the chip, while maintaining the electrical components and connections of the package. The control of such selective backside opening technique is an intricate process. Any damage can easily be induced to the package connections and silicon substrate without proper control. In this paper, we introduce a novel method with the combination of laser ablation and chemical etch to selectively open die in QFN packages where the package backside is a metallic Cu heatsink.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"94 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120852920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915769
C. Bergès, J. Bird, M. Shroff, Edwin Lumanauw, Sreerag Raghunathan, Chris Smith
Big-data infrastructure and environment enable the ability to connect and store data to develop and deploy machine-learning activities and analysis in various industries. Equipment manufacturers are implementing new artificial-intelligence capabilities on their tool platforms, thus pushing manufacturers themselves to use data provided by these new functionalities and to link them with other data from their processes. Then, the manufacturer who uses this new artificial-intelligence data is seeking to connect them to some other of internal data, such as the electrical test results per die, in a new type of analysis, with the purpose to improve the screening offered by the electrical test, and thus to increase overall quality. This paper reports new capabilities in automated optical inspection, implemented in automotive-semiconductor manufacturing, which predict a probability of failure per die, computed by the inspection equipment from the features of the observed defects, and presents some significant results in the case of a product implemented in automotive RADAR products.
{"title":"Inspection methodologies and machine-learning approaches for defectivity data in semiconductor industry for automotive applications: case study for field-failure prevention","authors":"C. Bergès, J. Bird, M. Shroff, Edwin Lumanauw, Sreerag Raghunathan, Chris Smith","doi":"10.1109/IPFA55383.2022.9915769","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915769","url":null,"abstract":"Big-data infrastructure and environment enable the ability to connect and store data to develop and deploy machine-learning activities and analysis in various industries. Equipment manufacturers are implementing new artificial-intelligence capabilities on their tool platforms, thus pushing manufacturers themselves to use data provided by these new functionalities and to link them with other data from their processes. Then, the manufacturer who uses this new artificial-intelligence data is seeking to connect them to some other of internal data, such as the electrical test results per die, in a new type of analysis, with the purpose to improve the screening offered by the electrical test, and thus to increase overall quality. This paper reports new capabilities in automated optical inspection, implemented in automotive-semiconductor manufacturing, which predict a probability of failure per die, computed by the inspection equipment from the features of the observed defects, and presents some significant results in the case of a product implemented in automotive RADAR products.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124213981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915755
F. Su, Ray Tu, W. Hsieh, Henry Lin, Vincent Chen, Irene Ou, Y. Lou
In this paper, an aluminum pad discoloration was observed for the wafers stored for more than one year after the CP testing process. The OM, SEM, EDS, AES and TEM analysis technique were used to identify the mechanism of Al pad discoloration. The Pt thin film deposition on top surface of Al pad can effectively enhance the visibility of discoloration. Based on HRTEM, FFT and NBD analysis results, this Al pad discoloration was characterized by the formation of fluorine containing crystalline defects on entire Al pad surface. Additionally, in order to monitor contaminants in Front Opening Shipping Box (FOSB), the ion chromatography analysis technique was introduced into routine wafer storage management of CP testing FAB.
{"title":"Characterization analysis of aluminum pad discoloration and ions contamination monitor of wafer storage environment","authors":"F. Su, Ray Tu, W. Hsieh, Henry Lin, Vincent Chen, Irene Ou, Y. Lou","doi":"10.1109/IPFA55383.2022.9915755","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915755","url":null,"abstract":"In this paper, an aluminum pad discoloration was observed for the wafers stored for more than one year after the CP testing process. The OM, SEM, EDS, AES and TEM analysis technique were used to identify the mechanism of Al pad discoloration. The Pt thin film deposition on top surface of Al pad can effectively enhance the visibility of discoloration. Based on HRTEM, FFT and NBD analysis results, this Al pad discoloration was characterized by the formation of fluorine containing crystalline defects on entire Al pad surface. Additionally, in order to monitor contaminants in Front Opening Shipping Box (FOSB), the ion chromatography analysis technique was introduced into routine wafer storage management of CP testing FAB.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126517655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915786
Younan Hua, Jin Liao, Binhai Liu, Lei Zhu, Xiaomin Li
In wafer fabrication, silicon nitride (Si3N4) and silicon oxide (SiO2) layers are widely used as passivation layer to protect the Al metal underneath from corrosion. To qualify the passivation layers, the traditional chemical recipe PAE (H3PO4 + HNO3) is used to conduct passivation pinhole test. If pinholes or cracks are present in the passivation layer of Si3N4/SiO2, the sample immersion in the test solution duration will allow HNO3 acid to chemically react with the Al layer underneath. Therefore, a black colored pinhole-like defect will be observed during optical inspection after the pinhole test. In this situation, the wafer sample fails the pinhole test and is not qualified.If there is no pinhole or crack in the passivation layers of Si3N4/SiO2, after the sample immersion in the testing solution time, HNO3 acid cannot chemically react with the underneath aluminum layer. The black pinhole-like defect during optical inspection is unable to be detected, and the wafer sample passes the pinhole test. However, this traditional method has its limitation. If the pinholes or cracks do not completely penetrate the entire passivation layer, in this case HNO3 acid cannot flow into the pinholes or cracks and could not chemically react with the underlying aluminum. As a result, those pinholes or cracks could not be detected.In this study, we proposed a new test method to replace the traditional pinhole test method by using fluorescent dye method. We have developed a fluorescence microscopy method which can be applied to qualify the passivation layer. Using this new method, we could detect pinholes/cracks in passivation layer in wafer fabrication which had totally or partially penetrate the entire passivation (Si3N4/SiO2) layer. The smallest microcrack size currently detected can reach 72nm. All micro-pinhole defects can be detected by fluorescence microscopy method, which can detect not only full perforation defects, but also those partially perforated defects.
{"title":"Studies of Passivation (Si3N4/SiO2) Qualification Method in Wafer Fabrication","authors":"Younan Hua, Jin Liao, Binhai Liu, Lei Zhu, Xiaomin Li","doi":"10.1109/IPFA55383.2022.9915786","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915786","url":null,"abstract":"In wafer fabrication, silicon nitride (Si3N4) and silicon oxide (SiO2) layers are widely used as passivation layer to protect the Al metal underneath from corrosion. To qualify the passivation layers, the traditional chemical recipe PAE (H3PO4 + HNO3) is used to conduct passivation pinhole test. If pinholes or cracks are present in the passivation layer of Si3N4/SiO2, the sample immersion in the test solution duration will allow HNO3 acid to chemically react with the Al layer underneath. Therefore, a black colored pinhole-like defect will be observed during optical inspection after the pinhole test. In this situation, the wafer sample fails the pinhole test and is not qualified.If there is no pinhole or crack in the passivation layers of Si3N4/SiO2, after the sample immersion in the testing solution time, HNO3 acid cannot chemically react with the underneath aluminum layer. The black pinhole-like defect during optical inspection is unable to be detected, and the wafer sample passes the pinhole test. However, this traditional method has its limitation. If the pinholes or cracks do not completely penetrate the entire passivation layer, in this case HNO3 acid cannot flow into the pinholes or cracks and could not chemically react with the underlying aluminum. As a result, those pinholes or cracks could not be detected.In this study, we proposed a new test method to replace the traditional pinhole test method by using fluorescent dye method. We have developed a fluorescence microscopy method which can be applied to qualify the passivation layer. Using this new method, we could detect pinholes/cracks in passivation layer in wafer fabrication which had totally or partially penetrate the entire passivation (Si3N4/SiO2) layer. The smallest microcrack size currently detected can reach 72nm. All micro-pinhole defects can be detected by fluorescence microscopy method, which can detect not only full perforation defects, but also those partially perforated defects.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132018817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915707
Xuanlong Chen, Xiaping Xie, Min Wang, Yongjia Ruan, Tianhan Liu, Lin Shi
The semiconductor assembly industry has migrated from Au wire to Cu wire, and has recently started with Ag alloy wire, due to the advantages of higher conductivity, lower price and hardness. With this paper, we reviewed several failure mechanisms of commercial silver wire bonding ICs operating in real life applications. The analyzed failure mechanisms are mainly due to: (1) pad cratering, (2) electrochemical migration, (3) chemical corrosion, (4) wire bridge. The results give a guidance on the improvement of the reliability and robustness of plastic encapsulated ICs using Ag wire.
{"title":"Failures of Ag Wire Bonding ICs in Real-world Applications","authors":"Xuanlong Chen, Xiaping Xie, Min Wang, Yongjia Ruan, Tianhan Liu, Lin Shi","doi":"10.1109/IPFA55383.2022.9915707","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915707","url":null,"abstract":"The semiconductor assembly industry has migrated from Au wire to Cu wire, and has recently started with Ag alloy wire, due to the advantages of higher conductivity, lower price and hardness. With this paper, we reviewed several failure mechanisms of commercial silver wire bonding ICs operating in real life applications. The analyzed failure mechanisms are mainly due to: (1) pad cratering, (2) electrochemical migration, (3) chemical corrosion, (4) wire bridge. The results give a guidance on the improvement of the reliability and robustness of plastic encapsulated ICs using Ag wire.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"119 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133157687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915762
H. Ceric, R. L. de Orio, S. Selberherr
Gold metallization used for GaAs devices is susceptible to significant electromigration degradation. In this work, a complete physics-based analysis of electromigration in gold is presented. In particular, the dependence of statistical failure features on the variation of geometric properties is investigated. The experimentally observed dependence of the mean failure time and the associated standard deviation of the failure times on the interconnect geometry is well reproduced by simulations.
{"title":"Statistical Study of Electromigration in Gold Interconnects","authors":"H. Ceric, R. L. de Orio, S. Selberherr","doi":"10.1109/IPFA55383.2022.9915762","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915762","url":null,"abstract":"Gold metallization used for GaAs devices is susceptible to significant electromigration degradation. In this work, a complete physics-based analysis of electromigration in gold is presented. In particular, the dependence of statistical failure features on the variation of geometric properties is investigated. The experimentally observed dependence of the mean failure time and the associated standard deviation of the failure times on the interconnect geometry is well reproduced by simulations.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121762663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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