Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915758
Jinzhi Lois Liao, Bisheng Wang, Xi Zhang, Younan Hua, Xiaomin Li
Currently, wire bonding is still the dominant interconnection mode in microelectronic packaging. Copper (Cu) bonding wire is widely used due to its advantages, such as low-cost and good electrical conductivity. However, Cu wire bond is susceptible to galvanic corrosion. It is well known that Cu wire bond corrosion with the presence of moisture and chlorine (Cl). However, there is few reports on Cl effect on Cu wire bond at elevated temperature.This paper discusses the influence of Cl effect on the Cu wire bond. Different contents of Cl were purposely added into the epoxy molding compound (EMC). Accelerated reliability tests biased highly accelerated stress test (bHAST), temperature humidity ubias test (THT), and high temperature storage test (HTS) were conducted. The purpose is to compare the Cl effect on Cu wire bond reliability under different environments (i.e. temperature, humidity, voltage). It is found that Cl acted as a catalyst in IMC corrosion under humid environment. Cl also caused wire bond failure in HTS test if the Cl content is high. This work can serve as a reference to semiconductor engineers and scientist who use Cu wire bond.
{"title":"Chlorine effect on copper bonding wire reliability","authors":"Jinzhi Lois Liao, Bisheng Wang, Xi Zhang, Younan Hua, Xiaomin Li","doi":"10.1109/IPFA55383.2022.9915758","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915758","url":null,"abstract":"Currently, wire bonding is still the dominant interconnection mode in microelectronic packaging. Copper (Cu) bonding wire is widely used due to its advantages, such as low-cost and good electrical conductivity. However, Cu wire bond is susceptible to galvanic corrosion. It is well known that Cu wire bond corrosion with the presence of moisture and chlorine (Cl). However, there is few reports on Cl effect on Cu wire bond at elevated temperature.This paper discusses the influence of Cl effect on the Cu wire bond. Different contents of Cl were purposely added into the epoxy molding compound (EMC). Accelerated reliability tests biased highly accelerated stress test (bHAST), temperature humidity ubias test (THT), and high temperature storage test (HTS) were conducted. The purpose is to compare the Cl effect on Cu wire bond reliability under different environments (i.e. temperature, humidity, voltage). It is found that Cl acted as a catalyst in IMC corrosion under humid environment. Cl also caused wire bond failure in HTS test if the Cl content is high. This work can serve as a reference to semiconductor engineers and scientist who use Cu wire bond.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114298408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915757
Rui Zhen Tan, N. Venkatarayalu, I. Atmosukarto, A. Premkumar, Tict Eng Teh, K. K. Thinn, Ming Xue
Lock-in Thermography (LIT) is a non-destructive technique in the failure analysis (FA) of integrated circuits (ICs). In diagnosing the cause of failure, a FA specialist spends a long time searching through a repository of historical images. In this paper, a supervised image retrieval and ranking algorithm incorporating image similarity and classification has been developed. Features are extracted from the images by passing them through the pre-trained VGG16 network. Principal component analysis (PCA) is then performed to identify 100 significant components that serve as signatures for each image and for computing Euclidean distance as the similarity metric. Next, a two-layer classifier replicating the human judgment process has been developed. The first layer of the classifier differentiates whether the query image is taken at the package or die level, whereas the second layer identifies the package or device class of the image. By analyzing the query image through the classifier, its classes in the two layers are determined. The distances of database images belonging to the same classes as the query image are reduced, shifting them ahead. The images thus sorted and ranked are recommended. The algorithm was tested on a dataset of 372 images of which 298 images were used for database construction, and 74 images were used as queried images. The incorporation of class classification improved the precision rate by recommending more images belonging to the same classes as the query.
{"title":"Supervised Image Retrieval and Ranking Technique for Lock-in Thermography Images","authors":"Rui Zhen Tan, N. Venkatarayalu, I. Atmosukarto, A. Premkumar, Tict Eng Teh, K. K. Thinn, Ming Xue","doi":"10.1109/IPFA55383.2022.9915757","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915757","url":null,"abstract":"Lock-in Thermography (LIT) is a non-destructive technique in the failure analysis (FA) of integrated circuits (ICs). In diagnosing the cause of failure, a FA specialist spends a long time searching through a repository of historical images. In this paper, a supervised image retrieval and ranking algorithm incorporating image similarity and classification has been developed. Features are extracted from the images by passing them through the pre-trained VGG16 network. Principal component analysis (PCA) is then performed to identify 100 significant components that serve as signatures for each image and for computing Euclidean distance as the similarity metric. Next, a two-layer classifier replicating the human judgment process has been developed. The first layer of the classifier differentiates whether the query image is taken at the package or die level, whereas the second layer identifies the package or device class of the image. By analyzing the query image through the classifier, its classes in the two layers are determined. The distances of database images belonging to the same classes as the query image are reduced, shifting them ahead. The images thus sorted and ranked are recommended. The algorithm was tested on a dataset of 372 images of which 298 images were used for database construction, and 74 images were used as queried images. The incorporation of class classification improved the precision rate by recommending more images belonging to the same classes as the query.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124716352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915711
P. K. Tan, Y. L. Pan, S. L. Ting, A. Quah, Y. Tam, A. Teo, N. Xu, H. Thoungh, K. Kang, T. T. Yu, C. Q. Chen
Focused Ion Beam Circuit Edit (FIB-CE) is one of the most commonly used silicon (Si) debug tools that are often used in the semiconductor industry, especially for the new design prototype chip. With the expanding growth of semiconductor applications in different areas, such as next-generation smartphones, automotive, medical equipment, artificial intelligence, RF application, and high power devices, the new prototype chip demand has also increased. Hence, FIB-CE plays an important role in Si debugging for new designs or prototype chips. Among FIB-CE jobs in failure analysis (FA), circuit isolation is one of the common requests. This paper introduces a novel and simple cross-sectional FIB circuit edit (XFIB-CE) techniques for circuit isolation. This technique utilized a normal cross-sectional FIB as a method to cut and isolate the unwanted circuitry. Hence, it is an easier, simpler and more efficient alternative technique for FIB-CE circuit isolation as compared with the top-down FIB-CE milling technique.
{"title":"Novel and Simple Cross-sectional FIB Circuit Edit Techniques for Circuit Isolation","authors":"P. K. Tan, Y. L. Pan, S. L. Ting, A. Quah, Y. Tam, A. Teo, N. Xu, H. Thoungh, K. Kang, T. T. Yu, C. Q. Chen","doi":"10.1109/IPFA55383.2022.9915711","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915711","url":null,"abstract":"Focused Ion Beam Circuit Edit (FIB-CE) is one of the most commonly used silicon (Si) debug tools that are often used in the semiconductor industry, especially for the new design prototype chip. With the expanding growth of semiconductor applications in different areas, such as next-generation smartphones, automotive, medical equipment, artificial intelligence, RF application, and high power devices, the new prototype chip demand has also increased. Hence, FIB-CE plays an important role in Si debugging for new designs or prototype chips. Among FIB-CE jobs in failure analysis (FA), circuit isolation is one of the common requests. This paper introduces a novel and simple cross-sectional FIB circuit edit (XFIB-CE) techniques for circuit isolation. This technique utilized a normal cross-sectional FIB as a method to cut and isolate the unwanted circuitry. Hence, it is an easier, simpler and more efficient alternative technique for FIB-CE circuit isolation as compared with the top-down FIB-CE milling technique.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128488781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915774
Syahirah Zulkifli, Bernice Zee, M. Lo
This paper demonstrates the capability of submicron Optical PhotoThermal InfraRed (O-PTIR) spectroscopy in the chemical identification of semiconductor component failures during failure analysis which was otherwise limited by conventional Fourier Transform Infrared Spectroscopy (FTIR). In the case studies presented, O-PTIR could analyze imperfect sample surfaces of (1) a 5 μm narrow gap filled with strong infrared absorbers, and of (2) poorly reflective regions. The versatility of O-PTIR provides precise identification of material chemical identification to improve failure analysis capabilities of such challenging samples.
{"title":"Novel Submicron Spatial Resolution Infrared Microspectroscopy for Failure Analysis of Semiconductor Components","authors":"Syahirah Zulkifli, Bernice Zee, M. Lo","doi":"10.1109/IPFA55383.2022.9915774","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915774","url":null,"abstract":"This paper demonstrates the capability of submicron Optical PhotoThermal InfraRed (O-PTIR) spectroscopy in the chemical identification of semiconductor component failures during failure analysis which was otherwise limited by conventional Fourier Transform Infrared Spectroscopy (FTIR). In the case studies presented, O-PTIR could analyze imperfect sample surfaces of (1) a 5 μm narrow gap filled with strong infrared absorbers, and of (2) poorly reflective regions. The versatility of O-PTIR provides precise identification of material chemical identification to improve failure analysis capabilities of such challenging samples.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127153068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915751
N. J. Lagatic, Jerald Santos, Jonelle Mananguit
In some cases, even though a distinct emission (EMMI) hotspot localized by a Photo Emission (PEM) tool and in-depth circuit analysis have established a correlation between the electrical failure, it does not guarantee that a defect will be found exactly at the EMMI site location during physical analysis. Supplementary fault localization techniques such as powered and static micro-probing complemented by circuit editing using Focused-Ion Beam (FIB) and Passive Voltage Contrast (PVC) analysis are necessary to uncover the true defect behind an ambiguous distinct PEM hotspot. Two case studies are presented in this paper to demonstrate how these supplementary techniques were exploited to successfully determine the failure mechanism and root cause.
{"title":"Uncovering the True Defect Behind an Ambiguous Distinct PEM Hotspot Through Micro-Probing and FIB Circuit Edit-PVC Analysis","authors":"N. J. Lagatic, Jerald Santos, Jonelle Mananguit","doi":"10.1109/IPFA55383.2022.9915751","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915751","url":null,"abstract":"In some cases, even though a distinct emission (EMMI) hotspot localized by a Photo Emission (PEM) tool and in-depth circuit analysis have established a correlation between the electrical failure, it does not guarantee that a defect will be found exactly at the EMMI site location during physical analysis. Supplementary fault localization techniques such as powered and static micro-probing complemented by circuit editing using Focused-Ion Beam (FIB) and Passive Voltage Contrast (PVC) analysis are necessary to uncover the true defect behind an ambiguous distinct PEM hotspot. Two case studies are presented in this paper to demonstrate how these supplementary techniques were exploited to successfully determine the failure mechanism and root cause.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130843796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915781
S. Liu, Kuang Yuan Chao, H. Chou, Wen Sheng Wu
Laser voltage imaging (LVI) and laser voltage probing (LVP) are laser stimulation techniques to verify a device under test (DUT) and have been widely used for circuit debugging and various frequency-dependent failure modes [1] [2]. In this paper, a scan chain with timing failure study was demonstrated by using LVI and LVP techniques, and further physical failure analysis (PFA) found dislocations in bulk silicon by plan view transmission electron microscopy (TEM). However, on checking the depth of dislocations by 3D-TEM, only deep dislocations were found, and it was hard to explain the phenomenon of channel leakage.In this paper, it is not to introduce the methods for dislocation inspection. The major idea is how to distinguish the dislocations those would induce channel leakage. In this work, we presented a re-thinning technique for shallow dislocation inspection by using EasyLift [5]. The EasyLift system allowed operators to extract the lamella and attach it to a TEM grid, all within the dual beam FIB chamber. Because the lamella had attached to TEM grid, lamella re-thinning and acquisition of TEM images could be performed repeatedly [6]. Using this method makes it possible to partially remove the deep dislocations from bulk silicon and then perform 3D-TEM to acquire the actual depth of target of interest.
{"title":"The Application of 2nd Harmonic Laser Voltage Imaging for Timing Failure, Re-Thinning Techniques for Effective Dislocation Identification","authors":"S. Liu, Kuang Yuan Chao, H. Chou, Wen Sheng Wu","doi":"10.1109/IPFA55383.2022.9915781","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915781","url":null,"abstract":"Laser voltage imaging (LVI) and laser voltage probing (LVP) are laser stimulation techniques to verify a device under test (DUT) and have been widely used for circuit debugging and various frequency-dependent failure modes [1] [2]. In this paper, a scan chain with timing failure study was demonstrated by using LVI and LVP techniques, and further physical failure analysis (PFA) found dislocations in bulk silicon by plan view transmission electron microscopy (TEM). However, on checking the depth of dislocations by 3D-TEM, only deep dislocations were found, and it was hard to explain the phenomenon of channel leakage.In this paper, it is not to introduce the methods for dislocation inspection. The major idea is how to distinguish the dislocations those would induce channel leakage. In this work, we presented a re-thinning technique for shallow dislocation inspection by using EasyLift [5]. The EasyLift system allowed operators to extract the lamella and attach it to a TEM grid, all within the dual beam FIB chamber. Because the lamella had attached to TEM grid, lamella re-thinning and acquisition of TEM images could be performed repeatedly [6]. Using this method makes it possible to partially remove the deep dislocations from bulk silicon and then perform 3D-TEM to acquire the actual depth of target of interest.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125629170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915746
F. Rivai, S. L. Ting, P. T. Ng, A. Teo, A. Quah, P. K. Tan, C. Q. Chen
Junction profile anomalies are one of most challenging failures to localize as the abnormal junction profile is usually difficult to be visualized. Thus, typical failure process relies heavily on electrical characterization of the junction profiles to hypothesize the failure. In this paper, a case study was described to demonstrate the effective use of Cross-Section EBIC to reveal incoming substrate anomaly in the N-type epitaxy layer thickness resulting in product low yield.
{"title":"Application of Cross-Section EBIC to Localize Junction Anomaly","authors":"F. Rivai, S. L. Ting, P. T. Ng, A. Teo, A. Quah, P. K. Tan, C. Q. Chen","doi":"10.1109/IPFA55383.2022.9915746","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915746","url":null,"abstract":"Junction profile anomalies are one of most challenging failures to localize as the abnormal junction profile is usually difficult to be visualized. Thus, typical failure process relies heavily on electrical characterization of the junction profiles to hypothesize the failure. In this paper, a case study was described to demonstrate the effective use of Cross-Section EBIC to reveal incoming substrate anomaly in the N-type epitaxy layer thickness resulting in product low yield.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134061948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915770
Siew Ming Lim, Jack Yi Jie Ng
Nanoprobing has become increasingly important for die level failure analysis as the industry moves towards smaller geometry over the years. This paper presents two case studies on Field Programmable Grid Array (FPGA) failure to demonstrate a destructive fault isolation methodology with the combination of delayering and nanoprobing in physical failure analysis
{"title":"Effective Backend Defect Localization by Destructive Fault Isolation","authors":"Siew Ming Lim, Jack Yi Jie Ng","doi":"10.1109/IPFA55383.2022.9915770","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915770","url":null,"abstract":"Nanoprobing has become increasingly important for die level failure analysis as the industry moves towards smaller geometry over the years. This paper presents two case studies on Field Programmable Grid Array (FPGA) failure to demonstrate a destructive fault isolation methodology with the combination of delayering and nanoprobing in physical failure analysis","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134353107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915730
Yee-Yang Tee, Xuenong Hong, Deruo Cheng, Tong Lin, Yiqiong Shi, B. Gwee
Delayered integrated circuit image analysis is an important step in hardware assurance, which is typically performed by automated approaches such as deep learning. The data dependent deep learning techniques require a diverse set of training data containing most of the variations in the delayered circuit images to perform well, which can be highly challenging to curate. In this paper, we present a hybrid unsupervised clustering method that aims to learn the distribution of newly acquired circuit image datasets, to aid the subsequent analysis flow. Our method consists of a deep learning-based feature extractor stage and a feature clustering stage, and we evaluate the performance of several feature extraction networks and clustering algorithms. Experimental results show that our method could obtain a promising normalized mutual information (NMI) score of 0.6095 on a dataset of delayered IC images taken of a manufactured Integrated Circuit (IC), and demonstrates excellent ability to retrieve visually similar images when provided with query images.
{"title":"Hybrid Unsupervised Clustering for Pretext Distribution Learning in IC Image Analysis","authors":"Yee-Yang Tee, Xuenong Hong, Deruo Cheng, Tong Lin, Yiqiong Shi, B. Gwee","doi":"10.1109/IPFA55383.2022.9915730","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915730","url":null,"abstract":"Delayered integrated circuit image analysis is an important step in hardware assurance, which is typically performed by automated approaches such as deep learning. The data dependent deep learning techniques require a diverse set of training data containing most of the variations in the delayered circuit images to perform well, which can be highly challenging to curate. In this paper, we present a hybrid unsupervised clustering method that aims to learn the distribution of newly acquired circuit image datasets, to aid the subsequent analysis flow. Our method consists of a deep learning-based feature extractor stage and a feature clustering stage, and we evaluate the performance of several feature extraction networks and clustering algorithms. Experimental results show that our method could obtain a promising normalized mutual information (NMI) score of 0.6095 on a dataset of delayered IC images taken of a manufactured Integrated Circuit (IC), and demonstrates excellent ability to retrieve visually similar images when provided with query images.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"241 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114051806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915783
C. Boit, J. Jatzkowski, F. Altmann, M. DiBattista, S. Silverman, G. Zwicker, N. Herfurth, E. Amini, J.-P. Seifert
The backside approach of contactless fault isolation (CFI) was comfortable as long as it could be carried out with Near Infra-Red (NIR) optical techniques. But even with a solid immersion lens (SIL), the resolution was limited to ~180nm, corresponding to ca. 40nm node integrated circuit (IC) technologies. However, with failure analysis (FA) experience and circuit simulation, it was still successful down to 14 nm FinFET technology. There are several attempts to keep optical CFI competitive because the FA community has enormous experience to read and interpret the obtained signals. Two major strategies are out to save optical CFI for smaller nanoscale IC technologies: (1) shorter wavelength increases resolution by practically max. 2X, but then optical absorption is increasing by orders of magnitude so bulk silicon has to get very thin, and (2) sticking to NIR resolution and work with the signal mix coming from ca. 10 FETs inside the optical spot, requiring an increasing level of circuit and device knowledge involving big data and Artificial Intelligence/Machine Learning (AI/ML).Here, another way out will be presented: (3) fault isolation techniques with real nanoscale resolution like e-beam probing, backside nanoprobing and even near-field optical microscopy are possible if only the back surface of the IC is very close to the active device. This Ultra-Thin Silicon Back Surface (UTSBS) has already been explored to a certain extent. This work shows an overview about the results that are available and the still open field of opportunities. These techniques also support CFI in 3D systems. The sample preparation is very challenging as it has to get down very close to the device of interest but gives more degrees of freedom as only local planarity in a trench is required. No space for a SIL has to be created and the imaging or probing techniques have a long working distance.So, the ultra-thinning may be only necessary in local area, offering a number of preparation solutions consisting of mainly FIB trenching and laser etching. They can as well be composed of these techniques. It will also be presented how beneficial chemical mechanical polishing (CMP) can be.
{"title":"The IC Ultra-Thin Back Surface - A Field of Real Nanoscale Fault Isolation Opportunities Requiring a Skillful Sample Preparation","authors":"C. Boit, J. Jatzkowski, F. Altmann, M. DiBattista, S. Silverman, G. Zwicker, N. Herfurth, E. Amini, J.-P. Seifert","doi":"10.1109/IPFA55383.2022.9915783","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915783","url":null,"abstract":"The backside approach of contactless fault isolation (CFI) was comfortable as long as it could be carried out with Near Infra-Red (NIR) optical techniques. But even with a solid immersion lens (SIL), the resolution was limited to ~180nm, corresponding to ca. 40nm node integrated circuit (IC) technologies. However, with failure analysis (FA) experience and circuit simulation, it was still successful down to 14 nm FinFET technology. There are several attempts to keep optical CFI competitive because the FA community has enormous experience to read and interpret the obtained signals. Two major strategies are out to save optical CFI for smaller nanoscale IC technologies: (1) shorter wavelength increases resolution by practically max. 2X, but then optical absorption is increasing by orders of magnitude so bulk silicon has to get very thin, and (2) sticking to NIR resolution and work with the signal mix coming from ca. 10 FETs inside the optical spot, requiring an increasing level of circuit and device knowledge involving big data and Artificial Intelligence/Machine Learning (AI/ML).Here, another way out will be presented: (3) fault isolation techniques with real nanoscale resolution like e-beam probing, backside nanoprobing and even near-field optical microscopy are possible if only the back surface of the IC is very close to the active device. This Ultra-Thin Silicon Back Surface (UTSBS) has already been explored to a certain extent. This work shows an overview about the results that are available and the still open field of opportunities. These techniques also support CFI in 3D systems. The sample preparation is very challenging as it has to get down very close to the device of interest but gives more degrees of freedom as only local planarity in a trench is required. No space for a SIL has to be created and the imaging or probing techniques have a long working distance.So, the ultra-thinning may be only necessary in local area, offering a number of preparation solutions consisting of mainly FIB trenching and laser etching. They can as well be composed of these techniques. It will also be presented how beneficial chemical mechanical polishing (CMP) can be.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123397357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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