Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858374
K. Yoshioka, R. Saito, Takumi Danjo, Sanroku Tsukamoto, H. Ishikuro
Subrange ADC with Dynamic Architecture and Frequency Scaling(DAFS) is presented, which has exponential power scaling against frequency with high-speed operation of over 1GS/s. We propose Live Configuring Technique(LCT) to adaptively configure the sub-ADC operation between binary-search and flash every clock cycle, reflecting the conversion delay. The power consumption is cut down significantly and retains high-speed operation. The prototype ADC fabricated in 65nm CMOS operates up to 1228MS/s and achieves an SNDR 36.2dB at nyquist. DAFS is active between 800-1200MS/s and when compared with the frequency power scaling with DAFS disabled, the peak power consumption cut down is 30%. Peak FoM of 85fJ/conv. was obtained at 820MS/s, which is nearly a 2x improvement compared with reported subrange ADCs.
{"title":"7-bit 0.8–1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique","authors":"K. Yoshioka, R. Saito, Takumi Danjo, Sanroku Tsukamoto, H. Ishikuro","doi":"10.1109/VLSIC.2014.6858374","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858374","url":null,"abstract":"Subrange ADC with Dynamic Architecture and Frequency Scaling(DAFS) is presented, which has exponential power scaling against frequency with high-speed operation of over 1GS/s. We propose Live Configuring Technique(LCT) to adaptively configure the sub-ADC operation between binary-search and flash every clock cycle, reflecting the conversion delay. The power consumption is cut down significantly and retains high-speed operation. The prototype ADC fabricated in 65nm CMOS operates up to 1228MS/s and achieves an SNDR 36.2dB at nyquist. DAFS is active between 800-1200MS/s and when compared with the frequency power scaling with DAFS disabled, the peak power consumption cut down is 30%. Peak FoM of 85fJ/conv. was obtained at 820MS/s, which is nearly a 2x improvement compared with reported subrange ADCs.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"85 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115842492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858429
S. Okura, O. Nishikido, Y. Sadanaga, Yasuhiro Kosaka, N. Araki, Kazuhiro Ueda, Masanori Tachibana, F. Morishita
A 5.0G-pixel/s readout circuit for 15.3mm×8.6mm optical size, 3.7M-pixel, 1300 fps, and digital output image sensor is presented. To achieve 5.0G-pixel/s readout rate, the high speed column readout circuit is introduced. The novel pixel readout, A/D conversion, and digital data transfer schemes are introduced to realize the readout rate and to reduce the interference noise. The 1 horizontal (1H) readout time is realized to be 1.0μs.
{"title":"A 3.7M-pixel 1300-fps CMOS image sensor with 5.0G-pixel/s high-speed readout circuit","authors":"S. Okura, O. Nishikido, Y. Sadanaga, Yasuhiro Kosaka, N. Araki, Kazuhiro Ueda, Masanori Tachibana, F. Morishita","doi":"10.1109/VLSIC.2014.6858429","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858429","url":null,"abstract":"A 5.0G-pixel/s readout circuit for 15.3mm×8.6mm optical size, 3.7M-pixel, 1300 fps, and digital output image sensor is presented. To achieve 5.0G-pixel/s readout rate, the high speed column readout circuit is introduced. The novel pixel readout, A/D conversion, and digital data transfer schemes are introduced to realize the readout rate and to reduce the interference noise. The 1 horizontal (1H) readout time is realized to be 1.0μs.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130717194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858376
J. Horng, Szu-Lin Liu, A. Kundu, Chin-Ho Chang, Chung-Hui Chen, H. Chiang, Y. Peng
This paper reports a combination structure of temperature and voltage sensor in a 16nm FinFET technology. The circuit transforms PTAT voltage across a resistor into an output clock with PTAT pulse-width. Fabricated in a 16nm CMOS, the temperature sensor achieves 1°C resolution over -10 ~ 90°C range and the voltage sensor achieves 4mV output error over 0.38V to 0.56V. The total chip size is 0.01mm2 and draws 70uW total power from a 0.7V supply. Depending on resolution, the measurement time can change from 10μsec to 1.6msec. This approach is not restricted by forward junction bias (~0.7V) of conventional BJTs and diodes.
{"title":"A 0.7V resistive sensor with temperature/voltage detection function in 16nm FinFET technologies","authors":"J. Horng, Szu-Lin Liu, A. Kundu, Chin-Ho Chang, Chung-Hui Chen, H. Chiang, Y. Peng","doi":"10.1109/VLSIC.2014.6858376","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858376","url":null,"abstract":"This paper reports a combination structure of temperature and voltage sensor in a 16nm FinFET technology. The circuit transforms PTAT voltage across a resistor into an output clock with PTAT pulse-width. Fabricated in a 16nm CMOS, the temperature sensor achieves 1°C resolution over -10 ~ 90°C range and the voltage sensor achieves 4mV output error over 0.38V to 0.56V. The total chip size is 0.01mm2 and draws 70uW total power from a 0.7V supply. Depending on resolution, the measurement time can change from 10μsec to 1.6msec. This approach is not restricted by forward junction bias (~0.7V) of conventional BJTs and diodes.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130908099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858433
T. Morrison, J. Silver, B. Otis
An electrocardiography SoC is integrated into a form-fitting textile along with flexible electrodes, battery and antenna. Clinically standard 12-lead ECG is recorded from this “smart shirt.” The data is encrypted and wirelessly transmitted via an on-chip ISM band radio and flexible antenna allowing secure, continuous cardiac monitoring on a smartphone while dissipating less than 1mW.
{"title":"A single-chip encrypted wireless 12-lead ECG smart shirt for continuous health monitoring","authors":"T. Morrison, J. Silver, B. Otis","doi":"10.1109/VLSIC.2014.6858433","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858433","url":null,"abstract":"An electrocardiography SoC is integrated into a form-fitting textile along with flexible electrodes, battery and antenna. Clinically standard 12-lead ECG is recorded from this “smart shirt.” The data is encrypted and wirelessly transmitted via an on-chip ISM band radio and flexible antenna allowing secure, continuous cardiac monitoring on a smartphone while dissipating less than 1mW.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"273 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114421512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858404
Li-Yue Huang, Meng-Fan Chang, C. Chuang, Chia-Chen Kuo, Chien-Fu Chen, Geng-Hau Yang, Hsiang-Jen Tsai, Tien-Fu Chen, S. Sheu, K. Su, Frederick T. Chen, T. Ku, M. Tsai, M. Kao
This study proposes an RC-filtered stress-decoupled (RCSD) 4T2R nonvolatile TCAM (nvTCAM) to 1) suppress match-line (ML) leakage current from match cells (IML-M), 2) reduce ML parasitic load (CML), 3) decouple NVM-stress from wordlength (WDL) and IML-MIS. RCSD reduces NVM-stress by 7+x, and achieves a 4+x improvement in speed-WDL-capacity-product. A 128×32b RCSD nvTCAM macro was fabricated using HfO ReRAM and an 180nm CMOS. This paper presents the first ReRAM-based nvTCAM featuring the shortest (1.2ns) search delay (TSD) among nvTCAMs with WDL≥32b.
{"title":"ReRAM-based 4T2R nonvolatile TCAM with 7x NVM-stress reduction, and 4x improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing","authors":"Li-Yue Huang, Meng-Fan Chang, C. Chuang, Chia-Chen Kuo, Chien-Fu Chen, Geng-Hau Yang, Hsiang-Jen Tsai, Tien-Fu Chen, S. Sheu, K. Su, Frederick T. Chen, T. Ku, M. Tsai, M. Kao","doi":"10.1109/VLSIC.2014.6858404","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858404","url":null,"abstract":"This study proposes an RC-filtered stress-decoupled (RCSD) 4T2R nonvolatile TCAM (nvTCAM) to 1) suppress match-line (ML) leakage current from match cells (IML-M), 2) reduce ML parasitic load (CML), 3) decouple NVM-stress from wordlength (WDL) and IML-MIS. RCSD reduces NVM-stress by 7+x, and achieves a 4+x improvement in speed-WDL-capacity-product. A 128×32b RCSD nvTCAM macro was fabricated using HfO ReRAM and an 180nm CMOS. This paper presents the first ReRAM-based nvTCAM featuring the shortest (1.2ns) search delay (TSD) among nvTCAMs with WDL≥32b.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"192 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114861853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858380
M. Tabesh, M. Rangwala, A. Niknejad, A. Arbabian
A wireless-powered pad-less single-chip dual-band mm-wave passive radio is implemented in 65nm CMOS for applications in sensor networks and wireless tagging. This fully self-sufficient system has no pads or external components (e.g. power supply), and the entire radio is a single 3.7mm × 1.2mm chip. To provide multi-access, and to mitigate interference, it uses two separate mm-wave bands for RX/TX and integrates both antennas to provide a measured communication range of 50cm. Compared to mm-sized passive radio solutions in the same category this system provides an order of magnitude range enhancement while improving input sensitivity by >14dB. Wideband pulse transmission enables real-time localization with time-of-flight. The entire system operates with standby harvested power below 1.5μW and aggregate rate >12Mbps.
{"title":"A power-harvesting pad-less mm-sized 24/60GHz passive radio with on-chip antennas","authors":"M. Tabesh, M. Rangwala, A. Niknejad, A. Arbabian","doi":"10.1109/VLSIC.2014.6858380","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858380","url":null,"abstract":"A wireless-powered pad-less single-chip dual-band mm-wave passive radio is implemented in 65nm CMOS for applications in sensor networks and wireless tagging. This fully self-sufficient system has no pads or external components (e.g. power supply), and the entire radio is a single 3.7mm × 1.2mm chip. To provide multi-access, and to mitigate interference, it uses two separate mm-wave bands for RX/TX and integrates both antennas to provide a measured communication range of 50cm. Compared to mm-sized passive radio solutions in the same category this system provides an order of magnitude range enhancement while improving input sensitivity by >14dB. Wideband pulse transmission enables real-time localization with time-of-flight. The entire system operates with standby harvested power below 1.5μW and aggregate rate >12Mbps.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114513044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858428
N. Dutton, L. Parmesan, A. Holmes, L. Grant, R. Henderson
A 320×240 single photon avalanche diode (SPAD) based single photon counting image sensor is implemented in 0.13μm imaging CMOS with state of the art 8μm pixel pitch at 26.8% fill factor. The imager is demonstrated operating as a global shutter (GS) oversampled binary image sensor reading out at 5.14kFPS. Frames are accumulated in real time on FPGA to construct a 256 photon/8bit output image at 20FPS.
{"title":"320×240 oversampled digital single photon counting image sensor","authors":"N. Dutton, L. Parmesan, A. Holmes, L. Grant, R. Henderson","doi":"10.1109/VLSIC.2014.6858428","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858428","url":null,"abstract":"A 320×240 single photon avalanche diode (SPAD) based single photon counting image sensor is implemented in 0.13μm imaging CMOS with state of the art 8μm pixel pitch at 26.8% fill factor. The imager is demonstrated operating as a global shutter (GS) oversampled binary image sensor reading out at 5.14kFPS. Frames are accumulated in real time on FPGA to construct a 256 photon/8bit output image at 20FPS.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115057000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858432
M. H. Nazari, M. Mujeeb-U.-Rahman, A. Scherer
We present a fully implantable subcutaneous continuous glucose monitoring (CGM) microsystem on CMOS platform. The proposed design incorporates electrochemical sensing technique using an ultra-low-power potentiostatic system. It is wirelessly powered through an inductive coupling link at 900MHz and supports bidirectional data communication with an external reader. A low-power potentiostat and a dual-slope ADC record the on-chip sensor signal. Pt and Ag/AgCl on-chip electrodes are post-fabricated and functionalized in situ by glucose oxidase enzyme to enable glucose measurement. The 1.4×1.4×0.25mm3 prototype fabricated in a 0.18μm CMOS technology was validated in glucose measurements. Total power consumption of the system is 6μW.
{"title":"An implantable continuous glucose monitoring microsystem in 0.18µm CMOS","authors":"M. H. Nazari, M. Mujeeb-U.-Rahman, A. Scherer","doi":"10.1109/VLSIC.2014.6858432","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858432","url":null,"abstract":"We present a fully implantable subcutaneous continuous glucose monitoring (CGM) microsystem on CMOS platform. The proposed design incorporates electrochemical sensing technique using an ultra-low-power potentiostatic system. It is wirelessly powered through an inductive coupling link at 900MHz and supports bidirectional data communication with an external reader. A low-power potentiostat and a dual-slope ADC record the on-chip sensor signal. Pt and Ag/AgCl on-chip electrodes are post-fabricated and functionalized in situ by glucose oxidase enzyme to enable glucose measurement. The 1.4×1.4×0.25mm3 prototype fabricated in a 0.18μm CMOS technology was validated in glucose measurements. Total power consumption of the system is 6μW.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128702427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858423
N. Miura, Daisuke Fujimoto, Daichi Tanaka, Yu-ichi Hayashi, N. Homma, T. Aoki, M. Nagata
A cryptographic engine (CE) resistant to local EM-analysis attacks (L-EMAs) is developed. An LC-oscillator-based tamper-access sensor detects a micro EM-probe approach and therefore protects the secret key information. A fully-digital sensor circuit with a reference-free dual-coil sensing scheme and a ring-oscillator-based one-step digital sensor calibration reduces the sensor area overhead to 1.6%. The sensor intermittently operates in interleave between CE operations, which saves power and performance penalty to 7.6% and 0.2%. A prototype in 0.18μm CMOS successfully demonstrates L-EMA attack detection and key protection for the first time.
{"title":"A local EM-analysis attack resistant cryptographic engine with fully-digital oscillator-based tamper-access sensor","authors":"N. Miura, Daisuke Fujimoto, Daichi Tanaka, Yu-ichi Hayashi, N. Homma, T. Aoki, M. Nagata","doi":"10.1109/VLSIC.2014.6858423","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858423","url":null,"abstract":"A cryptographic engine (CE) resistant to local EM-analysis attacks (L-EMAs) is developed. An LC-oscillator-based tamper-access sensor detects a micro EM-probe approach and therefore protects the secret key information. A fully-digital sensor circuit with a reference-free dual-coil sensing scheme and a ring-oscillator-based one-step digital sensor calibration reduces the sensor area overhead to 1.6%. The sensor intermittently operates in interleave between CE operations, which saves power and performance penalty to 7.6% and 0.2%. A prototype in 0.18μm CMOS successfully demonstrates L-EMA attack detection and key protection for the first time.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129972643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858393
F. Kuo, H. Chen, K. Yen, Hsien-Yuan Liao, C. Jou, F. Hsueh, M. Babaie, R. Staszewski
We propose a new architecture of an all-digital PLL (ADPLL) for advanced cellular radios that is optimized for 28 nm CMOS. It is based on a wide tuning range, fine-resolution class-F DCO with only switchable metal capacitors and a phase-predictive TDC. The 8mW DCO emits -157 dBc/Hz at 20MHz offset at ~2 GHz, while fully satisfying metal density rules. The 0.4mW TDC clocked at 40MHz achieves PVT-stabilized 6 ps resolution for -108 dBc/Hz in-band phase noise. FREF spur is ultra-low at <;-94 dBc. The ADPLL supports a 2-point modulation and consumes 12mW while occupying 0.22mm2, thus demonstrating both 72% power and 38% area reductions over prior records.
{"title":"A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS","authors":"F. Kuo, H. Chen, K. Yen, Hsien-Yuan Liao, C. Jou, F. Hsueh, M. Babaie, R. Staszewski","doi":"10.1109/VLSIC.2014.6858393","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858393","url":null,"abstract":"We propose a new architecture of an all-digital PLL (ADPLL) for advanced cellular radios that is optimized for 28 nm CMOS. It is based on a wide tuning range, fine-resolution class-F DCO with only switchable metal capacitors and a phase-predictive TDC. The 8mW DCO emits -157 dBc/Hz at 20MHz offset at ~2 GHz, while fully satisfying metal density rules. The 0.4mW TDC clocked at 40MHz achieves PVT-stabilized 6 ps resolution for -108 dBc/Hz in-band phase noise. FREF spur is ultra-low at <;-94 dBc. The ADPLL supports a 2-point modulation and consumes 12mW while occupying 0.22mm2, thus demonstrating both 72% power and 38% area reductions over prior records.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"273-276 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130765196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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