Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858385
J. K. Kim, Phil C. Knag, Thomas Chen, Zhengya Zhang
A sparse coding ASIC is designed to learn visual receptive fields and infer the sparse representation of images for encoding, feature detection and recognition. 256 leaky integrate-and-fire neurons are connected in a 2-layer network of 2D local grids linked in a 4-stage systolic ring to reduce the communication latency. Spike collisions are kept sparse enough to be tolerated to save power. Memory is divided into a core section to support inference, and an auxiliary section that is only powered on for learning. An approximate learning tracks only significant neuron activities to save memory and power. The 3.06mm2 65nm CMOS ASIC achieves an inference throughput of 1.24Gpixel/s at 1.0V and 310MHz, and on-chip learning can be completed in seconds. Memory supply voltage can be reduced to 440mV to exploit the soft algorithm that tolerates errors, reducing the inference power to 6.67mW for a 140Mpixel/s throughput at 35MHz.
{"title":"A 6.67mW sparse coding ASIC enabling on-chip learning and inference","authors":"J. K. Kim, Phil C. Knag, Thomas Chen, Zhengya Zhang","doi":"10.1109/VLSIC.2014.6858385","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858385","url":null,"abstract":"A sparse coding ASIC is designed to learn visual receptive fields and infer the sparse representation of images for encoding, feature detection and recognition. 256 leaky integrate-and-fire neurons are connected in a 2-layer network of 2D local grids linked in a 4-stage systolic ring to reduce the communication latency. Spike collisions are kept sparse enough to be tolerated to save power. Memory is divided into a core section to support inference, and an auxiliary section that is only powered on for learning. An approximate learning tracks only significant neuron activities to save memory and power. The 3.06mm2 65nm CMOS ASIC achieves an inference throughput of 1.24Gpixel/s at 1.0V and 310MHz, and on-chip learning can be completed in seconds. Memory supply voltage can be reduced to 440mV to exploit the soft algorithm that tolerates errors, reducing the inference power to 6.67mW for a 140Mpixel/s throughput at 35MHz.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116383907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858408
Jun-Chau Chien, M. Anwar, E. Yeh, Luke P. Lee, A. Niknejad
A series of high-sensitivity reactance sensors at 6.5/11/17.5/30-GHz is demonstrated for dielectric spectroscopy sensing on a single micron-size biological specimen. SNR is enhanced with the combination of interferometry and injection-locked oscillator sensors while the offset incurred by chopping-ripple is reduced through ping-pong nested chopping. The sensors achieve a sensitivity of less than 1.25 aF at 100-kHz, enabling label-free cellular detection as a new analytical tool.
{"title":"A 6.5/11/17.5/30-GHz high throughput interferometer-based reactance sensors using injection-locked oscillators and ping-pong nested chopping","authors":"Jun-Chau Chien, M. Anwar, E. Yeh, Luke P. Lee, A. Niknejad","doi":"10.1109/VLSIC.2014.6858408","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858408","url":null,"abstract":"A series of high-sensitivity reactance sensors at 6.5/11/17.5/30-GHz is demonstrated for dielectric spectroscopy sensing on a single micron-size biological specimen. SNR is enhanced with the combination of interferometry and injection-locked oscillator sensors while the offset incurred by chopping-ripple is reduced through ping-pong nested chopping. The sensors achieve a sensitivity of less than 1.25 aF at 100-kHz, enabling label-free cellular detection as a new analytical tool.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130852994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858440
Joseph Sankman, Minkyu Song, D. Ma
In conventional envelope modulators, a linear regulator is required to attain fast tracking, but it is a significant source of efficiency degradation. To eliminate the linear regulator, a dual-phase switching converter with synchronized adaptive voltage tracking (SAVT) control is employed. The SAVT control enables synchronization and fast hysteretic response for voltage tracking. To overcome the switching converter slew rate limit, a push-pull slew rate enhancer is implemented. The modulator is fabricated with a 0.18μm process and achieves 85.8% peak efficiency tracking a 10MHz LTE envelope.
{"title":"A 40-MHz 85.8%-peak-efficiency switching-converter-only dual-phase envelope modulator for 2-W 10-MHz LTE power amplifier","authors":"Joseph Sankman, Minkyu Song, D. Ma","doi":"10.1109/VLSIC.2014.6858440","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858440","url":null,"abstract":"In conventional envelope modulators, a linear regulator is required to attain fast tracking, but it is a significant source of efficiency degradation. To eliminate the linear regulator, a dual-phase switching converter with synchronized adaptive voltage tracking (SAVT) control is employed. The SAVT control enables synchronization and fast hysteretic response for voltage tracking. To overcome the switching converter slew rate limit, a push-pull slew rate enhancer is implemented. The modulator is fabricated with a 0.18μm process and achieves 85.8% peak efficiency tracking a 10MHz LTE envelope.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133764723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858394
Jun Yin, H. Luong
Employing a switched-transformer-based triple-band Q-VCO and a magnetically-tuned multi-mode triple-push x4 injection-locked frequency multiplier (ILFM), a CMOS SDR frequency synthesizer generates IQ LO signals continuously from 0.37GHz to 23.25GHz and differential LO signals from 23.25GHz to 46.5GHz. Implemented in 65-nm CMOS, the synthesizer measures phase noise of -94dBc/Hz in band and of -136dBc/Hz at 10MHz offset from 7.2GHz and RMS jitters between 0.43ps and 0.55ps across the whole frequency range while consuming 36 to 90mW and occupying an active area of 1.82mm2.
{"title":"A 0.37-to-46.5GHz frequency synthesizer for software-defined radios in 65nm CMOS","authors":"Jun Yin, H. Luong","doi":"10.1109/VLSIC.2014.6858394","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858394","url":null,"abstract":"Employing a switched-transformer-based triple-band Q-VCO and a magnetically-tuned multi-mode triple-push x4 injection-locked frequency multiplier (ILFM), a CMOS SDR frequency synthesizer generates IQ LO signals continuously from 0.37GHz to 23.25GHz and differential LO signals from 23.25GHz to 46.5GHz. Implemented in 65-nm CMOS, the synthesizer measures phase noise of -94dBc/Hz in band and of -136dBc/Hz at 10MHz offset from 7.2GHz and RMS jitters between 0.43ps and 0.55ps across the whole frequency range while consuming 36 to 90mW and occupying an active area of 1.82mm2.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"170 9-10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132462353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858445
Kailiang Chen, Hae-Seung Lee, C. Sodini
A Column-Row-Parallel ASIC architecture is proposed to enable 3D wearable / portable medical ultrasound. It offers linear-scaling interconnection, acquisition and programming time, while supporting rich functionality. High voltage MUX in Tx and specially sized source follower in Rx are used to implement parallelization for improved SNR. Fault-tolerant transceiver handles defective transducer elements to increase assembly yield and allow successful system demonstration.
{"title":"A Column-Row-Parallel ASIC architecture for 3D wearable / portable medical ultrasonic imaging","authors":"Kailiang Chen, Hae-Seung Lee, C. Sodini","doi":"10.1109/VLSIC.2014.6858445","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858445","url":null,"abstract":"A Column-Row-Parallel ASIC architecture is proposed to enable 3D wearable / portable medical ultrasound. It offers linear-scaling interconnection, acquisition and programming time, while supporting rich functionality. High voltage MUX in Tx and specially sized source follower in Rx are used to implement parallelization for improved SNR. Fault-tolerant transceiver handles defective transducer elements to increase assembly yield and allow successful system demonstration.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121259151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858435
Wei-Hsin Tseng, Pao-Cheng Chiu
A 960MS/s calibrated digital-to-analog converter (DAC) and low pass reconstruction filter are fabricated in 20nm CMOS. The calibration is implemented without an extra analog-to-digital converter (ADC) by reconfiguring the filter as the integrator for an incremental ADC which is used to digitize DAC cell mismatch. The digital input to the DAC is compensated by a look-up table to correct DAC mismatch in real-time. Before calibration, DNL is -1.1/+0.7LSB and INL is -2.1/+0.3LSB. After calibration DNL and INL are improved to -0.2/+0.2LSB and -0.3/+0.2LSB respectively. This 10b DAC achieves 80.2dB SFDR after calibration, and occupies 0.01mm2 for an I/Q DAC pair which is 12.5% of the area for an uncalibrated I/Q DAC pair.
{"title":"A 960MS/s DAC with 80dB SFDR in 20nm CMOS for multi-mode baseband wireless transmitter","authors":"Wei-Hsin Tseng, Pao-Cheng Chiu","doi":"10.1109/VLSIC.2014.6858435","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858435","url":null,"abstract":"A 960MS/s calibrated digital-to-analog converter (DAC) and low pass reconstruction filter are fabricated in 20nm CMOS. The calibration is implemented without an extra analog-to-digital converter (ADC) by reconfiguring the filter as the integrator for an incremental ADC which is used to digitize DAC cell mismatch. The digital input to the DAC is compensated by a look-up table to correct DAC mismatch in real-time. Before calibration, DNL is -1.1/+0.7LSB and INL is -2.1/+0.3LSB. After calibration DNL and INL are improved to -0.2/+0.2LSB and -0.3/+0.2LSB respectively. This 10b DAC achieves 80.2dB SFDR after calibration, and occupies 0.01mm2 for an I/Q DAC pair which is 12.5% of the area for an uncalibrated I/Q DAC pair.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120994097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858414
B. Kleveland, Jeong-Hyeok Choi, J. Kumala, Pascal Adam, Patrick Chen, Rajesh Chopra, Antonio Cruz, R. B. David, Ashish Dixit, Sinan Doluca, Mark Hendrickson, Ben Lee, Ming Liu, M. J. Miller, Mike Morrison, B. C. Na, Jay Patel, Dipak K. Sikdar, M. Sporer, Clement Szeto, Anju Tsao, Jianguang Wang, Daniel Yau, Wesley Yu
We propose improving system availability by performing in-field repair at the chip level. This enables margining and detection of degrading memory cells before the user observes any errors. A 576 Mb embedded DRAM at 1.5 GHz in a 40nm CMOS technology achieves improved resilience to both aging memory cells and cells with variable retention time (VRT). Un-interrupted user access of 6 billion 72-bit read and write operations per second is maintained during background repair.
{"title":"Early detection and repair of VRT and aging DRAM bits by margined in-field BIST","authors":"B. Kleveland, Jeong-Hyeok Choi, J. Kumala, Pascal Adam, Patrick Chen, Rajesh Chopra, Antonio Cruz, R. B. David, Ashish Dixit, Sinan Doluca, Mark Hendrickson, Ben Lee, Ming Liu, M. J. Miller, Mike Morrison, B. C. Na, Jay Patel, Dipak K. Sikdar, M. Sporer, Clement Szeto, Anju Tsao, Jianguang Wang, Daniel Yau, Wesley Yu","doi":"10.1109/VLSIC.2014.6858414","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858414","url":null,"abstract":"We propose improving system availability by performing in-field repair at the chip level. This enables margining and detection of degrading memory cells before the user observes any errors. A 576 Mb embedded DRAM at 1.5 GHz in a 40nm CMOS technology achieves improved resilience to both aging memory cells and cells with variable retention time (VRT). Un-interrupted user access of 6 billion 72-bit read and write operations per second is maintained during background repair.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121074890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858442
Liechao Huang, W. Rieutort-Louis, A. Gualdino, L. Teagno, Yingzhe Hu, J. Mouro, J. Sanz-Robinson, J. Sturm, S. Wagner, V. Chu, J. Conde, N. Verma
Thin-film MEMS bridges as micro-resonators have proven attractive for various sensing applications (acceleration, mass, chemical, pressure, etc.) by using frequency shift as a basis for sensing [1]. Low-temperature processing of amorphous-silicon (a-Si:H) enables low-cost fabrication of high-Q MEMS bridges having excellent compatibility with CMOS post processing. However, the a-Si:H bridges have weak motional conductances [2]. Parasitic feed-through capacitances, both due to the device structure and routing, can easily drown out the resonant behavior. This paper proposes a non-contact MEMS interfacing and readout system in standard CMOS which enables robust integration while substantially rejecting the effects of parasitic feed-through capacitance.
{"title":"An ASIC for readout of post-processed thin-film MEMS resonators by employing capacitive interfacing and active parasitic cancellation","authors":"Liechao Huang, W. Rieutort-Louis, A. Gualdino, L. Teagno, Yingzhe Hu, J. Mouro, J. Sanz-Robinson, J. Sturm, S. Wagner, V. Chu, J. Conde, N. Verma","doi":"10.1109/VLSIC.2014.6858442","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858442","url":null,"abstract":"Thin-film MEMS bridges as micro-resonators have proven attractive for various sensing applications (acceleration, mass, chemical, pressure, etc.) by using frequency shift as a basis for sensing [1]. Low-temperature processing of amorphous-silicon (a-Si:H) enables low-cost fabrication of high-Q MEMS bridges having excellent compatibility with CMOS post processing. However, the a-Si:H bridges have weak motional conductances [2]. Parasitic feed-through capacitances, both due to the device structure and routing, can easily drown out the resonant behavior. This paper proposes a non-contact MEMS interfacing and readout system in standard CMOS which enables robust integration while substantially rejecting the effects of parasitic feed-through capacitance.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126525977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858401
Joshua Liang, M. S. Jalali, A. Sheikholeslami, M. Kibune, H. Tamura
On-chip jitter measurement is demonstrated in a 10Gb/s CDR by correlating the phase detector outputs of two adjacent CDR lanes. The RMS jitter of the received data and an estimate of the jitter's power spectral density are then extracted without using an external reference clock. Circuits implemented in 65nm CMOS measure random jitter ranging from 0.85ps to 1.89ps in PRBS31 data with no more than 100fs error compared to an 80GS/s real-time oscilloscope. Sinusoidal jitter of 0.89ps to 5.1ps is measured with a worst-case error of 580fS compared to the oscilloscope.
{"title":"On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs","authors":"Joshua Liang, M. S. Jalali, A. Sheikholeslami, M. Kibune, H. Tamura","doi":"10.1109/VLSIC.2014.6858401","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858401","url":null,"abstract":"On-chip jitter measurement is demonstrated in a 10Gb/s CDR by correlating the phase detector outputs of two adjacent CDR lanes. The RMS jitter of the received data and an estimate of the jitter's power spectral density are then extracted without using an external reference clock. Circuits implemented in 65nm CMOS measure random jitter ranging from 0.85ps to 1.89ps in PRBS31 data with no more than 100fs error compared to an 80GS/s real-time oscilloscope. Sinusoidal jitter of 0.89ps to 5.1ps is measured with a worst-case error of 580fS compared to the oscilloscope.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132871035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858426
D. Bol, G. D. Streel, F. Botman, A. K. Lusala, N. Couniot
We propose a CMOS image sensor operating at ultra-low voltage (ULV) in a 65-nm low-power (LP) CMOS logic process for ultra-low-power SoC integration. Energy of 17-pJ/frame.pixel and 4×4-μm pixel size with 57-% fill factor are achieved at 0.5 V with digital pixel sensor (DPS) and time-based readout while reaching 40-dB dynamic range (DR) despite high leakage currents and Vt variability, thanks to delta-reset sampling (DRS) as well as gating and adaptive body biasing (ABB) of the 2-transistor (2-T) in-pixel comparator.
{"title":"A 65-nm 0.5-V 17-pJ/frame.pixel DPS CMOS image sensor for ultra-low-power SoCs achieving 40-dB dynamic range","authors":"D. Bol, G. D. Streel, F. Botman, A. K. Lusala, N. Couniot","doi":"10.1109/VLSIC.2014.6858426","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858426","url":null,"abstract":"We propose a CMOS image sensor operating at ultra-low voltage (ULV) in a 65-nm low-power (LP) CMOS logic process for ultra-low-power SoC integration. Energy of 17-pJ/frame.pixel and 4×4-μm pixel size with 57-% fill factor are achieved at 0.5 V with digital pixel sensor (DPS) and time-based readout while reaching 40-dB dynamic range (DR) despite high leakage currents and Vt variability, thanks to delta-reset sampling (DRS) as well as gating and adaptive body biasing (ABB) of the 2-transistor (2-T) in-pixel comparator.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130538044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：