Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858417
Yu-Lun Chen, Chiro Kao, Pen-Jui Peng, Jri Lee
This work introduces a 94GHz duobinary keying wireless transceiver for point-to-point communications. It presents bandwidth efficiency twice as much as an OOK system and requires no carrier recovery and baseband circuitry to reduce power consumption. Designed and fabricated in 65nm CMOS, the transceiver achieves a 2.0-Gb/s data link with BER <; 10-9 while consuming a total power of 265mW.
{"title":"A 94GHz duobinary keying wireless transceiver in 65nm CMOS","authors":"Yu-Lun Chen, Chiro Kao, Pen-Jui Peng, Jri Lee","doi":"10.1109/VLSIC.2014.6858417","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858417","url":null,"abstract":"This work introduces a 94GHz duobinary keying wireless transceiver for point-to-point communications. It presents bandwidth efficiency twice as much as an OOK system and requires no carrier recovery and baseband circuitry to reduce power consumption. Designed and fabricated in 65nm CMOS, the transceiver achieves a 2.0-Gb/s data link with BER <; 10-9 while consuming a total power of 265mW.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123793172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858362
Masum Hossain, Ehung Chen, R. Navid, B. Leibowitz, Chuen-huei Adam Chou, S. Li, Myeong-Jae Park, Jihong Ren, B. Daly, Bruce Su, M. Shirasgaonkar, F. Heaton, J. Zerbe, J. Eble
A 4×40 Gb/s collaborative digital CDR is implemented in 28nm CMOS. The CDR is capable of recovering a low jitter clock from a partially-equalized or un-equalized eye by using a phase detection scheme that inherently filters out ISI edges. The CDR uses split feedback that simultaneously allows wider bandwidth and lower recovered clock jitter. A shared frequency tracking is also introduced that results in lower periodic jitter. Combining these techniques the CDR recovers a 10GHz clock from an eye containing 0.8UIpp DDJ and still achieves 1-10 MHz of tracking bandwidth while adding <; 300fs of jitter. Per lane CDR occupies only .06 mm2 and consumes 175 mW.
{"title":"A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering","authors":"Masum Hossain, Ehung Chen, R. Navid, B. Leibowitz, Chuen-huei Adam Chou, S. Li, Myeong-Jae Park, Jihong Ren, B. Daly, Bruce Su, M. Shirasgaonkar, F. Heaton, J. Zerbe, J. Eble","doi":"10.1109/VLSIC.2014.6858362","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858362","url":null,"abstract":"A 4×40 Gb/s collaborative digital CDR is implemented in 28nm CMOS. The CDR is capable of recovering a low jitter clock from a partially-equalized or un-equalized eye by using a phase detection scheme that inherently filters out ISI edges. The CDR uses split feedback that simultaneously allows wider bandwidth and lower recovered clock jitter. A shared frequency tracking is also introduced that results in lower periodic jitter. Combining these techniques the CDR recovers a 10GHz clock from an eye containing 0.8UIpp DDJ and still achieves 1-10 MHz of tracking bandwidth while adding <; 300fs of jitter. Per lane CDR occupies only .06 mm2 and consumes 175 mW.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131017224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858369
A. R. Junaidi, Yasuhiro Take, T. Kuroda
The area efficiency of an inductive-coupling interface is improved by 12 times for WIO2 standard (352Gb/s) and beyond. By using a quadrature phase division multiplexing, coils are overlapped and the density is increased by 4 times. It is further increased by 3 times by shortening communication distance with an ultra-thin fan-out wafer level package. The proposed DRAM/SoC interface at 356Gb/s outperforms WIO2 with TSV in terms of area efficiency (4x better) and manufacturing cost (40% cheaper) and outperforms LPDDR4 in PoP in terms of power dissipation (5x lower) and timing control easiness.
{"title":"A 352Gb/s inductive-coupling DRAM/SoC interface using overlapping coils with phase division multiplexing and ultra-thin fan-out wafer level package","authors":"A. R. Junaidi, Yasuhiro Take, T. Kuroda","doi":"10.1109/VLSIC.2014.6858369","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858369","url":null,"abstract":"The area efficiency of an inductive-coupling interface is improved by 12 times for WIO2 standard (352Gb/s) and beyond. By using a quadrature phase division multiplexing, coils are overlapped and the density is increased by 4 times. It is further increased by 3 times by shortening communication distance with an ultra-thin fan-out wafer level package. The proposed DRAM/SoC interface at 356Gb/s outperforms WIO2 with TSV in terms of area efficiency (4x better) and manufacturing cost (40% cheaper) and outperforms LPDDR4 in PoP in terms of power dissipation (5x lower) and timing control easiness.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127111838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858395
B. Young, K. Reddy, Sachin Rao, A. Elshazly, Tejasvi Anand, P. Hanumolu
A wide bandwidth, high sample rate 3rd order continuous-time ΔΣ modulator using VCO-based integrators is presented. Non-idealities caused by VCOs at the modulator frontend are addressed using both circuit- and architecture-level techniques. Fabricated in 65 nm CMOS, the prototype modulator operates at 1.28 GS/s and achieves a dynamic range of 75 dB, SNR of 71 dB in 50 MHz bandwidth, while consuming 38 mW of total power.
{"title":"A 75dB DR 50MHz BW 3rd order CT-ΔΣ modulator using VCO-based integrators","authors":"B. Young, K. Reddy, Sachin Rao, A. Elshazly, Tejasvi Anand, P. Hanumolu","doi":"10.1109/VLSIC.2014.6858395","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858395","url":null,"abstract":"A wide bandwidth, high sample rate 3rd order continuous-time ΔΣ modulator using VCO-based integrators is presented. Non-idealities caused by VCOs at the modulator frontend are addressed using both circuit- and architecture-level techniques. Fabricated in 65 nm CMOS, the prototype modulator operates at 1.28 GS/s and achieves a dynamic range of 75 dB, SNR of 71 dB in 50 MHz bandwidth, while consuming 38 mW of total power.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127355968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858449
S. Iguchi, H. Fuketa, T. Sakurai, M. Takamiya
To reduce the start-up time of a crystal oscillator (XO), a chirp injection (CI) and a negative resistance booster (NRB) are proposed. By combining CI and NRB, the measured start-up time of a 39-MHz XO in 180-nm CMOS is reduced by 92% from 2.1ms to 158μs, which is the shortest time in the published XO's. The measured start-up time variations due to the ±20% supply voltage change or the temperature change are less than 13%.
{"title":"92% start-up time reduction by variation-tolerant chirp injection (CI) and negative resistance booster (NRB) in 39MHz crystal oscillator","authors":"S. Iguchi, H. Fuketa, T. Sakurai, M. Takamiya","doi":"10.1109/VLSIC.2014.6858449","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858449","url":null,"abstract":"To reduce the start-up time of a crystal oscillator (XO), a chirp injection (CI) and a negative resistance booster (NRB) are proposed. By combining CI and NRB, the measured start-up time of a 39-MHz XO in 180-nm CMOS is reduced by 92% from 2.1ms to 158μs, which is the shortest time in the published XO's. The measured start-up time variations due to the ±20% supply voltage change or the temperature change are less than 13%.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"184 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131467737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858425
Gyouho Kim, Yoonmyung Lee, Z. Foo, P. Pannuto, Ye-Sheng Kuo, B. Kempke, M. Ghaed, S. Bang, Inhee Lee, Yejoong Kim, Seokhyeon Jeong, P. Dutta, D. Sylvester, D. Blaauw
We present a 2×4×4mm3 imaging system complete with optics, wireless communication, battery, power management, solar harvesting, processor and memory. The system features a 160×160 resolution CMOS image sensor with 304nW continuous in-pixel motion detection mode. System components are fabricated in five different IC layers and die-stacked for minimal form factor. Photovoltaic (PV) cells face the opposite direction of the imager for optimal illumination and generate 456nW at 10klux to enable energy autonomous system operation.
{"title":"A millimeter-scale wireless imaging system with continuous motion detection and energy harvesting","authors":"Gyouho Kim, Yoonmyung Lee, Z. Foo, P. Pannuto, Ye-Sheng Kuo, B. Kempke, M. Ghaed, S. Bang, Inhee Lee, Yejoong Kim, Seokhyeon Jeong, P. Dutta, D. Sylvester, D. Blaauw","doi":"10.1109/VLSIC.2014.6858425","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858425","url":null,"abstract":"We present a 2×4×4mm3 imaging system complete with optics, wireless communication, battery, power management, solar harvesting, processor and memory. The system features a 160×160 resolution CMOS image sensor with 304nW continuous in-pixel motion detection mode. System components are fabricated in five different IC layers and die-stacked for minimal form factor. Photovoltaic (PV) cells face the opposite direction of the imager for optimal illumination and generate 456nW at 10klux to enable energy autonomous system operation.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131427562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858444
Kiduk Kim, Sanghyub Kang, Yoon-Kyung Choi, Kyung-Hoon Lee, Choong-Hoon Lee, Jin-chul Lee, Michael Choi, Kyungjun Ko, Joonwoo Jung, Namgu Park, Hojin Park, Gyoo-cheol Hwang
A fully-differential capacitive touch sensing method is proposed in which common-mode noise currents are symmetrically subtracted at the differential input of the first stage such that it doesn't contribute to dynamic range reduction in the later stages. And, for better sensitivity, the proposed method could accumulate signal charges in continuous time domain, and does not suffer from aliasing issues observed in many discrete-time charge integrating methods. Measurement results showed 42 dB SNR for a 1-mm diameter stylus on a 5-inch full-HD on-cell touch display panel.
{"title":"A fully-differential capacitive touch controller with input common-mode feedback for symmetric display noise cancellation","authors":"Kiduk Kim, Sanghyub Kang, Yoon-Kyung Choi, Kyung-Hoon Lee, Choong-Hoon Lee, Jin-chul Lee, Michael Choi, Kyungjun Ko, Joonwoo Jung, Namgu Park, Hojin Park, Gyoo-cheol Hwang","doi":"10.1109/VLSIC.2014.6858444","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858444","url":null,"abstract":"A fully-differential capacitive touch sensing method is proposed in which common-mode noise currents are symmetrically subtracted at the differential input of the first stage such that it doesn't contribute to dynamic range reduction in the later stages. And, for better sensitivity, the proposed method could accumulate signal charges in continuous time domain, and does not suffer from aliasing issues observed in many discrete-time charge integrating methods. Measurement results showed 42 dB SNR for a 1-mm diameter stylus on a 5-inch full-HD on-cell touch display panel.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114396570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858448
Chunyang Zhai, Jeffrey Fredenburg, John Bell, M. Flynn
A novel self-filtering scheme breaks the typical tradeoff between noise and power, enabling a ring oscillator to approach the phase noise performance of an LC oscillator. The prototype N-path filter enhanced voltage-controlled ring oscillator (NPFRVCO) achieves a measured phase noise of -110dBc/Hz at a 1MHz offset frequency for an oscillation frequency of 1.0GHz. The self-clocked N-path filter reduces the phase noise by 10dB and 28dB for 1.0GHz and 300MHz oscillation frequencies, respectively. Implemented in 65nm CMOS, the NPFRVCO occupies a die area of 0.015 mm2 and consumes 4.7mW from 1.2V power supply when operating at 1.0GHz. The NPFRVCO has a measured frequency tuning range from 300MHz to 1.6GHz and achieves a FoM of 163dB at 1MHz offset.
{"title":"An N-path filter enhanced low phase noise ring VCO","authors":"Chunyang Zhai, Jeffrey Fredenburg, John Bell, M. Flynn","doi":"10.1109/VLSIC.2014.6858448","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858448","url":null,"abstract":"A novel self-filtering scheme breaks the typical tradeoff between noise and power, enabling a ring oscillator to approach the phase noise performance of an LC oscillator. The prototype N-path filter enhanced voltage-controlled ring oscillator (NPFRVCO) achieves a measured phase noise of -110dBc/Hz at a 1MHz offset frequency for an oscillation frequency of 1.0GHz. The self-clocked N-path filter reduces the phase noise by 10dB and 28dB for 1.0GHz and 300MHz oscillation frequencies, respectively. Implemented in 65nm CMOS, the NPFRVCO occupies a die area of 0.015 mm2 and consumes 4.7mW from 1.2V power supply when operating at 1.0GHz. The NPFRVCO has a measured frequency tuning range from 300MHz to 1.6GHz and achieves a FoM of 163dB at 1MHz offset.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127396579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858419
H. Hedayati, V. Aparin, K. Entesari
The real challenge in designing wide-band receivers is the ability to tolerate out of band blockers. In this paper, different blocker rejection techniques are proposed to significantly improve the linearity. The blockers are first rejected prior to the LNA, then, a novel base-band blocker filtering technique further rejects the blockers at the TIA input. A dual mixer architecture is also employed to further attenuate blockers. Finally, a very low impedance TIA is designed to improve the linearity of the entire receiver chain. The receiver has an IIP3 of +22 dBm and a NF of 3.5 dB in 0.18 μm CMOS technology.
{"title":"A +22dBm IIP3 and 3.5dB NF wideband receiver with RF and baseband blocker filtering techniques","authors":"H. Hedayati, V. Aparin, K. Entesari","doi":"10.1109/VLSIC.2014.6858419","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858419","url":null,"abstract":"The real challenge in designing wide-band receivers is the ability to tolerate out of band blockers. In this paper, different blocker rejection techniques are proposed to significantly improve the linearity. The blockers are first rejected prior to the LNA, then, a novel base-band blocker filtering technique further rejects the blockers at the TIA input. A dual mixer architecture is also employed to further attenuate blockers. Finally, a very low impedance TIA is designed to improve the linearity of the entire receiver chain. The receiver has an IIP3 of +22 dBm and a NF of 3.5 dB in 0.18 μm CMOS technology.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125896392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858371
A. Bannon, Christopher P. Hurrell, Derek Hummerston, C. Lyden
This paper presents an 18 bit 5 MS/s SAR ADC. It has a dynamic range of 100.2 dB, SNR of 99 dB, INL of ±2 ppm and DNL of ±0.4 ppm. It has currently the lowest noise floor of any monolithic Nyquist converter relative to the full scale input (21.9 nV/√Hz, ±5V full scale) known to the author, all of this is achieved with an ADC core power of 30.52 mW giving a Schreier figure of merit of 179.3 dB [1]. Architectural choices such as the use of a residue amplifier are outlined that enable the high sample rate, low noise and power efficiency. The design is implemented on 0.18 μm CMOS with MIM capacitors and both 1.8 V and 5 V MOS devices. An LVDS interface is used to transfer the ADC result off chip.
{"title":"An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic range","authors":"A. Bannon, Christopher P. Hurrell, Derek Hummerston, C. Lyden","doi":"10.1109/VLSIC.2014.6858371","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858371","url":null,"abstract":"This paper presents an 18 bit 5 MS/s SAR ADC. It has a dynamic range of 100.2 dB, SNR of 99 dB, INL of ±2 ppm and DNL of ±0.4 ppm. It has currently the lowest noise floor of any monolithic Nyquist converter relative to the full scale input (21.9 nV/√Hz, ±5V full scale) known to the author, all of this is achieved with an ADC core power of 30.52 mW giving a Schreier figure of merit of 179.3 dB [1]. Architectural choices such as the use of a residue amplifier are outlined that enable the high sample rate, low noise and power efficiency. The design is implemented on 0.18 μm CMOS with MIM capacitors and both 1.8 V and 5 V MOS devices. An LVDS interface is used to transfer the ADC result off chip.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125248226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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