Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858395
B. Young, K. Reddy, Sachin Rao, A. Elshazly, Tejasvi Anand, P. Hanumolu
A wide bandwidth, high sample rate 3rd order continuous-time ΔΣ modulator using VCO-based integrators is presented. Non-idealities caused by VCOs at the modulator frontend are addressed using both circuit- and architecture-level techniques. Fabricated in 65 nm CMOS, the prototype modulator operates at 1.28 GS/s and achieves a dynamic range of 75 dB, SNR of 71 dB in 50 MHz bandwidth, while consuming 38 mW of total power.
{"title":"A 75dB DR 50MHz BW 3rd order CT-ΔΣ modulator using VCO-based integrators","authors":"B. Young, K. Reddy, Sachin Rao, A. Elshazly, Tejasvi Anand, P. Hanumolu","doi":"10.1109/VLSIC.2014.6858395","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858395","url":null,"abstract":"A wide bandwidth, high sample rate 3rd order continuous-time ΔΣ modulator using VCO-based integrators is presented. Non-idealities caused by VCOs at the modulator frontend are addressed using both circuit- and architecture-level techniques. Fabricated in 65 nm CMOS, the prototype modulator operates at 1.28 GS/s and achieves a dynamic range of 75 dB, SNR of 71 dB in 50 MHz bandwidth, while consuming 38 mW of total power.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127355968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858362
Masum Hossain, Ehung Chen, R. Navid, B. Leibowitz, Chuen-huei Adam Chou, S. Li, Myeong-Jae Park, Jihong Ren, B. Daly, Bruce Su, M. Shirasgaonkar, F. Heaton, J. Zerbe, J. Eble
A 4×40 Gb/s collaborative digital CDR is implemented in 28nm CMOS. The CDR is capable of recovering a low jitter clock from a partially-equalized or un-equalized eye by using a phase detection scheme that inherently filters out ISI edges. The CDR uses split feedback that simultaneously allows wider bandwidth and lower recovered clock jitter. A shared frequency tracking is also introduced that results in lower periodic jitter. Combining these techniques the CDR recovers a 10GHz clock from an eye containing 0.8UIpp DDJ and still achieves 1-10 MHz of tracking bandwidth while adding <; 300fs of jitter. Per lane CDR occupies only .06 mm2 and consumes 175 mW.
{"title":"A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering","authors":"Masum Hossain, Ehung Chen, R. Navid, B. Leibowitz, Chuen-huei Adam Chou, S. Li, Myeong-Jae Park, Jihong Ren, B. Daly, Bruce Su, M. Shirasgaonkar, F. Heaton, J. Zerbe, J. Eble","doi":"10.1109/VLSIC.2014.6858362","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858362","url":null,"abstract":"A 4×40 Gb/s collaborative digital CDR is implemented in 28nm CMOS. The CDR is capable of recovering a low jitter clock from a partially-equalized or un-equalized eye by using a phase detection scheme that inherently filters out ISI edges. The CDR uses split feedback that simultaneously allows wider bandwidth and lower recovered clock jitter. A shared frequency tracking is also introduced that results in lower periodic jitter. Combining these techniques the CDR recovers a 10GHz clock from an eye containing 0.8UIpp DDJ and still achieves 1-10 MHz of tracking bandwidth while adding <; 300fs of jitter. Per lane CDR occupies only .06 mm2 and consumes 175 mW.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131017224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858381
S. Ha, Chul Kim, Jongkil Park, Siddharth Joshi, G. Cauwenberghs
We present a power/data telemetry IC with a new data modulation scheme and simultaneous power transfer through a single inductive link. Data-driven synchronized single-cycle shorting of the secondary LC tank conserves reactive power while inducing an instantaneous voltage change at the primary side. Cyclic on-off keying time-encoded symbol mapping of the shorting cycle allows transmission of two data bits per four carrier cycles with simultaneous power transfer during non-shorting cycles. All timing control signals for rectification and data transmission are generated from a low-power clock recovery comparator and 22-phase 2× PLL. The 1-mm2 65-nm CMOS IC delivers up to 6.3-mW power and transmits 6.78-Mbps data with a BER of less than 5.9×10-7 over a single 1-cm 13.56-MHz inductive link.
我们提出了一种功率/数据遥测IC，具有新的数据调制方案，并通过单个感应链路同时传输功率。数据驱动的二次LC槽同步单周期短路在引起一次侧瞬时电压变化的同时节省了无功功率。短周期的循环开关键控时间编码符号映射允许每四个载波周期传输两个数据位，同时在非短周期期间传输功率。整流和数据传输的所有定时控制信号由低功耗时钟恢复比较器和22相2x锁相环产生。1 mm2 65nm CMOS IC提供高达6.3 mw的功率，传输6.78 mbps的数据，在单个1 cm 13.56 mhz电感链路上的误码小于5.9×10-7。
{"title":"Energy-recycling integrated 6.78-Mbps data 6.3-mW power telemetry over a single 13.56-MHz inductive link","authors":"S. Ha, Chul Kim, Jongkil Park, Siddharth Joshi, G. Cauwenberghs","doi":"10.1109/VLSIC.2014.6858381","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858381","url":null,"abstract":"We present a power/data telemetry IC with a new data modulation scheme and simultaneous power transfer through a single inductive link. Data-driven synchronized single-cycle shorting of the secondary LC tank conserves reactive power while inducing an instantaneous voltage change at the primary side. Cyclic on-off keying time-encoded symbol mapping of the shorting cycle allows transmission of two data bits per four carrier cycles with simultaneous power transfer during non-shorting cycles. All timing control signals for rectification and data transmission are generated from a low-power clock recovery comparator and 22-phase 2× PLL. The 1-mm2 65-nm CMOS IC delivers up to 6.3-mW power and transmits 6.78-Mbps data with a BER of less than 5.9×10-7 over a single 1-cm 13.56-MHz inductive link.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132783098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858360
A. Garg, U. Singh, Nick Huang, Wayne Wong, B. Liu, Z. Huang, A. Momtaz, Jun Cao
A quad-channel, 112-128 Gb/s coherent DP-QPSK transmitter in 40 nm CMOS is presented. The 27.9-32.1 Gb/s TX features a half-rate architecture with a 2-tap FIR. The measured output has an amplitude of 1.2Vpp-diff with 1.3 ps deterministic jitter (DJ). The DP-QPSK TX's precoded data alignment is maintained through the quad-lane transmitter by the use of an automatic synchronous feedback loop, removing the need for a master global reset. The PLL outputs the full-rate and half-rate clock with ±0.5 UI skew adjustment relative to the data. The power consumption of the transmitter and PLL is 712 mW.
{"title":"A quad-channel 112–128 Gb/s coherent transmitter in 40 nm CMOS","authors":"A. Garg, U. Singh, Nick Huang, Wayne Wong, B. Liu, Z. Huang, A. Momtaz, Jun Cao","doi":"10.1109/VLSIC.2014.6858360","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858360","url":null,"abstract":"A quad-channel, 112-128 Gb/s coherent DP-QPSK transmitter in 40 nm CMOS is presented. The 27.9-32.1 Gb/s TX features a half-rate architecture with a 2-tap FIR. The measured output has an amplitude of 1.2Vpp-diff with 1.3 ps deterministic jitter (DJ). The DP-QPSK TX's precoded data alignment is maintained through the quad-lane transmitter by the use of an automatic synchronous feedback loop, removing the need for a master global reset. The PLL outputs the full-rate and half-rate clock with ±0.5 UI skew adjustment relative to the data. The power consumption of the transmitter and PLL is 712 mW.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"202 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134310650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858406
S. Tanakamaru, Yuta Kitamura, Senju Yamazaki, Tsukasa Tokutomi, K. Takeuchi
Application-aware solid-state drives (SSDs) with 2 adaptive coding schemes to improve reliability are presented. In NAND flash memory, a direct reliability trade-off exists between write/erase (W/E) cycle and data-retention (DR) time. Thus, SSDs can be used for applications that have long DR time and low W/E cycles, or short DR time with high W/E cycles. The n-out-of-8 level cell (nLC) scheme is proposed for low-cost, long-term, archive storage which is indispensable to preserve human digital data. nLC eliminates the memory states of the Triple-Level Cell (TLC) NAND flash memory from 8 to 7...4 levels. Universal asymmetric coding (UAC) is also proposed for cloud/security camera/enterprise storage environments which require high endurance but shorter DR time. Both nLC and UAC optimize coding based on the applications' required W/E cycle and DR. Bit-error rates (BERs) are improved by 79% and 52% with nLC and UAC, respectively.
{"title":"Application-aware solid-state drives (SSDs) with adaptive coding","authors":"S. Tanakamaru, Yuta Kitamura, Senju Yamazaki, Tsukasa Tokutomi, K. Takeuchi","doi":"10.1109/VLSIC.2014.6858406","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858406","url":null,"abstract":"Application-aware solid-state drives (SSDs) with 2 adaptive coding schemes to improve reliability are presented. In NAND flash memory, a direct reliability trade-off exists between write/erase (W/E) cycle and data-retention (DR) time. Thus, SSDs can be used for applications that have long DR time and low W/E cycles, or short DR time with high W/E cycles. The n-out-of-8 level cell (nLC) scheme is proposed for low-cost, long-term, archive storage which is indispensable to preserve human digital data. nLC eliminates the memory states of the Triple-Level Cell (TLC) NAND flash memory from 8 to 7...4 levels. Universal asymmetric coding (UAC) is also proposed for cloud/security camera/enterprise storage environments which require high endurance but shorter DR time. Both nLC and UAC optimize coding based on the applications' required W/E cycle and DR. Bit-error rates (BERs) are improved by 79% and 52% with nLC and UAC, respectively.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133503660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858446
R. Nandwana, Tejasvi Anand, Saurabh Saxena, S. Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, A. Elshazly, P. Hanumolu
A calibration-free ring oscillator based fractional-N clock multiplier using hybrid phase/current-mode phase interpolator is presented. Fabricated in 65nm CMOS process, the prototype generates fractional frequencies from 4.25GHz-to-4.75GHz with in-band noise floor of -104dBc/Hz and 1.5ps integrated jitter. The clock multiplier achieves power efficiency of 2.4mW/GHz and FoM of -225.8dB.
{"title":"A 4.25GHz–4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement","authors":"R. Nandwana, Tejasvi Anand, Saurabh Saxena, S. Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, A. Elshazly, P. Hanumolu","doi":"10.1109/VLSIC.2014.6858446","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858446","url":null,"abstract":"A calibration-free ring oscillator based fractional-N clock multiplier using hybrid phase/current-mode phase interpolator is presented. Fabricated in 65nm CMOS process, the prototype generates fractional frequencies from 4.25GHz-to-4.75GHz with in-band noise floor of -104dBc/Hz and 1.5ps integrated jitter. The clock multiplier achieves power efficiency of 2.4mW/GHz and FoM of -225.8dB.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"224 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133460699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858444
Kiduk Kim, Sanghyub Kang, Yoon-Kyung Choi, Kyung-Hoon Lee, Choong-Hoon Lee, Jin-chul Lee, Michael Choi, Kyungjun Ko, Joonwoo Jung, Namgu Park, Hojin Park, Gyoo-cheol Hwang
A fully-differential capacitive touch sensing method is proposed in which common-mode noise currents are symmetrically subtracted at the differential input of the first stage such that it doesn't contribute to dynamic range reduction in the later stages. And, for better sensitivity, the proposed method could accumulate signal charges in continuous time domain, and does not suffer from aliasing issues observed in many discrete-time charge integrating methods. Measurement results showed 42 dB SNR for a 1-mm diameter stylus on a 5-inch full-HD on-cell touch display panel.
{"title":"A fully-differential capacitive touch controller with input common-mode feedback for symmetric display noise cancellation","authors":"Kiduk Kim, Sanghyub Kang, Yoon-Kyung Choi, Kyung-Hoon Lee, Choong-Hoon Lee, Jin-chul Lee, Michael Choi, Kyungjun Ko, Joonwoo Jung, Namgu Park, Hojin Park, Gyoo-cheol Hwang","doi":"10.1109/VLSIC.2014.6858444","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858444","url":null,"abstract":"A fully-differential capacitive touch sensing method is proposed in which common-mode noise currents are symmetrically subtracted at the differential input of the first stage such that it doesn't contribute to dynamic range reduction in the later stages. And, for better sensitivity, the proposed method could accumulate signal charges in continuous time domain, and does not suffer from aliasing issues observed in many discrete-time charge integrating methods. Measurement results showed 42 dB SNR for a 1-mm diameter stylus on a 5-inch full-HD on-cell touch display panel.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114396570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858448
Chunyang Zhai, Jeffrey Fredenburg, John Bell, M. Flynn
A novel self-filtering scheme breaks the typical tradeoff between noise and power, enabling a ring oscillator to approach the phase noise performance of an LC oscillator. The prototype N-path filter enhanced voltage-controlled ring oscillator (NPFRVCO) achieves a measured phase noise of -110dBc/Hz at a 1MHz offset frequency for an oscillation frequency of 1.0GHz. The self-clocked N-path filter reduces the phase noise by 10dB and 28dB for 1.0GHz and 300MHz oscillation frequencies, respectively. Implemented in 65nm CMOS, the NPFRVCO occupies a die area of 0.015 mm2 and consumes 4.7mW from 1.2V power supply when operating at 1.0GHz. The NPFRVCO has a measured frequency tuning range from 300MHz to 1.6GHz and achieves a FoM of 163dB at 1MHz offset.
{"title":"An N-path filter enhanced low phase noise ring VCO","authors":"Chunyang Zhai, Jeffrey Fredenburg, John Bell, M. Flynn","doi":"10.1109/VLSIC.2014.6858448","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858448","url":null,"abstract":"A novel self-filtering scheme breaks the typical tradeoff between noise and power, enabling a ring oscillator to approach the phase noise performance of an LC oscillator. The prototype N-path filter enhanced voltage-controlled ring oscillator (NPFRVCO) achieves a measured phase noise of -110dBc/Hz at a 1MHz offset frequency for an oscillation frequency of 1.0GHz. The self-clocked N-path filter reduces the phase noise by 10dB and 28dB for 1.0GHz and 300MHz oscillation frequencies, respectively. Implemented in 65nm CMOS, the NPFRVCO occupies a die area of 0.015 mm2 and consumes 4.7mW from 1.2V power supply when operating at 1.0GHz. The NPFRVCO has a measured frequency tuning range from 300MHz to 1.6GHz and achieves a FoM of 163dB at 1MHz offset.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127396579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858419
H. Hedayati, V. Aparin, K. Entesari
The real challenge in designing wide-band receivers is the ability to tolerate out of band blockers. In this paper, different blocker rejection techniques are proposed to significantly improve the linearity. The blockers are first rejected prior to the LNA, then, a novel base-band blocker filtering technique further rejects the blockers at the TIA input. A dual mixer architecture is also employed to further attenuate blockers. Finally, a very low impedance TIA is designed to improve the linearity of the entire receiver chain. The receiver has an IIP3 of +22 dBm and a NF of 3.5 dB in 0.18 μm CMOS technology.
{"title":"A +22dBm IIP3 and 3.5dB NF wideband receiver with RF and baseband blocker filtering techniques","authors":"H. Hedayati, V. Aparin, K. Entesari","doi":"10.1109/VLSIC.2014.6858419","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858419","url":null,"abstract":"The real challenge in designing wide-band receivers is the ability to tolerate out of band blockers. In this paper, different blocker rejection techniques are proposed to significantly improve the linearity. The blockers are first rejected prior to the LNA, then, a novel base-band blocker filtering technique further rejects the blockers at the TIA input. A dual mixer architecture is also employed to further attenuate blockers. Finally, a very low impedance TIA is designed to improve the linearity of the entire receiver chain. The receiver has an IIP3 of +22 dBm and a NF of 3.5 dB in 0.18 μm CMOS technology.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125896392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858371
A. Bannon, Christopher P. Hurrell, Derek Hummerston, C. Lyden
This paper presents an 18 bit 5 MS/s SAR ADC. It has a dynamic range of 100.2 dB, SNR of 99 dB, INL of ±2 ppm and DNL of ±0.4 ppm. It has currently the lowest noise floor of any monolithic Nyquist converter relative to the full scale input (21.9 nV/√Hz, ±5V full scale) known to the author, all of this is achieved with an ADC core power of 30.52 mW giving a Schreier figure of merit of 179.3 dB [1]. Architectural choices such as the use of a residue amplifier are outlined that enable the high sample rate, low noise and power efficiency. The design is implemented on 0.18 μm CMOS with MIM capacitors and both 1.8 V and 5 V MOS devices. An LVDS interface is used to transfer the ADC result off chip.
{"title":"An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic range","authors":"A. Bannon, Christopher P. Hurrell, Derek Hummerston, C. Lyden","doi":"10.1109/VLSIC.2014.6858371","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858371","url":null,"abstract":"This paper presents an 18 bit 5 MS/s SAR ADC. It has a dynamic range of 100.2 dB, SNR of 99 dB, INL of ±2 ppm and DNL of ±0.4 ppm. It has currently the lowest noise floor of any monolithic Nyquist converter relative to the full scale input (21.9 nV/√Hz, ±5V full scale) known to the author, all of this is achieved with an ADC core power of 30.52 mW giving a Schreier figure of merit of 179.3 dB [1]. Architectural choices such as the use of a residue amplifier are outlined that enable the high sample rate, low noise and power efficiency. The design is implemented on 0.18 μm CMOS with MIM capacitors and both 1.8 V and 5 V MOS devices. An LVDS interface is used to transfer the ADC result off chip.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125248226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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