Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858403
H. Noguchi, K. Ikegami, N. Shimomura, T. Tanamoto, J. Ito, S. Fujita
This paper presents a novel nonvolatile last level cache (LLC) based on the advanced perpendicular STT-MRAM to reduce the total power consumption of LLC. The presented LLC has novel readout circuit with the dual-sensing salvation scheme that enhances reliability of STT-MRAM along with typical error-correcting code (ECC). The comparison of CPU performance per power with SRAM-based, embedded DRAM and conventional STT-MRAM-based LLCs indicates that the presented novel nonvolatile LLC is the most suitable for large LLC.
{"title":"Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU","authors":"H. Noguchi, K. Ikegami, N. Shimomura, T. Tanamoto, J. Ito, S. Fujita","doi":"10.1109/VLSIC.2014.6858403","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858403","url":null,"abstract":"This paper presents a novel nonvolatile last level cache (LLC) based on the advanced perpendicular STT-MRAM to reduce the total power consumption of LLC. The presented LLC has novel readout circuit with the dual-sensing salvation scheme that enhances reliability of STT-MRAM along with typical error-correcting code (ECC). The comparison of CPU performance per power with SRAM-based, embedded DRAM and conventional STT-MRAM-based LLCs indicates that the presented novel nonvolatile LLC is the most suitable for large LLC.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131150641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858426
D. Bol, G. D. Streel, F. Botman, A. K. Lusala, N. Couniot
We propose a CMOS image sensor operating at ultra-low voltage (ULV) in a 65-nm low-power (LP) CMOS logic process for ultra-low-power SoC integration. Energy of 17-pJ/frame.pixel and 4×4-μm pixel size with 57-% fill factor are achieved at 0.5 V with digital pixel sensor (DPS) and time-based readout while reaching 40-dB dynamic range (DR) despite high leakage currents and Vt variability, thanks to delta-reset sampling (DRS) as well as gating and adaptive body biasing (ABB) of the 2-transistor (2-T) in-pixel comparator.
{"title":"A 65-nm 0.5-V 17-pJ/frame.pixel DPS CMOS image sensor for ultra-low-power SoCs achieving 40-dB dynamic range","authors":"D. Bol, G. D. Streel, F. Botman, A. K. Lusala, N. Couniot","doi":"10.1109/VLSIC.2014.6858426","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858426","url":null,"abstract":"We propose a CMOS image sensor operating at ultra-low voltage (ULV) in a 65-nm low-power (LP) CMOS logic process for ultra-low-power SoC integration. Energy of 17-pJ/frame.pixel and 4×4-μm pixel size with 57-% fill factor are achieved at 0.5 V with digital pixel sensor (DPS) and time-based readout while reaching 40-dB dynamic range (DR) despite high leakage currents and Vt variability, thanks to delta-reset sampling (DRS) as well as gating and adaptive body biasing (ABB) of the 2-transistor (2-T) in-pixel comparator.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130538044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858398
Chan-Hsiang Weng, Tzu-An Wei, E. Alpman, C. Fu, Yi-Ting Tseng, Tsung-Hsien Lin
A power-efficient continuous-time delta-sigma modulator (CTDSM) employing a single-amplifier biquad (SAB) based topology is proposed. The modulator incorporates a proposed twin-T SAB topology where the excess loop delay (ELD) is compensated by injecting a feedback signal into an internal node of the SAB while cooperating with an additional phase-compensation resistor. A low-power time-to-digital converter (TDC) with an embedded data weighted averaging (DWA) function is proposed as the quantizer, which mitigates the mismatch issue in the feedback DACs. Fabricated in 90nm CMOS, the proposed CTDSM achieves peak SNDR of 67.2dB over an 8.5MHz signal bandwidth, while consuming 4.3mW at 300MHz sampling frequency, and scores a FoM of 135fJ/conv.-step.
{"title":"An 8.5MHz 67.2dB SNDR CTDSM with ELD compensation embedded twin-T SAB and circular TDC-based quantizer in 90nm CMOS","authors":"Chan-Hsiang Weng, Tzu-An Wei, E. Alpman, C. Fu, Yi-Ting Tseng, Tsung-Hsien Lin","doi":"10.1109/VLSIC.2014.6858398","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858398","url":null,"abstract":"A power-efficient continuous-time delta-sigma modulator (CTDSM) employing a single-amplifier biquad (SAB) based topology is proposed. The modulator incorporates a proposed twin-T SAB topology where the excess loop delay (ELD) is compensated by injecting a feedback signal into an internal node of the SAB while cooperating with an additional phase-compensation resistor. A low-power time-to-digital converter (TDC) with an embedded data weighted averaging (DWA) function is proposed as the quantizer, which mitigates the mismatch issue in the feedback DACs. Fabricated in 90nm CMOS, the proposed CTDSM achieves peak SNDR of 67.2dB over an 8.5MHz signal bandwidth, while consuming 4.3mW at 300MHz sampling frequency, and scores a FoM of 135fJ/conv.-step.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124942936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858438
H. Krishnamurthy, V. Vaidya, Pavan Kumar, G. Matthew, Sheldon Weng, Bharani Thiruvengadam, W. Proefrock, K. Ravichandran, V. De
A fully on-die, digitally controlled, 500MHz switching, 250mA rated output buck Voltage Regulator (VR) implemented in 22nm Tri-Gate CMOS is presented. The silicon measured a peak efficiency of 68% and consumed an area of 0.6mm2 (without output decoupling) with a power density of about 410 mW/mm2. The paper also demonstrates a controller bandwidth of 43MHz; the highest reported to date for any digital controller, resulting in output voltage ramp rates as high as 10V/μsec.
{"title":"A 500 MHz, 68% efficient, fully on-die digitally controlled buck Voltage Regulator on 22nm Tri-Gate CMOS","authors":"H. Krishnamurthy, V. Vaidya, Pavan Kumar, G. Matthew, Sheldon Weng, Bharani Thiruvengadam, W. Proefrock, K. Ravichandran, V. De","doi":"10.1109/VLSIC.2014.6858438","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858438","url":null,"abstract":"A fully on-die, digitally controlled, 500MHz switching, 250mA rated output buck Voltage Regulator (VR) implemented in 22nm Tri-Gate CMOS is presented. The silicon measured a peak efficiency of 68% and consumed an area of 0.6mm2 (without output decoupling) with a power density of about 410 mW/mm2. The paper also demonstrates a controller bandwidth of 43MHz; the highest reported to date for any digital controller, resulting in output voltage ramp rates as high as 10V/μsec.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129402798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858420
S. Mathew, Sudhir K. Satpathy, Vikram B. Suresh, Himanshu Kaul, M. Anders, Gregory K. Chen, A. Agarwal, S. Hsu, R. Krishnamurthy
An on-die, lightweight nanoAES hardware accelerator is fabricated in 22nm tri-gate CMOS, targeted for ultra-low power mobile SOCs. Compared to conventional 128-bit AES implementations, this design uses an 8-bit Sbox datapath along with ShiftRow byte-order processing to compute all AES rounds in native GF(24)2 composite-field. This approach along with a serial-accumulating MixColumns circuit, area-optimized encrypt and decrypt Galois-field polynomials and integrated on-the-fly key generation circuit results in a compact 2090-gate design, enabling peak energy-efficiency of 289Gbps/W and AES-128 encrypt/decrypt throughput of 432/671Mbps with total energy consumption of 4.7/3nJ measured at 0.9V, 25°C.
{"title":"340mV–1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(24)2 polynomials in 22nm tri-gate CMOS","authors":"S. Mathew, Sudhir K. Satpathy, Vikram B. Suresh, Himanshu Kaul, M. Anders, Gregory K. Chen, A. Agarwal, S. Hsu, R. Krishnamurthy","doi":"10.1109/VLSIC.2014.6858420","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858420","url":null,"abstract":"An on-die, lightweight nanoAES hardware accelerator is fabricated in 22nm tri-gate CMOS, targeted for ultra-low power mobile SOCs. Compared to conventional 128-bit AES implementations, this design uses an 8-bit Sbox datapath along with ShiftRow byte-order processing to compute all AES rounds in native GF(24)2 composite-field. This approach along with a serial-accumulating MixColumns circuit, area-optimized encrypt and decrypt Galois-field polynomials and integrated on-the-fly key generation circuit results in a compact 2090-gate design, enabling peak energy-efficiency of 289Gbps/W and AES-128 encrypt/decrypt throughput of 432/671Mbps with total energy consumption of 4.7/3nJ measured at 0.9V, 25°C.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127568319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858412
M. Bhargava, Y. Chong, Vincent Schuppe, B. Maiti, M. Kinkade, Hsin-Yu Chen, A. Chen, S. Mangal, Jacek Wiatrowski, G. Gouya, A. Baradia, S. Thyagarajan, Gus Yeung
Measured results of VMIN from 20nm SRAM arrays with read and write assist techniques are presented for multiple flavors of bitcell. A novel assist technique is presented, that provides both read and write assist by controlling only the voltage of wordline (WL) and without using a separate supply voltage. The WL-drivers use a WL float technique to reduce the dc-path current compared to existing WL under-drive read assist designs. The assist technique resulted in a VMIN improvement of 143mV for the high-density 6T (6T-HD) SRAM, 96mV for the high-speed 6T (6T-HS) SRAM, and 86mV for the 8T dual-port (DP) SRAM.
{"title":"Low VMIN 20nm embedded SRAM with multi-voltage wordline control based read and write assist techniques","authors":"M. Bhargava, Y. Chong, Vincent Schuppe, B. Maiti, M. Kinkade, Hsin-Yu Chen, A. Chen, S. Mangal, Jacek Wiatrowski, G. Gouya, A. Baradia, S. Thyagarajan, Gus Yeung","doi":"10.1109/VLSIC.2014.6858412","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858412","url":null,"abstract":"Measured results of VMIN from 20nm SRAM arrays with read and write assist techniques are presented for multiple flavors of bitcell. A novel assist technique is presented, that provides both read and write assist by controlling only the voltage of wordline (WL) and without using a separate supply voltage. The WL-drivers use a WL float technique to reduce the dc-path current compared to existing WL under-drive read assist designs. The assist technique resulted in a VMIN improvement of 143mV for the high-density 6T (6T-HD) SRAM, 96mV for the high-speed 6T (6T-HS) SRAM, and 86mV for the 8T dual-port (DP) SRAM.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128660633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858436
Harsh Mehta, G. Krishnamurthy, M. Inerfield, Fang Lin, T. Kwan
A fourth-order Chebyshev high-pass filter (HPF) that achieves input-referred noise of 3 nV/√Hz, MTPR greater than 72 dB, and power consumption of less than 81 mW with 0.7 mm2 area in 28 nm CMOS is presented. Area and power reductions are realized via a mixed-signal filter topology.
{"title":"A 3nV/vHz programmable gain/BW mixed-signal 4th order Chebyshev high-pass filter for ADSL/VDSL analog front end in 28nm CMOS","authors":"Harsh Mehta, G. Krishnamurthy, M. Inerfield, Fang Lin, T. Kwan","doi":"10.1109/VLSIC.2014.6858436","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858436","url":null,"abstract":"A fourth-order Chebyshev high-pass filter (HPF) that achieves input-referred noise of 3 nV/√Hz, MTPR greater than 72 dB, and power consumption of less than 81 mW with 0.7 mm2 area in 28 nm CMOS is presented. Area and power reductions are realized via a mixed-signal filter topology.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122792508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858397
A. Bandyopadhyay, R. Adams, K. Nguyen, P. Baginski, David Lamb, Thomas Tansley
A continuous time 5-bit feed forward ΔΣ ADC architecture is presented, which measures 97.3 dB SNR, over 600 kHz bandwidth while consuming 31 mW/channel. This performance is achieved by using an ISI mitigation scheme and a 2nd-order DEM for 3-level DACs along with analog low power techniques. The 0.99mm2/channel chip was fabricated in 0.18um CMOS process, and achieves a FOM of 171.8 dB.
{"title":"A 97.3 dB SNR, 600 kHz BW, 31mW multibit continuous time ΔΣ ADC","authors":"A. Bandyopadhyay, R. Adams, K. Nguyen, P. Baginski, David Lamb, Thomas Tansley","doi":"10.1109/VLSIC.2014.6858397","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858397","url":null,"abstract":"A continuous time 5-bit feed forward ΔΣ ADC architecture is presented, which measures 97.3 dB SNR, over 600 kHz bandwidth while consuming 31 mW/channel. This performance is achieved by using an ISI mitigation scheme and a 2nd-order DEM for 3-level DACs along with analog low power techniques. The 0.99mm2/channel chip was fabricated in 0.18um CMOS process, and achieves a FOM of 171.8 dB.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115905660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858363
Inhee Lee, Yoonmyung Lee, D. Sylvester, D. Blaauw
We propose a battery supervisory circuit (BSC) for wireless sensor nodes that automatically adapts to varying battery health, as reflected by its internal resistance (RBAT), and establishes a constant effective threshold voltage. Compared to a conventional fixed-threshold BSC, the new design avoids oscillation and widens the usable range of battery voltages, independent of RBAT. RBAT is measured by inducing a test current using decaps and measuring the resulting battery RC response time. When tested with a 2μAh battery and 11μA sensor system, the BSC reduces the required hysteresis from 656mV to 77mV, increasing the usable battery voltage range by 2.7×.
{"title":"Low power battery supervisory circuit with adaptive battery health monitor","authors":"Inhee Lee, Yoonmyung Lee, D. Sylvester, D. Blaauw","doi":"10.1109/VLSIC.2014.6858363","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858363","url":null,"abstract":"We propose a battery supervisory circuit (BSC) for wireless sensor nodes that automatically adapts to varying battery health, as reflected by its internal resistance (RBAT), and establishes a constant effective threshold voltage. Compared to a conventional fixed-threshold BSC, the new design avoids oscillation and widens the usable range of battery voltages, independent of RBAT. RBAT is measured by inducing a test current using decaps and measuring the resulting battery RC response time. When tested with a 2μAh battery and 11μA sensor system, the BSC reduces the required hysteresis from 656mV to 77mV, increasing the usable battery voltage range by 2.7×.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126488984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858382
Takayuki Abe, T. Morie, Kazutoshi Satou, D. Nomasaki, S. Nakamura, Y. Horiuchi, K. Imamura
This paper presents an ultra-low-power 2-step wake-up receiver for the IEEE 802.15.4g. The receiver is composed of an ultra-low-power energy-detection receiver (EDRX) and an address-detection FSK receiver (ADRX). The ADRX is activated only when the EDRX detects a wakeup packet which minimizes power consumption. Fabricated in a 65 nm CMOS process, the receiver achieves an excellent receiver sensitivity of -87 dBm while consuming only 45.5 μW average power.
{"title":"An ultra-low-power 2-step wake-up receiver for IEEE 802.15.4g wireless sensor networks","authors":"Takayuki Abe, T. Morie, Kazutoshi Satou, D. Nomasaki, S. Nakamura, Y. Horiuchi, K. Imamura","doi":"10.1109/VLSIC.2014.6858382","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858382","url":null,"abstract":"This paper presents an ultra-low-power 2-step wake-up receiver for the IEEE 802.15.4g. The receiver is composed of an ultra-low-power energy-detection receiver (EDRX) and an address-detection FSK receiver (ADRX). The ADRX is activated only when the EDRX detects a wakeup packet which minimizes power consumption. Fabricated in a 65 nm CMOS process, the receiver achieves an excellent receiver sensitivity of -87 dBm while consuming only 45.5 μW average power.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125632681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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