Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858424
Yildiz Sinangil, Sabrina M. Neuman, M. Sinangil, N. Ickes, George B. P. Bezerra, Eric Lau, Jason E. Miller, H. Hoffmann, S. Devadas, A. Chandrakasan
This paper presents a self-aware processor with energy monitoring circuits that can measure actual energy consumption of the key blocks. The monitors are embedded into on-chip DC/DC converters and generate results within 10% of accuracy with minimal power (<;0.1%) and area (<;1%) overhead. Our system, which is implemented in 0.18μm technology, is designed to be voltage scalable from 1.8V down to 0.6V. Low-voltage SRAM operation is made possible through the use of 8T bit-cells and write-assists. The d-caches are designed to be re-configurable in associativity and size to adapt to compute- versus cache-bound phases of applications. Cache configuration is performed in <; 3 clock cycles including tag invalidation. These hardware features enable a software self-aware computation engine (SEEC) to dynamically adapt the processor to meet performance and energy goals. Measurement results show that up to 8.4× energy savings can be achieved with DVFS and self-adaptation.
{"title":"A self-aware processor SoC using energy monitors integrated into power converters for self-adaptation","authors":"Yildiz Sinangil, Sabrina M. Neuman, M. Sinangil, N. Ickes, George B. P. Bezerra, Eric Lau, Jason E. Miller, H. Hoffmann, S. Devadas, A. Chandrakasan","doi":"10.1109/VLSIC.2014.6858424","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858424","url":null,"abstract":"This paper presents a self-aware processor with energy monitoring circuits that can measure actual energy consumption of the key blocks. The monitors are embedded into on-chip DC/DC converters and generate results within 10% of accuracy with minimal power (<;0.1%) and area (<;1%) overhead. Our system, which is implemented in 0.18μm technology, is designed to be voltage scalable from 1.8V down to 0.6V. Low-voltage SRAM operation is made possible through the use of 8T bit-cells and write-assists. The d-caches are designed to be re-configurable in associativity and size to adapt to compute- versus cache-bound phases of applications. Cache configuration is performed in <; 3 clock cycles including tag invalidation. These hardware features enable a software self-aware computation engine (SEEC) to dynamically adapt the processor to meet performance and energy goals. Measurement results show that up to 8.4× energy savings can be achieved with DVFS and self-adaptation.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130556891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858422
Chang-Hung Tsai, Tung-Yu Wu, S. Hsu, Chia-Ching Chu, Fang-Ju Ku, Ying-Siou Laio, Chih-Lung Chen, W. Wong, Hsie-Chia Chang, Chen-Yi Lee
A data-driven machine learning processor (D2MLP) with MIMD architecture is designed for big data analysis. Adopting the configurable counting engine array with 3-layer dimension merging, the D2MLP processes maximal 1-128/1024 dimensional data with parallel 64/8 queries in learning stage. Implement in 90nm CMOS technology, the D2MLP achieves 219.9x and 8.2x faster processing time than CPU and GPGPU, respectively. In application phase, maximal 22.7k 128-class classifications/s are performed with the learned density model. Operated at 1.0V and 165MHz, the D2MLP demonstrates an energy-efficient solution for learning and classification with 7.11mJ/Gb/query and 2.3μJ/classification, respectively.
{"title":"A 7.11mJ/Gb/query data-driven machine learning processor (D2MLP) for big data analysis and applications","authors":"Chang-Hung Tsai, Tung-Yu Wu, S. Hsu, Chia-Ching Chu, Fang-Ju Ku, Ying-Siou Laio, Chih-Lung Chen, W. Wong, Hsie-Chia Chang, Chen-Yi Lee","doi":"10.1109/VLSIC.2014.6858422","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858422","url":null,"abstract":"A data-driven machine learning processor (D2MLP) with MIMD architecture is designed for big data analysis. Adopting the configurable counting engine array with 3-layer dimension merging, the D2MLP processes maximal 1-128/1024 dimensional data with parallel 64/8 queries in learning stage. Implement in 90nm CMOS technology, the D2MLP achieves 219.9x and 8.2x faster processing time than CPU and GPGPU, respectively. In application phase, maximal 22.7k 128-class classifications/s are performed with the learned density model. Operated at 1.0V and 165MHz, the D2MLP demonstrates an energy-efficient solution for learning and classification with 7.11mJ/Gb/query and 2.3μJ/classification, respectively.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132518111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858453
M. Inerfield, Abhishek Kamath, Feng Su, Jason Hu, Xinyu Yu, V. Fong, Omar Alnaggar, Fang Lin, T. Kwan
Recent publications have demonstrated ADCs with ENOB > 11, sampling frequencies > 50MHz, with power <; 50mW, making the SAR ADC architecture an attractive alternative to the traditional pipeline. This paper presents a production quality 11.5 ENOB, 89dB SFDR, 100MS/s SAR ADC that, including the voltage reference and digital calibration circuitry, consumes 8mW and uses 0.1mm2 in 28nm CMOS. It uses a unique dual-reference, dual unit-cap architecture with a regulated DAC switch, providing a 2Vppd input swing while utilizing a low-voltage transistor implementation for the core ADC.
{"title":"An 11.5-ENOB 100-MS/s 8mW dual-reference SAR ADC in 28nm CMOS","authors":"M. Inerfield, Abhishek Kamath, Feng Su, Jason Hu, Xinyu Yu, V. Fong, Omar Alnaggar, Fang Lin, T. Kwan","doi":"10.1109/VLSIC.2014.6858453","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858453","url":null,"abstract":"Recent publications have demonstrated ADCs with ENOB > 11, sampling frequencies > 50MHz, with power <; 50mW, making the SAR ADC architecture an attractive alternative to the traditional pipeline. This paper presents a production quality 11.5 ENOB, 89dB SFDR, 100MS/s SAR ADC that, including the voltage reference and digital calibration circuitry, consumes 8mW and uses 0.1mm2 in 28nm CMOS. It uses a unique dual-reference, dual unit-cap architecture with a regulated DAC switch, providing a 2Vppd input swing while utilizing a low-voltage transistor implementation for the core ADC.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122262331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858399
Hao Li, Shuai Chen, Liqiong Yang, Rui Bai, Weiwu Hu, Freeman Y. Zhong, S. Palermo, P. Chiang
A quarter-rate forwarded-clock receiver utilizes an edge-rotating 5/4X sub-rate CDR for improved jitter tolerance with low power overhead relative to conventional 2X oversampling CDR systems. Low-voltage operation is achieved with efficient quarter-rate clock generation from an injection-locked oscillator (ILO) and through automatic independent phase rotator control that optimizes timing margin of each input quantizer in the presence of receive-side clock static phase errors and transmitter duty-cycle distortion (DCD). Fabricated in GP 65nm CMOS, the receiver operates up to 16Gb/s with a BER<;10-12, achieves a 1MHz phase tracking bandwidth, tolerates ±50%UIpp DCD on input data, and has 14Gb/s energy efficiency of 560fJ/bit at VDD=0.8V.
{"title":"A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with input duty-cycle distortion tolerable edge-rotating 5/4X sub-rate CDR in 65nm CMOS","authors":"Hao Li, Shuai Chen, Liqiong Yang, Rui Bai, Weiwu Hu, Freeman Y. Zhong, S. Palermo, P. Chiang","doi":"10.1109/VLSIC.2014.6858399","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858399","url":null,"abstract":"A quarter-rate forwarded-clock receiver utilizes an edge-rotating 5/4X sub-rate CDR for improved jitter tolerance with low power overhead relative to conventional 2X oversampling CDR systems. Low-voltage operation is achieved with efficient quarter-rate clock generation from an injection-locked oscillator (ILO) and through automatic independent phase rotator control that optimizes timing margin of each input quantizer in the presence of receive-side clock static phase errors and transmitter duty-cycle distortion (DCD). Fabricated in GP 65nm CMOS, the receiver operates up to 16Gb/s with a BER<;10-12, achieves a 1MHz phase tracking bandwidth, tolerates ±50%UIpp DCD on input data, and has 14Gb/s energy efficiency of 560fJ/bit at VDD=0.8V.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130173805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858450
Yuji Satoh, Hiroyuki Kobayashi, T. Miyaba, S. Kousai
A novel on-chip frequency calibration of temperature dependency is proposed for CMOS reference frequency generator. High-order temperature coefficients are rapidly extracted by employing a carefully designed on-chip heater, so that the frequency deviation due to the temperature variation is accurately estimated, and compensated in digitally by means of all-digital PLL (ADPLL). The proposed technique was implemented in a 0.18um CMOS and achieved ±85ppm accuracy at 24MHz, consuming a power of 2.9mW.
{"title":"A 2.9mW, +/− 85ppm accuracy reference clock generator based on RC oscillator with on-chip temperature calibration","authors":"Yuji Satoh, Hiroyuki Kobayashi, T. Miyaba, S. Kousai","doi":"10.1109/VLSIC.2014.6858450","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858450","url":null,"abstract":"A novel on-chip frequency calibration of temperature dependency is proposed for CMOS reference frequency generator. High-order temperature coefficients are rapidly extracted by employing a carefully designed on-chip heater, so that the frequency deviation due to the temperature variation is accurately estimated, and compensated in digitally by means of all-digital PLL (ADPLL). The proposed technique was implemented in a 0.18um CMOS and achieved ±85ppm accuracy at 24MHz, consuming a power of 2.9mW.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129489926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858359
T. Hashida, Y. Tomita, Yuuki Ogata, Kosuke Suzuki, S. Suzuki, Takanori Nakao, Yuji Terao, Satofumi Honda, Sota Sakabayashi, Ryuichi Nishiyama, A. Konmoto, Yoshitomo Ozeki, H. Adachi, H. Yamaguchi, Y. Koyanagi, H. Tamura
A 36-Gbps transceiver with a continuous-time linear equalizer and a 1-tap DFE in 20-nm CMOS is demonstrated. The transceiver uses a quarter-rate (i.e., 9-GHz) differential-clock distribution to reduce the clock-delivery power. Multi-phase half-rate clock signals that drive the transceiver front-ends are generated by a delay-locked loop and frequency doublers that systematically reduce the impact of skew and jitter. The transceiver occupies 0.55 mm2 and consumes 609.9 mW of power from a 0.9-V supply.
{"title":"A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution","authors":"T. Hashida, Y. Tomita, Yuuki Ogata, Kosuke Suzuki, S. Suzuki, Takanori Nakao, Yuji Terao, Satofumi Honda, Sota Sakabayashi, Ryuichi Nishiyama, A. Konmoto, Yoshitomo Ozeki, H. Adachi, H. Yamaguchi, Y. Koyanagi, H. Tamura","doi":"10.1109/VLSIC.2014.6858359","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858359","url":null,"abstract":"A 36-Gbps transceiver with a continuous-time linear equalizer and a 1-tap DFE in 20-nm CMOS is demonstrated. The transceiver uses a quarter-rate (i.e., 9-GHz) differential-clock distribution to reduce the clock-delivery power. Multi-phase half-rate clock signals that drive the transceiver front-ends are generated by a delay-locked loop and frequency doublers that systematically reduce the impact of skew and jitter. The transceiver occupies 0.55 mm2 and consumes 609.9 mW of power from a 0.9-V supply.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124241505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858387
Fang-Li Yuan, Tsung-Han Yu, D. Markovic
A blind classification processor for cognitive radios is realized in 40nm CMOS, featuring three-step parameter estimation for a 59× energy saving compared to an exhaustive method, and multi-algorithm feature extraction to distinguish five modulation classes: multicarrier, single-carrier PSK/QAM/MSK, and spread-spectrum signals. The chip consumes 17μJ within 2ms sensing time per classification, achieving ≥95% detection probability (PD) and ≤0.5% false-alarm rate (PFA) at 10dB SNR in a 500MHz channel.
{"title":"A 500MHz blind classification processor for cognitive radios in 40nm CMOS","authors":"Fang-Li Yuan, Tsung-Han Yu, D. Markovic","doi":"10.1109/VLSIC.2014.6858387","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858387","url":null,"abstract":"A blind classification processor for cognitive radios is realized in 40nm CMOS, featuring three-step parameter estimation for a 59× energy saving compared to an exhaustive method, and multi-algorithm feature extraction to distinguish five modulation classes: multicarrier, single-carrier PSK/QAM/MSK, and spread-spectrum signals. The chip consumes 17μJ within 2ms sensing time per classification, achieving ≥95% detection probability (PD) and ≤0.5% false-alarm rate (PFA) at 10dB SNR in a 500MHz channel.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131640014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858370
C. Liu, Chin-Hao Chang, H. Tu, C. Chao, F. Hsueh, Szu-Ying Chen, Vincent Hsu, Jen-Cheng Liu, D. Yaung, S. Wuu
A 1.1 um pitch pixel array fabricated by 45 nm 3D stacked technology, can be switched to peripheral circuits on same wafer or to other stacked wafer for process and signal integrity verification. It supports through silicon connection or direct connection to increase the flexibility by separating pixel array and sensing circuit. The novel wide operation range VCO and low power serializer are implemented to reduce the total power and noise.
{"title":"A peripheral switchable 3D stacked CMOS image sensor","authors":"C. Liu, Chin-Hao Chang, H. Tu, C. Chao, F. Hsueh, Szu-Ying Chen, Vincent Hsu, Jen-Cheng Liu, D. Yaung, S. Wuu","doi":"10.1109/VLSIC.2014.6858370","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858370","url":null,"abstract":"A 1.1 um pitch pixel array fabricated by 45 nm 3D stacked technology, can be switched to peripheral circuits on same wafer or to other stacked wafer for process and signal integrity verification. It supports through silicon connection or direct connection to increase the flexibility by separating pixel array and sensing circuit. The novel wide operation range VCO and low power serializer are implemented to reduce the total power and noise.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116790276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858431
Yen-Po Chen, D. Blaauw, D. Sylvester
A low power high efficiency neural signal recording amplifier with a novel multi-chopper technique is proposed and implemented in 180nm CMOS. The input referred rms noise is 1.54μV (1-500Hz) with 266nA tail current. The result corresponds to a 1.38 noise efficiency factor, which is the best reported among current state-of-the-art amplifiers.
{"title":"A 266nW multi-chopper amplifier with 1.38 noise efficiency factor for neural signal recording","authors":"Yen-Po Chen, D. Blaauw, D. Sylvester","doi":"10.1109/VLSIC.2014.6858431","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858431","url":null,"abstract":"A low power high efficiency neural signal recording amplifier with a novel multi-chopper technique is proposed and implemented in 180nm CMOS. The input referred rms noise is 1.54μV (1-500Hz) with 266nA tail current. The result corresponds to a 1.38 noise efficiency factor, which is the best reported among current state-of-the-art amplifiers.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128707362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858378
M. Georgas, B. Moss, Chen Sun, J. Shainline, J. Orcutt, M. Wade, Yu-hsin Chen, Kareem Nammari, J. Leu, Aravind Srinivasan, Rajeev J Ram, M. Popović, V. Stojanović
An optical transmitter and receiver with monolithically-integrated photonic devices and circuits are demonstrated together for the first time in a commercial 45nm SOI process, without any process changes. The transmitter features an interleaved-junction carrier-depletion ring modulator and operates at 3.5Gb/s with an 8dB extinction ratio and combined circuit and device energy cost of 70fJ/bit. The optical receiver connects to an integrated SiGe detector designed for 1180nm wavelength and performs at 2.5Gb/s with 15μA sensitivity and energy cost of 220fJ/bit.
{"title":"A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process","authors":"M. Georgas, B. Moss, Chen Sun, J. Shainline, J. Orcutt, M. Wade, Yu-hsin Chen, Kareem Nammari, J. Leu, Aravind Srinivasan, Rajeev J Ram, M. Popović, V. Stojanović","doi":"10.1109/VLSIC.2014.6858378","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858378","url":null,"abstract":"An optical transmitter and receiver with monolithically-integrated photonic devices and circuits are demonstrated together for the first time in a commercial 45nm SOI process, without any process changes. The transmitter features an interleaved-junction carrier-depletion ring modulator and operates at 3.5Gb/s with an 8dB extinction ratio and combined circuit and device energy cost of 70fJ/bit. The optical receiver connects to an integrated SiGe detector designed for 1180nm wavelength and performs at 2.5Gb/s with 15μA sensitivity and energy cost of 220fJ/bit.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121125132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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