Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858396
S. Ho, Chilun Lo, Z. Ru, Jialin Zhao
A 23mW, 80MHz BW, 73dB dynamic range continuous-time ΔΣ modulator in 20nm CMOS is presented. The modulator operates from 1.0/1.2/1.5V supplies. Power is minimized by combining a low OSR, fast digital excess loop delay compensation scheme, and several techniques to minimize delay in the feedback path. The result is a highly power efficient modulator that achieves an FOM(DR) of 168dB.
{"title":"A 23mW, 73dB dynamic range, 80MHz BW continuous-time delta-sigma modulator in 20nm CMOS","authors":"S. Ho, Chilun Lo, Z. Ru, Jialin Zhao","doi":"10.1109/VLSIC.2014.6858396","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858396","url":null,"abstract":"A 23mW, 80MHz BW, 73dB dynamic range continuous-time ΔΣ modulator in 20nm CMOS is presented. The modulator operates from 1.0/1.2/1.5V supplies. Power is minimized by combining a low OSR, fast digital excess loop delay compensation scheme, and several techniques to minimize delay in the feedback path. The result is a highly power efficient modulator that achieves an FOM(DR) of 168dB.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126331197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858357
E. Doller, Ameen Akel, Jeffrey Wang, Ken Curewitz, S. Eilert
In the years between now and 2020, we should expect continued exponential data growth [15][16]. A number of ongoing advances in storage: the transition to solid-state drives (SSDs), the scaling of NAND flash capacity, and advanced silicon packaging techniques will dramatically increase the capacity of storage subsystems over the same timeframe. This will significantly reduce the ratio of storage bandwidth to storage density. Consequently, the majority of data in 2020 will either be cold or will require near-memory acceleration to pull rich information out of the sea of big data. We argue that, increasingly over time, value lies not merely in the size of the data, but rather in what one can do with it.
{"title":"DataCenter 2020: Near-memory acceleration for data-oriented applications","authors":"E. Doller, Ameen Akel, Jeffrey Wang, Ken Curewitz, S. Eilert","doi":"10.1109/VLSIC.2014.6858357","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858357","url":null,"abstract":"In the years between now and 2020, we should expect continued exponential data growth [15][16]. A number of ongoing advances in storage: the transition to solid-state drives (SSDs), the scaling of NAND flash capacity, and advanced silicon packaging techniques will dramatically increase the capacity of storage subsystems over the same timeframe. This will significantly reduce the ratio of storage bandwidth to storage density. Consequently, the majority of data in 2020 will either be cold or will require near-memory acceleration to pull rich information out of the sea of big data. We argue that, increasingly over time, value lies not merely in the size of the data, but rather in what one can do with it.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"318 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122220373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858407
Kiseok Song, U. Ha, Seongwook Park, H. Yoo
A multi-modal spectroscopy IC combining the impedance spectroscopy (IMPS) and the multi-wavelength near-infrared spectroscopy (mNIRS) is proposed for high precision non-invasive glucose level estimation. A frequency sweep (10kHz - 76kHz) sinusoidal oscillator (FSSO) is proposed for high resolution (500 steps) for IMPS. The output voltage swing of the FSSO is stabilized by an adaptive gain control (AGC). The measurement results of the IMPS and mNIRS are combined by an artificial neural network (ANN) in external smart device so that mean absolute relative difference (mARD) is enhanced to 8.3% from 15% of IMPS, 15% - 20% of mNIRS. A proposed 12.5mm2 0.18μm CMOS chip consumes peak power of 38mW at 1.5V.
{"title":"An impedance and multi-wavelength near-infrared spectroscopy IC for non-invasive blood glucose estimation","authors":"Kiseok Song, U. Ha, Seongwook Park, H. Yoo","doi":"10.1109/VLSIC.2014.6858407","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858407","url":null,"abstract":"A multi-modal spectroscopy IC combining the impedance spectroscopy (IMPS) and the multi-wavelength near-infrared spectroscopy (mNIRS) is proposed for high precision non-invasive glucose level estimation. A frequency sweep (10kHz - 76kHz) sinusoidal oscillator (FSSO) is proposed for high resolution (500 steps) for IMPS. The output voltage swing of the FSSO is stabilized by an adaptive gain control (AGC). The measurement results of the IMPS and mNIRS are combined by an artificial neural network (ANN) in external smart device so that mean absolute relative difference (mARD) is enhanced to 8.3% from 15% of IMPS, 15% - 20% of mNIRS. A proposed 12.5mm2 0.18μm CMOS chip consumes peak power of 38mW at 1.5V.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123879608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858417
Yu-Lun Chen, Chiro Kao, Pen-Jui Peng, Jri Lee
This work introduces a 94GHz duobinary keying wireless transceiver for point-to-point communications. It presents bandwidth efficiency twice as much as an OOK system and requires no carrier recovery and baseband circuitry to reduce power consumption. Designed and fabricated in 65nm CMOS, the transceiver achieves a 2.0-Gb/s data link with BER <; 10-9 while consuming a total power of 265mW.
{"title":"A 94GHz duobinary keying wireless transceiver in 65nm CMOS","authors":"Yu-Lun Chen, Chiro Kao, Pen-Jui Peng, Jri Lee","doi":"10.1109/VLSIC.2014.6858417","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858417","url":null,"abstract":"This work introduces a 94GHz duobinary keying wireless transceiver for point-to-point communications. It presents bandwidth efficiency twice as much as an OOK system and requires no carrier recovery and baseband circuitry to reduce power consumption. Designed and fabricated in 65nm CMOS, the transceiver achieves a 2.0-Gb/s data link with BER <; 10-9 while consuming a total power of 265mW.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123793172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A first-reported 4K×2K@60fps digital TV SoC processor supporting 9 video formats and integrating HDMI/MHL receiver is fabricated in a 40nm CMOS process. It adopts error compensation processor (ECP) to improve the visual quality, and designs a memory management unit and resource sharing technique to improve the throughput and area efficiency by 38.5% and 34.3%, respectively. Moreover, a lossless compression processor (LCP) is newly designed to reduce 30% and 45% of external data accesses in playback and gaming scenario, respectively. The proposed TV SoC processor includes multi-standard 4K×2K@60fps playback and 3.4Gbps HDMI receiver (Rx), and both scenario dissipate 198.15mW at 1.2V core and 3.3V I/O.
{"title":"A 4K×2K@60fps multi-standard TV SoC processor with integrated HDMI/MHL receiver","authors":"Chi-Cheng Ju, Tsu-Ming Liu, Huaide Wang, Yung-Chang Chang, Chih-Ming Wang, Chang-Lin Hsieh, Brian Liu, Hue-Min Lin, Chia-Yun Cheng, Chun-Chia Chen, Min-Hao Chiu, Sheng-Jen Wang, P. Chao, Meng-Jye Hu, Ryan Yeh, Ted Chuang, Hsiu-Yi Lin, Chung-Hung Tsai","doi":"10.1109/VLSIC.2014.6858389","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858389","url":null,"abstract":"A first-reported 4K×2K@60fps digital TV SoC processor supporting 9 video formats and integrating HDMI/MHL receiver is fabricated in a 40nm CMOS process. It adopts error compensation processor (ECP) to improve the visual quality, and designs a memory management unit and resource sharing technique to improve the throughput and area efficiency by 38.5% and 34.3%, respectively. Moreover, a lossless compression processor (LCP) is newly designed to reduce 30% and 45% of external data accesses in playback and gaming scenario, respectively. The proposed TV SoC processor includes multi-standard 4K×2K@60fps playback and 3.4Gbps HDMI receiver (Rx), and both scenario dissipate 198.15mW at 1.2V core and 3.3V I/O.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124577189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858425
Gyouho Kim, Yoonmyung Lee, Z. Foo, P. Pannuto, Ye-Sheng Kuo, B. Kempke, M. Ghaed, S. Bang, Inhee Lee, Yejoong Kim, Seokhyeon Jeong, P. Dutta, D. Sylvester, D. Blaauw
We present a 2×4×4mm3 imaging system complete with optics, wireless communication, battery, power management, solar harvesting, processor and memory. The system features a 160×160 resolution CMOS image sensor with 304nW continuous in-pixel motion detection mode. System components are fabricated in five different IC layers and die-stacked for minimal form factor. Photovoltaic (PV) cells face the opposite direction of the imager for optimal illumination and generate 456nW at 10klux to enable energy autonomous system operation.
{"title":"A millimeter-scale wireless imaging system with continuous motion detection and energy harvesting","authors":"Gyouho Kim, Yoonmyung Lee, Z. Foo, P. Pannuto, Ye-Sheng Kuo, B. Kempke, M. Ghaed, S. Bang, Inhee Lee, Yejoong Kim, Seokhyeon Jeong, P. Dutta, D. Sylvester, D. Blaauw","doi":"10.1109/VLSIC.2014.6858425","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858425","url":null,"abstract":"We present a 2×4×4mm3 imaging system complete with optics, wireless communication, battery, power management, solar harvesting, processor and memory. The system features a 160×160 resolution CMOS image sensor with 304nW continuous in-pixel motion detection mode. System components are fabricated in five different IC layers and die-stacked for minimal form factor. Photovoltaic (PV) cells face the opposite direction of the imager for optimal illumination and generate 456nW at 10klux to enable energy autonomous system operation.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131427562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858449
S. Iguchi, H. Fuketa, T. Sakurai, M. Takamiya
To reduce the start-up time of a crystal oscillator (XO), a chirp injection (CI) and a negative resistance booster (NRB) are proposed. By combining CI and NRB, the measured start-up time of a 39-MHz XO in 180-nm CMOS is reduced by 92% from 2.1ms to 158μs, which is the shortest time in the published XO's. The measured start-up time variations due to the ±20% supply voltage change or the temperature change are less than 13%.
{"title":"92% start-up time reduction by variation-tolerant chirp injection (CI) and negative resistance booster (NRB) in 39MHz crystal oscillator","authors":"S. Iguchi, H. Fuketa, T. Sakurai, M. Takamiya","doi":"10.1109/VLSIC.2014.6858449","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858449","url":null,"abstract":"To reduce the start-up time of a crystal oscillator (XO), a chirp injection (CI) and a negative resistance booster (NRB) are proposed. By combining CI and NRB, the measured start-up time of a 39-MHz XO in 180-nm CMOS is reduced by 92% from 2.1ms to 158μs, which is the shortest time in the published XO's. The measured start-up time variations due to the ±20% supply voltage change or the temperature change are less than 13%.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"184 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131467737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858384
Ronghua Ni, K. Mayaram, T. Fiez
A mixer-less low energy BFSK receiver for wireless sensor networks is presented. Q-enhanced frequency-to-amplitude conversion and linear amplification at RF frequencies provide a large conversion gain and high data rates, leading to improved sensitivity and energy efficiency. Fabricated in a 0.13 μm CMOS process, the 915 MHz receiver, with integrated digital calibration, demonstrates a sensitivity of -90 dBm at 500 kb/s and an energy efficiency of 80 pJ/b at 6 Mb/s.
{"title":"A 915MHz, 6Mb/s, 80pJ/b BFSK receiver with −76dBm sensitivity for high data rate wireless sensor networks","authors":"Ronghua Ni, K. Mayaram, T. Fiez","doi":"10.1109/VLSIC.2014.6858384","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858384","url":null,"abstract":"A mixer-less low energy BFSK receiver for wireless sensor networks is presented. Q-enhanced frequency-to-amplitude conversion and linear amplification at RF frequencies provide a large conversion gain and high data rates, leading to improved sensitivity and energy efficiency. Fabricated in a 0.13 μm CMOS process, the 915 MHz receiver, with integrated digital calibration, demonstrates a sensitivity of -90 dBm at 500 kb/s and an energy efficiency of 80 pJ/b at 6 Mb/s.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116180332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858369
A. R. Junaidi, Yasuhiro Take, T. Kuroda
The area efficiency of an inductive-coupling interface is improved by 12 times for WIO2 standard (352Gb/s) and beyond. By using a quadrature phase division multiplexing, coils are overlapped and the density is increased by 4 times. It is further increased by 3 times by shortening communication distance with an ultra-thin fan-out wafer level package. The proposed DRAM/SoC interface at 356Gb/s outperforms WIO2 with TSV in terms of area efficiency (4x better) and manufacturing cost (40% cheaper) and outperforms LPDDR4 in PoP in terms of power dissipation (5x lower) and timing control easiness.
{"title":"A 352Gb/s inductive-coupling DRAM/SoC interface using overlapping coils with phase division multiplexing and ultra-thin fan-out wafer level package","authors":"A. R. Junaidi, Yasuhiro Take, T. Kuroda","doi":"10.1109/VLSIC.2014.6858369","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858369","url":null,"abstract":"The area efficiency of an inductive-coupling interface is improved by 12 times for WIO2 standard (352Gb/s) and beyond. By using a quadrature phase division multiplexing, coils are overlapped and the density is increased by 4 times. It is further increased by 3 times by shortening communication distance with an ultra-thin fan-out wafer level package. The proposed DRAM/SoC interface at 356Gb/s outperforms WIO2 with TSV in terms of area efficiency (4x better) and manufacturing cost (40% cheaper) and outperforms LPDDR4 in PoP in terms of power dissipation (5x lower) and timing control easiness.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127111838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858413
Youn Sung Park, Yaoyu Tao, S. Sun, Zhengya Zhang
A 1.48mm2 1024-bit belief propagation polar decoder is designed in 65nm CMOS. A unidirectional processing reduces the memory size to 45Kb, and simplifies the processing element. A double-column 1024-parallel architecture enables a 4.68Gb/s throughput. A bit-splitting latch-based register file accommodates logic in memory for an 85% density. The architecture and circuit techniques reduce the power to 478mW for an efficiency of 15.5pJ/b/iteration at 1.0V. At 475mV, the efficiency is improved to 3.6pJ/b/iteration for a throughput of 780Mb/s.
{"title":"A 4.68Gb/s belief propagation polar decoder with bit-splitting register file","authors":"Youn Sung Park, Yaoyu Tao, S. Sun, Zhengya Zhang","doi":"10.1109/VLSIC.2014.6858413","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858413","url":null,"abstract":"A 1.48mm2 1024-bit belief propagation polar decoder is designed in 65nm CMOS. A unidirectional processing reduces the memory size to 45Kb, and simplifies the processing element. A double-column 1024-parallel architecture enables a 4.68Gb/s throughput. A bit-splitting latch-based register file accommodates logic in memory for an 85% density. The architecture and circuit techniques reduce the power to 478mW for an efficiency of 15.5pJ/b/iteration at 1.0V. At 475mV, the efficiency is improved to 3.6pJ/b/iteration for a throughput of 780Mb/s.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124014452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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