Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858396
S. Ho, Chilun Lo, Z. Ru, Jialin Zhao
A 23mW, 80MHz BW, 73dB dynamic range continuous-time ΔΣ modulator in 20nm CMOS is presented. The modulator operates from 1.0/1.2/1.5V supplies. Power is minimized by combining a low OSR, fast digital excess loop delay compensation scheme, and several techniques to minimize delay in the feedback path. The result is a highly power efficient modulator that achieves an FOM(DR) of 168dB.
{"title":"A 23mW, 73dB dynamic range, 80MHz BW continuous-time delta-sigma modulator in 20nm CMOS","authors":"S. Ho, Chilun Lo, Z. Ru, Jialin Zhao","doi":"10.1109/VLSIC.2014.6858396","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858396","url":null,"abstract":"A 23mW, 80MHz BW, 73dB dynamic range continuous-time ΔΣ modulator in 20nm CMOS is presented. The modulator operates from 1.0/1.2/1.5V supplies. Power is minimized by combining a low OSR, fast digital excess loop delay compensation scheme, and several techniques to minimize delay in the feedback path. The result is a highly power efficient modulator that achieves an FOM(DR) of 168dB.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126331197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858357
E. Doller, Ameen Akel, Jeffrey Wang, Ken Curewitz, S. Eilert
In the years between now and 2020, we should expect continued exponential data growth [15][16]. A number of ongoing advances in storage: the transition to solid-state drives (SSDs), the scaling of NAND flash capacity, and advanced silicon packaging techniques will dramatically increase the capacity of storage subsystems over the same timeframe. This will significantly reduce the ratio of storage bandwidth to storage density. Consequently, the majority of data in 2020 will either be cold or will require near-memory acceleration to pull rich information out of the sea of big data. We argue that, increasingly over time, value lies not merely in the size of the data, but rather in what one can do with it.
{"title":"DataCenter 2020: Near-memory acceleration for data-oriented applications","authors":"E. Doller, Ameen Akel, Jeffrey Wang, Ken Curewitz, S. Eilert","doi":"10.1109/VLSIC.2014.6858357","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858357","url":null,"abstract":"In the years between now and 2020, we should expect continued exponential data growth [15][16]. A number of ongoing advances in storage: the transition to solid-state drives (SSDs), the scaling of NAND flash capacity, and advanced silicon packaging techniques will dramatically increase the capacity of storage subsystems over the same timeframe. This will significantly reduce the ratio of storage bandwidth to storage density. Consequently, the majority of data in 2020 will either be cold or will require near-memory acceleration to pull rich information out of the sea of big data. We argue that, increasingly over time, value lies not merely in the size of the data, but rather in what one can do with it.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"318 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122220373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858407
Kiseok Song, U. Ha, Seongwook Park, H. Yoo
A multi-modal spectroscopy IC combining the impedance spectroscopy (IMPS) and the multi-wavelength near-infrared spectroscopy (mNIRS) is proposed for high precision non-invasive glucose level estimation. A frequency sweep (10kHz - 76kHz) sinusoidal oscillator (FSSO) is proposed for high resolution (500 steps) for IMPS. The output voltage swing of the FSSO is stabilized by an adaptive gain control (AGC). The measurement results of the IMPS and mNIRS are combined by an artificial neural network (ANN) in external smart device so that mean absolute relative difference (mARD) is enhanced to 8.3% from 15% of IMPS, 15% - 20% of mNIRS. A proposed 12.5mm2 0.18μm CMOS chip consumes peak power of 38mW at 1.5V.
{"title":"An impedance and multi-wavelength near-infrared spectroscopy IC for non-invasive blood glucose estimation","authors":"Kiseok Song, U. Ha, Seongwook Park, H. Yoo","doi":"10.1109/VLSIC.2014.6858407","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858407","url":null,"abstract":"A multi-modal spectroscopy IC combining the impedance spectroscopy (IMPS) and the multi-wavelength near-infrared spectroscopy (mNIRS) is proposed for high precision non-invasive glucose level estimation. A frequency sweep (10kHz - 76kHz) sinusoidal oscillator (FSSO) is proposed for high resolution (500 steps) for IMPS. The output voltage swing of the FSSO is stabilized by an adaptive gain control (AGC). The measurement results of the IMPS and mNIRS are combined by an artificial neural network (ANN) in external smart device so that mean absolute relative difference (mARD) is enhanced to 8.3% from 15% of IMPS, 15% - 20% of mNIRS. A proposed 12.5mm2 0.18μm CMOS chip consumes peak power of 38mW at 1.5V.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123879608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A first-reported 4K×2K@60fps digital TV SoC processor supporting 9 video formats and integrating HDMI/MHL receiver is fabricated in a 40nm CMOS process. It adopts error compensation processor (ECP) to improve the visual quality, and designs a memory management unit and resource sharing technique to improve the throughput and area efficiency by 38.5% and 34.3%, respectively. Moreover, a lossless compression processor (LCP) is newly designed to reduce 30% and 45% of external data accesses in playback and gaming scenario, respectively. The proposed TV SoC processor includes multi-standard 4K×2K@60fps playback and 3.4Gbps HDMI receiver (Rx), and both scenario dissipate 198.15mW at 1.2V core and 3.3V I/O.
{"title":"A 4K×2K@60fps multi-standard TV SoC processor with integrated HDMI/MHL receiver","authors":"Chi-Cheng Ju, Tsu-Ming Liu, Huaide Wang, Yung-Chang Chang, Chih-Ming Wang, Chang-Lin Hsieh, Brian Liu, Hue-Min Lin, Chia-Yun Cheng, Chun-Chia Chen, Min-Hao Chiu, Sheng-Jen Wang, P. Chao, Meng-Jye Hu, Ryan Yeh, Ted Chuang, Hsiu-Yi Lin, Chung-Hung Tsai","doi":"10.1109/VLSIC.2014.6858389","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858389","url":null,"abstract":"A first-reported 4K×2K@60fps digital TV SoC processor supporting 9 video formats and integrating HDMI/MHL receiver is fabricated in a 40nm CMOS process. It adopts error compensation processor (ECP) to improve the visual quality, and designs a memory management unit and resource sharing technique to improve the throughput and area efficiency by 38.5% and 34.3%, respectively. Moreover, a lossless compression processor (LCP) is newly designed to reduce 30% and 45% of external data accesses in playback and gaming scenario, respectively. The proposed TV SoC processor includes multi-standard 4K×2K@60fps playback and 3.4Gbps HDMI receiver (Rx), and both scenario dissipate 198.15mW at 1.2V core and 3.3V I/O.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124577189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858360
A. Garg, U. Singh, Nick Huang, Wayne Wong, B. Liu, Z. Huang, A. Momtaz, Jun Cao
A quad-channel, 112-128 Gb/s coherent DP-QPSK transmitter in 40 nm CMOS is presented. The 27.9-32.1 Gb/s TX features a half-rate architecture with a 2-tap FIR. The measured output has an amplitude of 1.2Vpp-diff with 1.3 ps deterministic jitter (DJ). The DP-QPSK TX's precoded data alignment is maintained through the quad-lane transmitter by the use of an automatic synchronous feedback loop, removing the need for a master global reset. The PLL outputs the full-rate and half-rate clock with ±0.5 UI skew adjustment relative to the data. The power consumption of the transmitter and PLL is 712 mW.
{"title":"A quad-channel 112–128 Gb/s coherent transmitter in 40 nm CMOS","authors":"A. Garg, U. Singh, Nick Huang, Wayne Wong, B. Liu, Z. Huang, A. Momtaz, Jun Cao","doi":"10.1109/VLSIC.2014.6858360","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858360","url":null,"abstract":"A quad-channel, 112-128 Gb/s coherent DP-QPSK transmitter in 40 nm CMOS is presented. The 27.9-32.1 Gb/s TX features a half-rate architecture with a 2-tap FIR. The measured output has an amplitude of 1.2Vpp-diff with 1.3 ps deterministic jitter (DJ). The DP-QPSK TX's precoded data alignment is maintained through the quad-lane transmitter by the use of an automatic synchronous feedback loop, removing the need for a master global reset. The PLL outputs the full-rate and half-rate clock with ±0.5 UI skew adjustment relative to the data. The power consumption of the transmitter and PLL is 712 mW.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"202 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134310650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858446
R. Nandwana, Tejasvi Anand, Saurabh Saxena, S. Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, A. Elshazly, P. Hanumolu
A calibration-free ring oscillator based fractional-N clock multiplier using hybrid phase/current-mode phase interpolator is presented. Fabricated in 65nm CMOS process, the prototype generates fractional frequencies from 4.25GHz-to-4.75GHz with in-band noise floor of -104dBc/Hz and 1.5ps integrated jitter. The clock multiplier achieves power efficiency of 2.4mW/GHz and FoM of -225.8dB.
{"title":"A 4.25GHz–4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement","authors":"R. Nandwana, Tejasvi Anand, Saurabh Saxena, S. Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, A. Elshazly, P. Hanumolu","doi":"10.1109/VLSIC.2014.6858446","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858446","url":null,"abstract":"A calibration-free ring oscillator based fractional-N clock multiplier using hybrid phase/current-mode phase interpolator is presented. Fabricated in 65nm CMOS process, the prototype generates fractional frequencies from 4.25GHz-to-4.75GHz with in-band noise floor of -104dBc/Hz and 1.5ps integrated jitter. The clock multiplier achieves power efficiency of 2.4mW/GHz and FoM of -225.8dB.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"224 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133460699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858406
S. Tanakamaru, Yuta Kitamura, Senju Yamazaki, Tsukasa Tokutomi, K. Takeuchi
Application-aware solid-state drives (SSDs) with 2 adaptive coding schemes to improve reliability are presented. In NAND flash memory, a direct reliability trade-off exists between write/erase (W/E) cycle and data-retention (DR) time. Thus, SSDs can be used for applications that have long DR time and low W/E cycles, or short DR time with high W/E cycles. The n-out-of-8 level cell (nLC) scheme is proposed for low-cost, long-term, archive storage which is indispensable to preserve human digital data. nLC eliminates the memory states of the Triple-Level Cell (TLC) NAND flash memory from 8 to 7...4 levels. Universal asymmetric coding (UAC) is also proposed for cloud/security camera/enterprise storage environments which require high endurance but shorter DR time. Both nLC and UAC optimize coding based on the applications' required W/E cycle and DR. Bit-error rates (BERs) are improved by 79% and 52% with nLC and UAC, respectively.
{"title":"Application-aware solid-state drives (SSDs) with adaptive coding","authors":"S. Tanakamaru, Yuta Kitamura, Senju Yamazaki, Tsukasa Tokutomi, K. Takeuchi","doi":"10.1109/VLSIC.2014.6858406","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858406","url":null,"abstract":"Application-aware solid-state drives (SSDs) with 2 adaptive coding schemes to improve reliability are presented. In NAND flash memory, a direct reliability trade-off exists between write/erase (W/E) cycle and data-retention (DR) time. Thus, SSDs can be used for applications that have long DR time and low W/E cycles, or short DR time with high W/E cycles. The n-out-of-8 level cell (nLC) scheme is proposed for low-cost, long-term, archive storage which is indispensable to preserve human digital data. nLC eliminates the memory states of the Triple-Level Cell (TLC) NAND flash memory from 8 to 7...4 levels. Universal asymmetric coding (UAC) is also proposed for cloud/security camera/enterprise storage environments which require high endurance but shorter DR time. Both nLC and UAC optimize coding based on the applications' required W/E cycle and DR. Bit-error rates (BERs) are improved by 79% and 52% with nLC and UAC, respectively.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133503660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858381
S. Ha, Chul Kim, Jongkil Park, Siddharth Joshi, G. Cauwenberghs
We present a power/data telemetry IC with a new data modulation scheme and simultaneous power transfer through a single inductive link. Data-driven synchronized single-cycle shorting of the secondary LC tank conserves reactive power while inducing an instantaneous voltage change at the primary side. Cyclic on-off keying time-encoded symbol mapping of the shorting cycle allows transmission of two data bits per four carrier cycles with simultaneous power transfer during non-shorting cycles. All timing control signals for rectification and data transmission are generated from a low-power clock recovery comparator and 22-phase 2× PLL. The 1-mm2 65-nm CMOS IC delivers up to 6.3-mW power and transmits 6.78-Mbps data with a BER of less than 5.9×10-7 over a single 1-cm 13.56-MHz inductive link.
我们提出了一种功率/数据遥测IC，具有新的数据调制方案，并通过单个感应链路同时传输功率。数据驱动的二次LC槽同步单周期短路在引起一次侧瞬时电压变化的同时节省了无功功率。短周期的循环开关键控时间编码符号映射允许每四个载波周期传输两个数据位，同时在非短周期期间传输功率。整流和数据传输的所有定时控制信号由低功耗时钟恢复比较器和22相2x锁相环产生。1 mm2 65nm CMOS IC提供高达6.3 mw的功率，传输6.78 mbps的数据，在单个1 cm 13.56 mhz电感链路上的误码小于5.9×10-7。
{"title":"Energy-recycling integrated 6.78-Mbps data 6.3-mW power telemetry over a single 13.56-MHz inductive link","authors":"S. Ha, Chul Kim, Jongkil Park, Siddharth Joshi, G. Cauwenberghs","doi":"10.1109/VLSIC.2014.6858381","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858381","url":null,"abstract":"We present a power/data telemetry IC with a new data modulation scheme and simultaneous power transfer through a single inductive link. Data-driven synchronized single-cycle shorting of the secondary LC tank conserves reactive power while inducing an instantaneous voltage change at the primary side. Cyclic on-off keying time-encoded symbol mapping of the shorting cycle allows transmission of two data bits per four carrier cycles with simultaneous power transfer during non-shorting cycles. All timing control signals for rectification and data transmission are generated from a low-power clock recovery comparator and 22-phase 2× PLL. The 1-mm2 65-nm CMOS IC delivers up to 6.3-mW power and transmits 6.78-Mbps data with a BER of less than 5.9×10-7 over a single 1-cm 13.56-MHz inductive link.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132783098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858384
Ronghua Ni, K. Mayaram, T. Fiez
A mixer-less low energy BFSK receiver for wireless sensor networks is presented. Q-enhanced frequency-to-amplitude conversion and linear amplification at RF frequencies provide a large conversion gain and high data rates, leading to improved sensitivity and energy efficiency. Fabricated in a 0.13 μm CMOS process, the 915 MHz receiver, with integrated digital calibration, demonstrates a sensitivity of -90 dBm at 500 kb/s and an energy efficiency of 80 pJ/b at 6 Mb/s.
{"title":"A 915MHz, 6Mb/s, 80pJ/b BFSK receiver with −76dBm sensitivity for high data rate wireless sensor networks","authors":"Ronghua Ni, K. Mayaram, T. Fiez","doi":"10.1109/VLSIC.2014.6858384","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858384","url":null,"abstract":"A mixer-less low energy BFSK receiver for wireless sensor networks is presented. Q-enhanced frequency-to-amplitude conversion and linear amplification at RF frequencies provide a large conversion gain and high data rates, leading to improved sensitivity and energy efficiency. Fabricated in a 0.13 μm CMOS process, the 915 MHz receiver, with integrated digital calibration, demonstrates a sensitivity of -90 dBm at 500 kb/s and an energy efficiency of 80 pJ/b at 6 Mb/s.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116180332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858413
Youn Sung Park, Yaoyu Tao, S. Sun, Zhengya Zhang
A 1.48mm2 1024-bit belief propagation polar decoder is designed in 65nm CMOS. A unidirectional processing reduces the memory size to 45Kb, and simplifies the processing element. A double-column 1024-parallel architecture enables a 4.68Gb/s throughput. A bit-splitting latch-based register file accommodates logic in memory for an 85% density. The architecture and circuit techniques reduce the power to 478mW for an efficiency of 15.5pJ/b/iteration at 1.0V. At 475mV, the efficiency is improved to 3.6pJ/b/iteration for a throughput of 780Mb/s.
{"title":"A 4.68Gb/s belief propagation polar decoder with bit-splitting register file","authors":"Youn Sung Park, Yaoyu Tao, S. Sun, Zhengya Zhang","doi":"10.1109/VLSIC.2014.6858413","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858413","url":null,"abstract":"A 1.48mm2 1024-bit belief propagation polar decoder is designed in 65nm CMOS. A unidirectional processing reduces the memory size to 45Kb, and simplifies the processing element. A double-column 1024-parallel architecture enables a 4.68Gb/s throughput. A bit-splitting latch-based register file accommodates logic in memory for an 85% density. The architecture and circuit techniques reduce the power to 478mW for an efficiency of 15.5pJ/b/iteration at 1.0V. At 475mV, the efficiency is improved to 3.6pJ/b/iteration for a throughput of 780Mb/s.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124014452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：