Pub Date : 2018-09-01DOI: 10.1109/autest.2018.8532553
R. Spinner, William Biagiotti, James McKenna, William Leippe
Traditional Test Program Sets (TPS) developed and deployed on legacy Automated Test Systems (ATS) predominately operate within a serial architecture, statically collecting and analyzing UUT data one unit at a time. High performance ATS station instrumentation supporting parallel testing has been commercially available for some time and is now capable of being fully exploited. A new generation of ATS has been developed that employs an integrated combination of COTS parallel simultaneous data stimulus and acquisition, software simulated UUT circuit behavior, and advanced automated waveform analysis to dynamically match mixed-signal UUT acquired data with a catalog of defined UUT parallel circuit signatures. The result is a methodology that enables TPS developers to create and deploy TPSs with higher test quality, greater cost efficiency and highly reduced execution times. This paper will explore how the combination of PXI-based stimulus and acquisition instruments, commercial circuit simulation software, dynamic waveform verification, and other innovations led to the design of the compact TPS workstation, “PADS” (Parallel Automated Development System) as innovated by Advanced Testing Technologies, Inc.
{"title":"Integrated Technologies Fulfill the Potential of Parallel Mixed Signal Testing","authors":"R. Spinner, William Biagiotti, James McKenna, William Leippe","doi":"10.1109/autest.2018.8532553","DOIUrl":"https://doi.org/10.1109/autest.2018.8532553","url":null,"abstract":"Traditional Test Program Sets (TPS) developed and deployed on legacy Automated Test Systems (ATS) predominately operate within a serial architecture, statically collecting and analyzing UUT data one unit at a time. High performance ATS station instrumentation supporting parallel testing has been commercially available for some time and is now capable of being fully exploited. A new generation of ATS has been developed that employs an integrated combination of COTS parallel simultaneous data stimulus and acquisition, software simulated UUT circuit behavior, and advanced automated waveform analysis to dynamically match mixed-signal UUT acquired data with a catalog of defined UUT parallel circuit signatures. The result is a methodology that enables TPS developers to create and deploy TPSs with higher test quality, greater cost efficiency and highly reduced execution times. This paper will explore how the combination of PXI-based stimulus and acquisition instruments, commercial circuit simulation software, dynamic waveform verification, and other innovations led to the design of the compact TPS workstation, “PADS” (Parallel Automated Development System) as innovated by Advanced Testing Technologies, Inc.","PeriodicalId":384058,"journal":{"name":"2018 IEEE AUTOTESTCON","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131882479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/AUTEST.2018.8532561
U. Jha
The modern millimeter wave (mmW) Radar exhibits distinct advantages over lower band (L, C, X, Ku, K, Ka) radars providing lower radar cross-section (greater stealthiness), multimode multi-target acquisition/tracking capabilities, long target-detection range, enhanced spatial resolution, agile maneuverability, superior survivability, all weather capabilities and greater reliability including reduced SWaPC metric. The mmW Radars are also at the forefront of the Advanced Driver Assistance Systems (ADAS), which are making their way into many of the high end automobiles at present. Adaptive cruise control, automatic braking, backup object detection, blind-spot detection, cross-traffic alerts, and lane-change assist take advantage of many mmW radar capabilities. The goal of ADAS is to reduce driver error and, therefore, decrease the number of crashes, injuries, and fatalities. In fact, these systems have been so effective that the government is contemplating ADAS for most of the future cars. The mmW Radar also lends handsomely towards the compact and low cost design of phased array antennas capable of beamforming and beam steering (dynamically pointing them in the desired direction). They enable beam steering without any moving part and an antenna beam is formed by an array of smaller antenna elements, such as individual patches or dipoles. By varying the relative phases and amplitudes of the signals applied to the individual receiver/exciter elements, the antenna array can shape and steer a beam in the desired direction. The compactness and low profile design of mmW phased array system presents daunting challenges to test and verification engineers since many of these intermediary points are neither accessible nor adequate to calibrate and/or characterize the system performance (e.g. uniformity, linearity, coverage, sensitivity etc…). To overcome these challenges, two approaches are employed to characterize such a compact and complex system – far-field and near-field mode, each with their own advantages and disadvantages. The far-field mode characterization can be done either outdoor or indoor but requires large anechoic chamber, sensitive and highly uniform and calibrated probe element as well specialized test equipment for injecting, collecting and analyzing the signals. The near-field mode testing has some unique advantages, where testing can be performed in a close range requiring far less complex anechoic chamber, simple test probe, easy test setup and majority of the characterization and error corrections can be done off-line utilizing sophisticated signal processing techniques. This paper analyzes the far-field and near-field testing methods of the mmW Radar systems and delineates the challenges and opportunities in enabling a low cost solution to the military and automotive world.
{"title":"The millimeter Wave (mmW) radar characterization, testing, verification challenges and opportunities","authors":"U. Jha","doi":"10.1109/AUTEST.2018.8532561","DOIUrl":"https://doi.org/10.1109/AUTEST.2018.8532561","url":null,"abstract":"The modern millimeter wave (mmW) Radar exhibits distinct advantages over lower band (L, C, X, Ku, K, Ka) radars providing lower radar cross-section (greater stealthiness), multimode multi-target acquisition/tracking capabilities, long target-detection range, enhanced spatial resolution, agile maneuverability, superior survivability, all weather capabilities and greater reliability including reduced SWaPC metric. The mmW Radars are also at the forefront of the Advanced Driver Assistance Systems (ADAS), which are making their way into many of the high end automobiles at present. Adaptive cruise control, automatic braking, backup object detection, blind-spot detection, cross-traffic alerts, and lane-change assist take advantage of many mmW radar capabilities. The goal of ADAS is to reduce driver error and, therefore, decrease the number of crashes, injuries, and fatalities. In fact, these systems have been so effective that the government is contemplating ADAS for most of the future cars. The mmW Radar also lends handsomely towards the compact and low cost design of phased array antennas capable of beamforming and beam steering (dynamically pointing them in the desired direction). They enable beam steering without any moving part and an antenna beam is formed by an array of smaller antenna elements, such as individual patches or dipoles. By varying the relative phases and amplitudes of the signals applied to the individual receiver/exciter elements, the antenna array can shape and steer a beam in the desired direction. The compactness and low profile design of mmW phased array system presents daunting challenges to test and verification engineers since many of these intermediary points are neither accessible nor adequate to calibrate and/or characterize the system performance (e.g. uniformity, linearity, coverage, sensitivity etc…). To overcome these challenges, two approaches are employed to characterize such a compact and complex system – far-field and near-field mode, each with their own advantages and disadvantages. The far-field mode characterization can be done either outdoor or indoor but requires large anechoic chamber, sensitive and highly uniform and calibrated probe element as well specialized test equipment for injecting, collecting and analyzing the signals. The near-field mode testing has some unique advantages, where testing can be performed in a close range requiring far less complex anechoic chamber, simple test probe, easy test setup and majority of the characterization and error corrections can be done off-line utilizing sophisticated signal processing techniques. This paper analyzes the far-field and near-field testing methods of the mmW Radar systems and delineates the challenges and opportunities in enabling a low cost solution to the military and automotive world.","PeriodicalId":384058,"journal":{"name":"2018 IEEE AUTOTESTCON","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134089996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/AUTEST.2018.8532564
Laura Catrine
Fibre Channel networks are used in a variety of modern avionics applications, mainly due to their high speed, low latency, and deterministic nature. Time synchronization of independent end-systems on a network is an important feature necessary for avionic systems that are real-time, safety critical, and fault tolerant. Fibre Channel can be configured as a deterministic network, by using an in-band synchronization protocol to synchronize the clocks of attached nodes thus allowing autonomous synchronized data transmissions. A synchronized message sent out periodically can be used to trigger the relative time start of each network time frame or window. Using this approach, the beginning time (TO) is determined each time the synchronization message is transmitted, as opposed to setting up a global clock between each of the nodes. This “time-triggered” synchronization must be accurately characterized to understand the deterministic timing of the network. This paper covers how the Fibre Channel “time-triggered” in-band synchronization operates and the testing used to characterize the deterministic Fibre Channel network timing.
{"title":"Fibre Channel Time Synchronization for Automated Testing","authors":"Laura Catrine","doi":"10.1109/AUTEST.2018.8532564","DOIUrl":"https://doi.org/10.1109/AUTEST.2018.8532564","url":null,"abstract":"Fibre Channel networks are used in a variety of modern avionics applications, mainly due to their high speed, low latency, and deterministic nature. Time synchronization of independent end-systems on a network is an important feature necessary for avionic systems that are real-time, safety critical, and fault tolerant. Fibre Channel can be configured as a deterministic network, by using an in-band synchronization protocol to synchronize the clocks of attached nodes thus allowing autonomous synchronized data transmissions. A synchronized message sent out periodically can be used to trigger the relative time start of each network time frame or window. Using this approach, the beginning time (TO) is determined each time the synchronization message is transmitted, as opposed to setting up a global clock between each of the nodes. This “time-triggered” synchronization must be accurately characterized to understand the deterministic timing of the network. This paper covers how the Fibre Channel “time-triggered” in-band synchronization operates and the testing used to characterize the deterministic Fibre Channel network timing.","PeriodicalId":384058,"journal":{"name":"2018 IEEE AUTOTESTCON","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116341287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/AUTEST.2018.8532513
Michael Fluet, P. Gilenberg
As the complexity and bandwidth requirements of modern avionics increase, new high speed digital buses are needed to support these requirements, and bring with them unique test challenges. Parallel bus interfaces often begin to exhibit problems with timing alignment and signal integrity when data rates approach several hundred Mbps. By converting single-ended parallel interfaces to differential signaling, their use can be extended to around 1 Gbps. As data rates rise beyond 1 Gbps, parallel buses become unusable due to skew issues and are replaced by multi-gigabit serial buses that alleviate the problems of parallel buses and can provide much higher data rates. As multi-gigabit serial buses become more prevalent in automated test, test engineers are finding that these buses come with their own set of test challenges. Multi-gigabit serial buses over copper media are difficult to interface and require special attention be paid to signal integrity and use of emphasis and equalization to produce a reliable test interface. Higher bandwidth test interfaces require generation, sourcing, processing, and storage of large amounts of test data. Some of the physical challenges of high speed serial buses over copper media can be resolved with optical interfaces. However, optical interfaces present yet again a new set of challenges. While traditional signal integrity is no longer a problem with optical interfaces, signal attenuation and optical link budgets must be understood. This paper discusses the progression from parallel data buses to electrical multi-gigabit serial buses to optical multi-gigabit serial buses, and beyond. Test challenges that must be addressed with each type of interface are discussed in detail. By understanding these test challenges, a test engineer can be prepared to reliably interface to and test modern avionics.
{"title":"Test Challenges of Multi-Gigabit Serial Buses","authors":"Michael Fluet, P. Gilenberg","doi":"10.1109/AUTEST.2018.8532513","DOIUrl":"https://doi.org/10.1109/AUTEST.2018.8532513","url":null,"abstract":"As the complexity and bandwidth requirements of modern avionics increase, new high speed digital buses are needed to support these requirements, and bring with them unique test challenges. Parallel bus interfaces often begin to exhibit problems with timing alignment and signal integrity when data rates approach several hundred Mbps. By converting single-ended parallel interfaces to differential signaling, their use can be extended to around 1 Gbps. As data rates rise beyond 1 Gbps, parallel buses become unusable due to skew issues and are replaced by multi-gigabit serial buses that alleviate the problems of parallel buses and can provide much higher data rates. As multi-gigabit serial buses become more prevalent in automated test, test engineers are finding that these buses come with their own set of test challenges. Multi-gigabit serial buses over copper media are difficult to interface and require special attention be paid to signal integrity and use of emphasis and equalization to produce a reliable test interface. Higher bandwidth test interfaces require generation, sourcing, processing, and storage of large amounts of test data. Some of the physical challenges of high speed serial buses over copper media can be resolved with optical interfaces. However, optical interfaces present yet again a new set of challenges. While traditional signal integrity is no longer a problem with optical interfaces, signal attenuation and optical link budgets must be understood. This paper discusses the progression from parallel data buses to electrical multi-gigabit serial buses to optical multi-gigabit serial buses, and beyond. Test challenges that must be addressed with each type of interface are discussed in detail. By understanding these test challenges, a test engineer can be prepared to reliably interface to and test modern avionics.","PeriodicalId":384058,"journal":{"name":"2018 IEEE AUTOTESTCON","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114750056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/AUTEST.2018.8532536
L. Gutterman
Smart weapon systems are now common place within the U.S. Armed Forces community and among U. S. allies. And to ensure mission success, maintainers need to confirm that all of these systems are mission ready or Full Mission Capable (FMC). Gone are the days of simply checking for the absence of stray voltage and the presence of firing signals by using an Armament Circuits Pre-Load Test Set (ACPTS), commonly referred to as a “beer can”. Today's sophisticated weapon systems need to support not only legacy test needs but also advanced systems by providing multiple measurement and stimulus channels as well as incorporating communication busses such as MMSI, MIL-STD-1760, Ethernet, CAN Bus, and more. The challenges faced by developers and customers alike lie with the difficulty to incorporate these capabilities into a handheld package to help minimize the “footprint of test”. There are some advanced solutions available today that can address not only the current generation of legacy and smart weapons but also have the flexibility to address future armament test needs on the flightline. Building on the current generation of “smart” beercans, the next generation solution for flightline test offers maintainers the ability to perform advanced test and diagnosis on the flightline - simplifying maintenance logistics while increasing performance and reducing test and maintenance time. This next generation “smart” beercan - the “SmartCan™”, offers advanced features and capabilities including: •Full analog test support for legacy systems including Audio and Video signal generation •Full MIL-STD-1760 support •Full support for additional interfaces including EBR1553, MMSI, Ethernet, CAN Bus, and more By offering these advanced features and improved legacy test capabilities, maintainers now have the ability to not only test but also emulate the weapons – facilitating a complete test of the weapon system's interface, from the cockpit's multi-function display (MFD) to the launch rails, without requiring any supplemental equipment. This paper provides an overview of flightline armament testers and presents key features of a next generation flightline tester that is capable of supporting multiple aircraft platforms and weapon systems as well as being upgradeable for future test needs.
{"title":"Next Generation Armament Test Solutions for the Flightline","authors":"L. Gutterman","doi":"10.1109/AUTEST.2018.8532536","DOIUrl":"https://doi.org/10.1109/AUTEST.2018.8532536","url":null,"abstract":"Smart weapon systems are now common place within the U.S. Armed Forces community and among U. S. allies. And to ensure mission success, maintainers need to confirm that all of these systems are mission ready or Full Mission Capable (FMC). Gone are the days of simply checking for the absence of stray voltage and the presence of firing signals by using an Armament Circuits Pre-Load Test Set (ACPTS), commonly referred to as a “beer can”. Today's sophisticated weapon systems need to support not only legacy test needs but also advanced systems by providing multiple measurement and stimulus channels as well as incorporating communication busses such as MMSI, MIL-STD-1760, Ethernet, CAN Bus, and more. The challenges faced by developers and customers alike lie with the difficulty to incorporate these capabilities into a handheld package to help minimize the “footprint of test”. There are some advanced solutions available today that can address not only the current generation of legacy and smart weapons but also have the flexibility to address future armament test needs on the flightline. Building on the current generation of “smart” beercans, the next generation solution for flightline test offers maintainers the ability to perform advanced test and diagnosis on the flightline - simplifying maintenance logistics while increasing performance and reducing test and maintenance time. This next generation “smart” beercan - the “SmartCan™”, offers advanced features and capabilities including: •Full analog test support for legacy systems including Audio and Video signal generation •Full MIL-STD-1760 support •Full support for additional interfaces including EBR1553, MMSI, Ethernet, CAN Bus, and more By offering these advanced features and improved legacy test capabilities, maintainers now have the ability to not only test but also emulate the weapons – facilitating a complete test of the weapon system's interface, from the cockpit's multi-function display (MFD) to the launch rails, without requiring any supplemental equipment. This paper provides an overview of flightline armament testers and presents key features of a next generation flightline tester that is capable of supporting multiple aircraft platforms and weapon systems as well as being upgradeable for future test needs.","PeriodicalId":384058,"journal":{"name":"2018 IEEE AUTOTESTCON","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128089892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/AUTEST.2018.8532516
W. J. Headrick, Anne Dlugosz, Paul J. Rajcok
For modern Automatic Test Equipment (ATE) one of the most daunting tasks is now Information Assurance (IA). What was once at most a secondary item consisting mainly of installing an Anti-Virus suite is now becoming one of the most important aspects of ATE. Given the current climate of IA it has become important to ensure ATE is kept safe from any breaches of security or loss of information. Even though most ATE are not on the Internet (or even on a network for many) they are still vulnerable to some of the same attack vectors plaguing common computers and other electronic devices. This paper will discuss some of the processes and procedures which must be used to ensure that modern ATE can continue to be used to test and detect faults in the systems they are designed to test. The common items that must be considered for ATE are as follows: The ATE system must have some form of Anti-Virus (as should all computers). The ATE system should have a minimum software footprint only providing the software needed to perform the task. The ATE system should be verified to have all the Operating System (OS) settings configured pursuant to the task it is intended to perform. The ATE OS settings should include password and password expiration settings to prevent access by anyone not expected to be on the system. The ATE system software should be written and constructed such that it in itself is not readily open to attack. The ATE system should be designed in a manner such that none of the instruments in the system can easily be attacked. The ATE system should insure any paths to the outside world (such as Ethernet or USB devices) are limited to only those required to perform the task it was designed for. These and many other common configuration concerns will be discussed in the paper.
{"title":"Information Assurance in modern ATE","authors":"W. J. Headrick, Anne Dlugosz, Paul J. Rajcok","doi":"10.1109/AUTEST.2018.8532516","DOIUrl":"https://doi.org/10.1109/AUTEST.2018.8532516","url":null,"abstract":"For modern Automatic Test Equipment (ATE) one of the most daunting tasks is now Information Assurance (IA). What was once at most a secondary item consisting mainly of installing an Anti-Virus suite is now becoming one of the most important aspects of ATE. Given the current climate of IA it has become important to ensure ATE is kept safe from any breaches of security or loss of information. Even though most ATE are not on the Internet (or even on a network for many) they are still vulnerable to some of the same attack vectors plaguing common computers and other electronic devices. This paper will discuss some of the processes and procedures which must be used to ensure that modern ATE can continue to be used to test and detect faults in the systems they are designed to test. The common items that must be considered for ATE are as follows: The ATE system must have some form of Anti-Virus (as should all computers). The ATE system should have a minimum software footprint only providing the software needed to perform the task. The ATE system should be verified to have all the Operating System (OS) settings configured pursuant to the task it is intended to perform. The ATE OS settings should include password and password expiration settings to prevent access by anyone not expected to be on the system. The ATE system software should be written and constructed such that it in itself is not readily open to attack. The ATE system should be designed in a manner such that none of the instruments in the system can easily be attacked. The ATE system should insure any paths to the outside world (such as Ethernet or USB devices) are limited to only those required to perform the task it was designed for. These and many other common configuration concerns will be discussed in the paper.","PeriodicalId":384058,"journal":{"name":"2018 IEEE AUTOTESTCON","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133483246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/AUTEST.2018.8532547
S. Odintsov
Every mission-critical system goes through extensive functionality and stress tests after being manufactured. But these tests alone do not guarantee correct system behavior in the field. A contemporary high-performance system board is a complex 3D object that may contain a few dozens of hidden layers, stacked micro-vias, high density interconnect, with all above not contributing to ease of test and reliability. Today, data transmission rates on the board may be reaching multi-gigabit ranges on a single channel. Even small changes in high-speed transmission line's impedance caused by system degradation may result in system performance issues and increased error rates due to small delays, intermittent faults and other sporadic stability issues observed in certain operation modes, at certain workloads or manifesting in a seemingly stochastic manner. Diagnosing the root cause of such faulty behavior (defects) in the field is extremely difficult. Differently from Intermittent Faults, Marginal Defects are permanent imperfections, which do not have a temporary or periodic effect. In a way, they are similar to parametric variations, pushing the system (or more specifically, the assembled board) very close or slightly beyond its specified operating margins. As a remedy, high-speed signals are normally fine-tuned or even calibrated to deliver pitch perfect timing even in case of now-ubiquitous DDR3 memories. As a negative side, the calibration mechanism may mask Marginal Defects out until the operating window shrinks to unbearable size and system starts to fail. Self-test and various built-in monitors are often used to monitor system health status, predict and prepare for possible failures. In this paper, we will present methodology aimed at overcoming described above challenges and successfully monitor high-speed data transmission interface health. The methodology is based on observation of signal sampling delays deviation and method described in the previous paper [1].
{"title":"In-Field Detection of Degradation on PCB Assembly High-Speed Buses","authors":"S. Odintsov","doi":"10.1109/AUTEST.2018.8532547","DOIUrl":"https://doi.org/10.1109/AUTEST.2018.8532547","url":null,"abstract":"Every mission-critical system goes through extensive functionality and stress tests after being manufactured. But these tests alone do not guarantee correct system behavior in the field. A contemporary high-performance system board is a complex 3D object that may contain a few dozens of hidden layers, stacked micro-vias, high density interconnect, with all above not contributing to ease of test and reliability. Today, data transmission rates on the board may be reaching multi-gigabit ranges on a single channel. Even small changes in high-speed transmission line's impedance caused by system degradation may result in system performance issues and increased error rates due to small delays, intermittent faults and other sporadic stability issues observed in certain operation modes, at certain workloads or manifesting in a seemingly stochastic manner. Diagnosing the root cause of such faulty behavior (defects) in the field is extremely difficult. Differently from Intermittent Faults, Marginal Defects are permanent imperfections, which do not have a temporary or periodic effect. In a way, they are similar to parametric variations, pushing the system (or more specifically, the assembled board) very close or slightly beyond its specified operating margins. As a remedy, high-speed signals are normally fine-tuned or even calibrated to deliver pitch perfect timing even in case of now-ubiquitous DDR3 memories. As a negative side, the calibration mechanism may mask Marginal Defects out until the operating window shrinks to unbearable size and system starts to fail. Self-test and various built-in monitors are often used to monitor system health status, predict and prepare for possible failures. In this paper, we will present methodology aimed at overcoming described above challenges and successfully monitor high-speed data transmission interface health. The methodology is based on observation of signal sampling delays deviation and method described in the previous paper [1].","PeriodicalId":384058,"journal":{"name":"2018 IEEE AUTOTESTCON","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127026303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/AUTEST.2018.8532517
Yang Yu, Yueming Jiang, Junyan Liu, Zhiming Yang, Xiyuan Peng
With the increasing demand of high reliability and safety of modern electric devices, failure prediction becomes more and more important since it is efficient to increase reliability and reduce downtime cost. A novel prediction method for analog circuits is proposed in this paper. Firstly, output waveforms in time domain of the initial state and the degradation states are extracted, then particle filter algorithm is implemented to estimate the changes of the waveforms according to the principles of noise estimation based on Grey Theory to obtain more reasonable fault indicators from more complete information. Thereafter, a novel degradation prediction model for analog circuits is constructed according to the newly obtained fault indicators. To validate the proposed degradation prediction method, the experiments are implemented on high-voltage power circuit board. The experimental results show that the method can predict the degradation trend and the information will be useful for the reliability design of the analog circuits.
{"title":"A Novel Degradation Prediction for Analog Circuits using Particle Filter","authors":"Yang Yu, Yueming Jiang, Junyan Liu, Zhiming Yang, Xiyuan Peng","doi":"10.1109/AUTEST.2018.8532517","DOIUrl":"https://doi.org/10.1109/AUTEST.2018.8532517","url":null,"abstract":"With the increasing demand of high reliability and safety of modern electric devices, failure prediction becomes more and more important since it is efficient to increase reliability and reduce downtime cost. A novel prediction method for analog circuits is proposed in this paper. Firstly, output waveforms in time domain of the initial state and the degradation states are extracted, then particle filter algorithm is implemented to estimate the changes of the waveforms according to the principles of noise estimation based on Grey Theory to obtain more reasonable fault indicators from more complete information. Thereafter, a novel degradation prediction model for analog circuits is constructed according to the newly obtained fault indicators. To validate the proposed degradation prediction method, the experiments are implemented on high-voltage power circuit board. The experimental results show that the method can predict the degradation trend and the information will be useful for the reliability design of the analog circuits.","PeriodicalId":384058,"journal":{"name":"2018 IEEE AUTOTESTCON","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116189272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/autest.2018.8532560
E. Cabanillas, M. Kafal, Wafa Ben-Hassen
In this paper, the first electronic device capable of performing simultaneous Orthogonal Multi-Tone Time Domain Reflectometry (OMTDR) measurements with data fusion is presented. This is possible by executing reliable communication among several OMTDR-based systems. In fact, the main challenge of any developed system is to achieve a zero bit error rate communication with a typical reflectometry hardware without considering complex clock recovery systems and synchronization blocks. To achieve that, the proposed system must to be able to find the minimum interference sampling time in a short delay in order to avoid synchronous issues. This is achieved by performing a novel fast time distributed oversampling technique. Such technique consists of sampling the Analog-to-Digital Converter (ADC) and the Digital-to-Analog Converter (DAC) with a frequency offset, achieving $Omega$ order oversampling in $Omega+1$ OMTDR signal cycles. The developed demonstrator is capable of ensuring cable diagnosis and reliable communication between several devices connected with aeronautical cables.
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