Pub Date : 2016-03-04DOI: 10.1109/ICEDSS.2016.7587785
Deepa C. Nambiar, C. Jose
This paper investigates a novel method to compensate the reactive power losses incurred in a wind energy conversion system equipped with maximum power point tracking. A variable speed generator is used here, which is a permanent magnet generator. In order to enable protection from mechanical damages of Wind Energy Conversion System, pitch angle control is employed which is an advanced pitch angle control strategy based on fuzzy logic. Also, the switching of inverter is done using Space Vector Pulse Width Modulation logic. Gate pulses for inverter are generated using SVPWM block. The simulation of the integration of a system to the grid with maximum power point tracking, fuzzy logic based pitch angle control and SVPWM based inverter switching is performed using MATLAB/SIMULINK software and the simulation results are also presented.
{"title":"A novel fuzzy based pitch angle control scheme and SVPWM based active and reactive power flow control of a permanent magnet generator based grid tied Wind Energy Conversion System","authors":"Deepa C. Nambiar, C. Jose","doi":"10.1109/ICEDSS.2016.7587785","DOIUrl":"https://doi.org/10.1109/ICEDSS.2016.7587785","url":null,"abstract":"This paper investigates a novel method to compensate the reactive power losses incurred in a wind energy conversion system equipped with maximum power point tracking. A variable speed generator is used here, which is a permanent magnet generator. In order to enable protection from mechanical damages of Wind Energy Conversion System, pitch angle control is employed which is an advanced pitch angle control strategy based on fuzzy logic. Also, the switching of inverter is done using Space Vector Pulse Width Modulation logic. Gate pulses for inverter are generated using SVPWM block. The simulation of the integration of a system to the grid with maximum power point tracking, fuzzy logic based pitch angle control and SVPWM based inverter switching is performed using MATLAB/SIMULINK software and the simulation results are also presented.","PeriodicalId":399107,"journal":{"name":"2016 Conference on Emerging Devices and Smart Systems (ICEDSS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130589119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-04DOI: 10.1109/ICEDSS.2016.7587776
Ruchi, S. Dasgupta
Technology advancement demands more functionality per device with reducing device dimensions as a result of technology scaling. SRAM represents the technology workhorse due to its compatibility with the logic. The denser SRAM is the requirement for modern high performance. The stability of SRAM in low power regime needs attention due to increasing effects of process variations. These variations are dominant for the scaled devices. Therefore, the reliability of the overall SoC is mostly affected by the reliability of the SRAM. In this paper, the challenges to low-power SRAM design, based on the scaling, power dissipation, and process variations are discussed. The result of the discussion is that the challenges for SRAM designing increase with technology scaling.
{"title":"Challenges of low power SRAM design in Nanoscale Era","authors":"Ruchi, S. Dasgupta","doi":"10.1109/ICEDSS.2016.7587776","DOIUrl":"https://doi.org/10.1109/ICEDSS.2016.7587776","url":null,"abstract":"Technology advancement demands more functionality per device with reducing device dimensions as a result of technology scaling. SRAM represents the technology workhorse due to its compatibility with the logic. The denser SRAM is the requirement for modern high performance. The stability of SRAM in low power regime needs attention due to increasing effects of process variations. These variations are dominant for the scaled devices. Therefore, the reliability of the overall SoC is mostly affected by the reliability of the SRAM. In this paper, the challenges to low-power SRAM design, based on the scaling, power dissipation, and process variations are discussed. The result of the discussion is that the challenges for SRAM designing increase with technology scaling.","PeriodicalId":399107,"journal":{"name":"2016 Conference on Emerging Devices and Smart Systems (ICEDSS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132262466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-04DOI: 10.1109/ICEDSS.2016.7587795
E. Chaithanya, P. Jyothsna
The demand of plug in hybrid electric vehicle is increasing day by day. This paper introduces a charging station architecture by using a combination of PV-Wind hybrid system and smart charging strategies for plug-in hybrid electric vehicles (PHEVs). With the increasing in the number of PHEVs, the demand on the electric grid increases appreciably. The proliferation in the number of PHEVs will trigger extreme surges in demand while charging them during peak hours. To avoid this problem, a sma r t charging station architecture is proposed in which the rate of charging the PHEVs, is controlled in such a way that the effect of charging during peak load period is not felt on the grid. The power required to charge the plug in hybrids comes from PV-Wind hybrid system or the utility or both. The three way interaction between the PHEVs, hybrid source and the grid ensures optimal usage of available power, charging time and grid stability. The system consists of a PV-Wind hybrid system, DC/DC boost converter, DC/DC buck converter and DC/AC bi-directional converter. The output of DC/DC boost converter and input of DC/AC bi-directional converter share a common DC link. The control strategy is based on DC link voltage sensing is proposed for the above system for efficient and reliable energy transfer. Simulation studies are performed along with the theoretical analysis to validate the proposed method.
{"title":"Smart charging of PV-Wind hybrid integrated PHEVs based on DC link voltage sensing","authors":"E. Chaithanya, P. Jyothsna","doi":"10.1109/ICEDSS.2016.7587795","DOIUrl":"https://doi.org/10.1109/ICEDSS.2016.7587795","url":null,"abstract":"The demand of plug in hybrid electric vehicle is increasing day by day. This paper introduces a charging station architecture by using a combination of PV-Wind hybrid system and smart charging strategies for plug-in hybrid electric vehicles (PHEVs). With the increasing in the number of PHEVs, the demand on the electric grid increases appreciably. The proliferation in the number of PHEVs will trigger extreme surges in demand while charging them during peak hours. To avoid this problem, a sma r t charging station architecture is proposed in which the rate of charging the PHEVs, is controlled in such a way that the effect of charging during peak load period is not felt on the grid. The power required to charge the plug in hybrids comes from PV-Wind hybrid system or the utility or both. The three way interaction between the PHEVs, hybrid source and the grid ensures optimal usage of available power, charging time and grid stability. The system consists of a PV-Wind hybrid system, DC/DC boost converter, DC/DC buck converter and DC/AC bi-directional converter. The output of DC/DC boost converter and input of DC/AC bi-directional converter share a common DC link. The control strategy is based on DC link voltage sensing is proposed for the above system for efficient and reliable energy transfer. Simulation studies are performed along with the theoretical analysis to validate the proposed method.","PeriodicalId":399107,"journal":{"name":"2016 Conference on Emerging Devices and Smart Systems (ICEDSS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134408812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-04DOI: 10.1109/ICEDSS.2016.7587792
A. Hari, Prabin James
Solar energy maintains life on the earth, and it is an infinite source of clean energy. Modeling and simulation of renewable sources have enhanced the optimal integration of PV Systems into smart grids. The main notion of the new converter presented is to use a single-stage three phase grid-tie solar PV converter to perform dc/ac and dc/dc operations. The System incorporates fuzzy logic controller for optimized performance. This converter solution is urging for PV-battery application, reducing the number of conversion stages, thus superior to the conventional system regarding efficiency cost, weight, and volume. The model is efficient in computational complexity, and it is easy to configure for representing wide-range Of PV installations. The overall system is designed, developed and validated by using MATLAB/SIMULINK.
{"title":"Single stage solar power conversion with multimode operation","authors":"A. Hari, Prabin James","doi":"10.1109/ICEDSS.2016.7587792","DOIUrl":"https://doi.org/10.1109/ICEDSS.2016.7587792","url":null,"abstract":"Solar energy maintains life on the earth, and it is an infinite source of clean energy. Modeling and simulation of renewable sources have enhanced the optimal integration of PV Systems into smart grids. The main notion of the new converter presented is to use a single-stage three phase grid-tie solar PV converter to perform dc/ac and dc/dc operations. The System incorporates fuzzy logic controller for optimized performance. This converter solution is urging for PV-battery application, reducing the number of conversion stages, thus superior to the conventional system regarding efficiency cost, weight, and volume. The model is efficient in computational complexity, and it is easy to configure for representing wide-range Of PV installations. The overall system is designed, developed and validated by using MATLAB/SIMULINK.","PeriodicalId":399107,"journal":{"name":"2016 Conference on Emerging Devices and Smart Systems (ICEDSS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126009049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-04DOI: 10.1109/ICEDSS.2016.7587689
T. Kalita, B. Das
Analog to Digital Converter (ADC) is an essential part of a mixed signal circuit design, which acts as a bridge between naturally occurring analog signals and digital signals. It has been a continuous effort of the researchers to reduce or keep the noise constant along with the level of advancement made in the field of mixed signal circuit design to increase the speed. This work has been intended towards modification of Quantum Voltage Comparator (QVC) in a 4 bit flash ADC design which results in the reduction of linearity along with noise. The 2×1 multiplexer based decoder in ADC increases the speed of the circuit. QVC is a cascading of two differential comparators as a single comparator with systematically varying sizes of NMOS pair, which eliminates the resistor ladder circuit in a conventional flash ADC. In this work, the modified QVC based flash ADC works on a single input voltage. It has been simulated in GPDK 180 nm CADENCE VIRTUOSO platform with a supply voltage of 1.8 V. This proposed flash ADC design results in a significant drop in noise, yielding an SNR value of 25.4 dB with a sampling rate of 5.12 GS/s with a power consumption of 4.19 mW.
模数转换器(Analog to Digital Converter, ADC)是混合信号电路设计的重要组成部分，它是自然产生的模拟信号和数字信号之间的桥梁。随着混合信号电路设计水平的不断提高，降低或保持噪声恒定一直是研究人员不断努力的方向。这项工作旨在修改4位闪存ADC设计中的量子电压比较器(QVC)，从而降低线性度和噪声。ADC中基于2×1多路复用器的解码器提高了电路的速度。QVC是将两个差分比较器级联成一个比较器，系统地改变NMOS对的大小，消除了传统闪存ADC中的电阻阶梯电路。在这项工作中，改进的基于QVC的闪存ADC工作在单输入电压下。在GPDK 180 nm CADENCE VIRTUOSO平台上进行了仿真，电源电压为1.8 V。提出的闪存ADC设计显著降低了噪声，产生了25.4 dB的信噪比，采样率为5.12 GS/s，功耗为4.19 mW。
{"title":"A 4 bit Quantum Voltage Comparator based flash ADC for low noise applications","authors":"T. Kalita, B. Das","doi":"10.1109/ICEDSS.2016.7587689","DOIUrl":"https://doi.org/10.1109/ICEDSS.2016.7587689","url":null,"abstract":"Analog to Digital Converter (ADC) is an essential part of a mixed signal circuit design, which acts as a bridge between naturally occurring analog signals and digital signals. It has been a continuous effort of the researchers to reduce or keep the noise constant along with the level of advancement made in the field of mixed signal circuit design to increase the speed. This work has been intended towards modification of Quantum Voltage Comparator (QVC) in a 4 bit flash ADC design which results in the reduction of linearity along with noise. The 2×1 multiplexer based decoder in ADC increases the speed of the circuit. QVC is a cascading of two differential comparators as a single comparator with systematically varying sizes of NMOS pair, which eliminates the resistor ladder circuit in a conventional flash ADC. In this work, the modified QVC based flash ADC works on a single input voltage. It has been simulated in GPDK 180 nm CADENCE VIRTUOSO platform with a supply voltage of 1.8 V. This proposed flash ADC design results in a significant drop in noise, yielding an SNR value of 25.4 dB with a sampling rate of 5.12 GS/s with a power consumption of 4.19 mW.","PeriodicalId":399107,"journal":{"name":"2016 Conference on Emerging Devices and Smart Systems (ICEDSS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117126358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-04DOI: 10.1109/ICEDSS.2016.7587782
Randeep Kaur, Sandeep Kaur
The main goal of this paper is to process a medical image. For a medical diagnosis, the result is more suitable. Contrast enhancement is used to improve the contrast of an image. Contrast enhancement of images is used for a different variety of applications such as in the medical field. Most of the images like medical images, remote sensing, aerial images and real life photographs suffer from poor contrast. The main goal of image enhancement is to improve the quality or clarity of images or to increase the interpretability in images for human viewing. In medical images detection and analysis, contrast enhancement techniques are one of the most significant stages. We are used contrast enhancement techniques to achieve contrast enhancement of images. The type of techniques includes neighborhood operation, average filter, bilateral ratinex, imadjust and sigmoid function. All these techniques are comparing with each other to achieve which enhancement techniques have produced a better contrast of an image. The four separate parameters are used. These parameters are such as peak signal to noise ratio (PSNR), mean square error (MSE), normalization coefficient (NC) and root mean square error (RMSE). In image research, this is one of the most important and difficult technique.
{"title":"Comparison of contrast enhancement techniques for medical image","authors":"Randeep Kaur, Sandeep Kaur","doi":"10.1109/ICEDSS.2016.7587782","DOIUrl":"https://doi.org/10.1109/ICEDSS.2016.7587782","url":null,"abstract":"The main goal of this paper is to process a medical image. For a medical diagnosis, the result is more suitable. Contrast enhancement is used to improve the contrast of an image. Contrast enhancement of images is used for a different variety of applications such as in the medical field. Most of the images like medical images, remote sensing, aerial images and real life photographs suffer from poor contrast. The main goal of image enhancement is to improve the quality or clarity of images or to increase the interpretability in images for human viewing. In medical images detection and analysis, contrast enhancement techniques are one of the most significant stages. We are used contrast enhancement techniques to achieve contrast enhancement of images. The type of techniques includes neighborhood operation, average filter, bilateral ratinex, imadjust and sigmoid function. All these techniques are comparing with each other to achieve which enhancement techniques have produced a better contrast of an image. The four separate parameters are used. These parameters are such as peak signal to noise ratio (PSNR), mean square error (MSE), normalization coefficient (NC) and root mean square error (RMSE). In image research, this is one of the most important and difficult technique.","PeriodicalId":399107,"journal":{"name":"2016 Conference on Emerging Devices and Smart Systems (ICEDSS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124923591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-04DOI: 10.1109/ICEDSS.2016.7587789
R. Ramesh, K. Kannan, M. Madheswaran
The development in the field of sensors in general and biosensors in particular has motivated the research in the recent past. The design and fabrication of devices for health care monitoring has drawn attention in the twenty first century. The simulation of the high-k dielectric (HfO2) FinFET biosensor with nano dimension has been carried out and presented in the present paper. Based on the existing literature it has been found that in order to facilitate an easier match with the biological stimulus the HfO2 dielectric FinFET can be preferred. Keeping this in view, the three dimensional numerical simulation of the HfO2 FinFET has been done to study the potential use as sensor for health care applications. The device equations are numerically solved including quantum mechanical effects to estimate the performance of the device for biological applications. The results show that the device characteristics are strongly influenced by the light even if the intensity is very less. The integrated circuit compatibility of the HfO2 FinFET device also enhances the potential use for future biological systems.
{"title":"Numerical modeling of high sensitivity nanoscale FinFET biosensor for health care applications","authors":"R. Ramesh, K. Kannan, M. Madheswaran","doi":"10.1109/ICEDSS.2016.7587789","DOIUrl":"https://doi.org/10.1109/ICEDSS.2016.7587789","url":null,"abstract":"The development in the field of sensors in general and biosensors in particular has motivated the research in the recent past. The design and fabrication of devices for health care monitoring has drawn attention in the twenty first century. The simulation of the high-k dielectric (HfO2) FinFET biosensor with nano dimension has been carried out and presented in the present paper. Based on the existing literature it has been found that in order to facilitate an easier match with the biological stimulus the HfO2 dielectric FinFET can be preferred. Keeping this in view, the three dimensional numerical simulation of the HfO2 FinFET has been done to study the potential use as sensor for health care applications. The device equations are numerically solved including quantum mechanical effects to estimate the performance of the device for biological applications. The results show that the device characteristics are strongly influenced by the light even if the intensity is very less. The integrated circuit compatibility of the HfO2 FinFET device also enhances the potential use for future biological systems.","PeriodicalId":399107,"journal":{"name":"2016 Conference on Emerging Devices and Smart Systems (ICEDSS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131201387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-04DOI: 10.1109/ICEDSS.2016.7587779
Aditi Y. Patil, J. J. Alexander, Shital Satpute, J. Katti, T. Sali
Compared to traditional methods, Visual Secret Sharing methods for encryption help in achieving high levels of confidentiality and reliability. Secret sharing schemes are ideal for storing information that is highly sensitive and important. In this paper we introduce a novel method of creating shares of a grayscale image by first dividing the image into corresponding bitmaps. Creating bit-plane slices or bitmaps of a grayscale image provides an additional level of security to it. According to this approach, first the grayscale image is divided into 8 bitmaps and then 2 shares of every bitmap are produced; all the first shares are combined to generate final share 1 and all the second shares of every bitmap are combined to generate final share 2. For the reconstruction of original image final share 1 and final share 2 are combined.
{"title":"Security of grayscale images by VSS with novel method of bit-plane slicing","authors":"Aditi Y. Patil, J. J. Alexander, Shital Satpute, J. Katti, T. Sali","doi":"10.1109/ICEDSS.2016.7587779","DOIUrl":"https://doi.org/10.1109/ICEDSS.2016.7587779","url":null,"abstract":"Compared to traditional methods, Visual Secret Sharing methods for encryption help in achieving high levels of confidentiality and reliability. Secret sharing schemes are ideal for storing information that is highly sensitive and important. In this paper we introduce a novel method of creating shares of a grayscale image by first dividing the image into corresponding bitmaps. Creating bit-plane slices or bitmaps of a grayscale image provides an additional level of security to it. According to this approach, first the grayscale image is divided into 8 bitmaps and then 2 shares of every bitmap are produced; all the first shares are combined to generate final share 1 and all the second shares of every bitmap are combined to generate final share 2. For the reconstruction of original image final share 1 and final share 2 are combined.","PeriodicalId":399107,"journal":{"name":"2016 Conference on Emerging Devices and Smart Systems (ICEDSS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133772882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-04DOI: 10.1109/ICEDSS.2016.7587786
V. Vijikala, D. Dhas
Mammogram plays a vital role in clinical imaging. It is necessary to provide a clear image to the surgeon for diagnosing the disorder and diseases of soft and complex tissue structure. Images obtained from the mammogram may have noises added to it during capturing of the image. Removing noise is still a challenging problem. Many filters are innovated to remove noise from the image with its postulation, advantage, and limitations. In this paper, Hybrid Median Filter (HMF), Linear Minimum Mean-Square-Error (LMMSE), Oriented Rician Noise Reduction Anisotropic Diffusion (ORNRAD), Higher Order Hybrid Median (HOHM), and Non-Level Means (NLM) denoising filters are used to remove noise from a mammogram image. The performance analyses of filters were evaluated by Mean Square Error (MSE), Peak Signal to Noise Ratio (PSNR), Image Quality Index (IQI), Mean Absolute Error (MAE), and Contrast to Noise Ratio (CNR) parameters. ORNRAD filter gives desirable results regarding above five quality and performance analysis attributes.
{"title":"Identification of most preferential denoising method for mammogram images","authors":"V. Vijikala, D. Dhas","doi":"10.1109/ICEDSS.2016.7587786","DOIUrl":"https://doi.org/10.1109/ICEDSS.2016.7587786","url":null,"abstract":"Mammogram plays a vital role in clinical imaging. It is necessary to provide a clear image to the surgeon for diagnosing the disorder and diseases of soft and complex tissue structure. Images obtained from the mammogram may have noises added to it during capturing of the image. Removing noise is still a challenging problem. Many filters are innovated to remove noise from the image with its postulation, advantage, and limitations. In this paper, Hybrid Median Filter (HMF), Linear Minimum Mean-Square-Error (LMMSE), Oriented Rician Noise Reduction Anisotropic Diffusion (ORNRAD), Higher Order Hybrid Median (HOHM), and Non-Level Means (NLM) denoising filters are used to remove noise from a mammogram image. The performance analyses of filters were evaluated by Mean Square Error (MSE), Peak Signal to Noise Ratio (PSNR), Image Quality Index (IQI), Mean Absolute Error (MAE), and Contrast to Noise Ratio (CNR) parameters. ORNRAD filter gives desirable results regarding above five quality and performance analysis attributes.","PeriodicalId":399107,"journal":{"name":"2016 Conference on Emerging Devices and Smart Systems (ICEDSS)","volume":"55 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114132587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-04DOI: 10.1109/ICEDSS.2016.7587783
Shilpa Bisnoi, S. Dasgupta
This paper presents the impact of gate underlap length and high-k spacer width on the parasitic capacitances of nanoscale Dual-K spacer FinFET. It was found that the optimum gate underlap length can considerably reduce the parasitic capacitances. Also, the impact of abrupt doping profile on the parasitic capacitance of the device is discussed. All the 2-D simulations were performed on 2-D Sentaurus TCAD device simulator.
{"title":"Parasitic capacitances of Dual-K spacer FinFET","authors":"Shilpa Bisnoi, S. Dasgupta","doi":"10.1109/ICEDSS.2016.7587783","DOIUrl":"https://doi.org/10.1109/ICEDSS.2016.7587783","url":null,"abstract":"This paper presents the impact of gate underlap length and high-k spacer width on the parasitic capacitances of nanoscale Dual-K spacer FinFET. It was found that the optimum gate underlap length can considerably reduce the parasitic capacitances. Also, the impact of abrupt doping profile on the parasitic capacitance of the device is discussed. All the 2-D simulations were performed on 2-D Sentaurus TCAD device simulator.","PeriodicalId":399107,"journal":{"name":"2016 Conference on Emerging Devices and Smart Systems (ICEDSS)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121830223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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