Pub Date : 2016-03-04DOI: 10.1109/ICEDSS.2016.7587775
Sheetal G. Jagtap, M. Bivalkar
Compressive sensing (CS) is a novel method for channel estimation. The recently introduced principle and the methodology of compressed sensing allow the efficient reconstruction of sparse signals of a very limited number of measurements. CS has gained a fast growing interest in applied mathematics. We consider the channel estimation in mobile environment using different methods. We identified an optimized method for compressive sensing in a mobile environment after an investigation of Orthogonal Matching Pursuit (OMP) and Delay-Doppler sparsity with reduced pilots for higher spectral efficiency. We demonstrated simulation results for 4-QAM and 16-QAM with the parameters of Least Square Estimation (LSE) and CS. Our simulation results show that the Delay-Doppler Sparsity achieved good spectral efficiency along with less probability of error.
{"title":"Optimized method for compressive sensing in mobile environment","authors":"Sheetal G. Jagtap, M. Bivalkar","doi":"10.1109/ICEDSS.2016.7587775","DOIUrl":"https://doi.org/10.1109/ICEDSS.2016.7587775","url":null,"abstract":"Compressive sensing (CS) is a novel method for channel estimation. The recently introduced principle and the methodology of compressed sensing allow the efficient reconstruction of sparse signals of a very limited number of measurements. CS has gained a fast growing interest in applied mathematics. We consider the channel estimation in mobile environment using different methods. We identified an optimized method for compressive sensing in a mobile environment after an investigation of Orthogonal Matching Pursuit (OMP) and Delay-Doppler sparsity with reduced pilots for higher spectral efficiency. We demonstrated simulation results for 4-QAM and 16-QAM with the parameters of Least Square Estimation (LSE) and CS. Our simulation results show that the Delay-Doppler Sparsity achieved good spectral efficiency along with less probability of error.","PeriodicalId":399107,"journal":{"name":"2016 Conference on Emerging Devices and Smart Systems (ICEDSS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116876253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-04DOI: 10.1109/ICEDSS.2016.7587692
M. Chanda, Diptansu Sinha, Jeet Basak, Tanushree Ganguli, C. Sarkar
Recently, behavior of adiabatic logic circuits have been analyzed in the literature due to the high demand for low power Portable application. In this paper, behaviors of Efficient Charge Recovery Logic (ECRL) logic structure has been analyzed in the sub-threshold regime for the first time in the literature. Proposed structures are efficacious compared to the conventional logic circuits due to very low leakage and very less amount of power dissipation. Design complexity can be reduced significantly by using single clocked supply. Static logic resembled structure of the proposed logic also reduces the silicon area. Studies of power dissipation, leakage, optimum frequency, etc. have been given analytically. Extensive CADENCE simulations in 22 nm node have been given to validate the proposed structure in sub-threshold regime.
{"title":"Design and analysis of adiabatic logic in sub-threshold regime for ultra low power application","authors":"M. Chanda, Diptansu Sinha, Jeet Basak, Tanushree Ganguli, C. Sarkar","doi":"10.1109/ICEDSS.2016.7587692","DOIUrl":"https://doi.org/10.1109/ICEDSS.2016.7587692","url":null,"abstract":"Recently, behavior of adiabatic logic circuits have been analyzed in the literature due to the high demand for low power Portable application. In this paper, behaviors of Efficient Charge Recovery Logic (ECRL) logic structure has been analyzed in the sub-threshold regime for the first time in the literature. Proposed structures are efficacious compared to the conventional logic circuits due to very low leakage and very less amount of power dissipation. Design complexity can be reduced significantly by using single clocked supply. Static logic resembled structure of the proposed logic also reduces the silicon area. Studies of power dissipation, leakage, optimum frequency, etc. have been given analytically. Extensive CADENCE simulations in 22 nm node have been given to validate the proposed structure in sub-threshold regime.","PeriodicalId":399107,"journal":{"name":"2016 Conference on Emerging Devices and Smart Systems (ICEDSS)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122542351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-04DOI: 10.1109/ICEDSS.2016.7587690
M. Chanda, Jeet Basak, Diptansu Sinha, Tanushree Ganguli, C. Sarkar
In super-threshold regime, a plethora of adiabatic logic styles are reported for ultra-low power design. In this paper a comparative analysis of transistor based imperative logic styles are analyzed in the sub-threshold regime for the first time in the literature. A uniform test bench is set up for fair comparison. Extensive CADENCE simulations were done using 22nm technology file to analyze the effect of loading, temperature and the supply voltage on power dissipations of the logic styles in sub-threshold regime. Significant differences in workability, power consumption, and logic degradation were found among the various logic styles. Simulation shows that efficient charge recovery logic (ECRL) is efficacious amongst the transistor based adiabatic logic styles in sub-threshold regime.
{"title":"Comparative analysis of adiabatic logics in sub-threshold regime for ultra-low power application","authors":"M. Chanda, Jeet Basak, Diptansu Sinha, Tanushree Ganguli, C. Sarkar","doi":"10.1109/ICEDSS.2016.7587690","DOIUrl":"https://doi.org/10.1109/ICEDSS.2016.7587690","url":null,"abstract":"In super-threshold regime, a plethora of adiabatic logic styles are reported for ultra-low power design. In this paper a comparative analysis of transistor based imperative logic styles are analyzed in the sub-threshold regime for the first time in the literature. A uniform test bench is set up for fair comparison. Extensive CADENCE simulations were done using 22nm technology file to analyze the effect of loading, temperature and the supply voltage on power dissipations of the logic styles in sub-threshold regime. Significant differences in workability, power consumption, and logic degradation were found among the various logic styles. Simulation shows that efficient charge recovery logic (ECRL) is efficacious amongst the transistor based adiabatic logic styles in sub-threshold regime.","PeriodicalId":399107,"journal":{"name":"2016 Conference on Emerging Devices and Smart Systems (ICEDSS)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122717008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-04DOI: 10.1109/ICEDSS.2016.7587777
S. Sharma, S. Dasgupta, M. Kartikeyan
In this paper, thorough study of Analytical thermal noise models for MOSFET is presented. Since the advent of basic MOSFET, various researchers develop the noise model. As, the device is shrinking the enhancement of the noise in the device attract researchers to make advances in the model according to new physical phenomenon that occur in deep sub-micron level. We are presented here, a review of recent analytical noise model published in the literature. The physical and analytical aspects of the drain current noise model are investigated here.
{"title":"A review of Analytical thermal noise model","authors":"S. Sharma, S. Dasgupta, M. Kartikeyan","doi":"10.1109/ICEDSS.2016.7587777","DOIUrl":"https://doi.org/10.1109/ICEDSS.2016.7587777","url":null,"abstract":"In this paper, thorough study of Analytical thermal noise models for MOSFET is presented. Since the advent of basic MOSFET, various researchers develop the noise model. As, the device is shrinking the enhancement of the noise in the device attract researchers to make advances in the model according to new physical phenomenon that occur in deep sub-micron level. We are presented here, a review of recent analytical noise model published in the literature. The physical and analytical aspects of the drain current noise model are investigated here.","PeriodicalId":399107,"journal":{"name":"2016 Conference on Emerging Devices and Smart Systems (ICEDSS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125668104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-04DOI: 10.1109/ICEDSS.2016.7587794
T. Prasannavenkatesan, T. Menakadevi
On-demand routing protocols are the most commonly used protocols for the MANETs. It is the dynamic protocol and suitable for many applications. Wireless mobile adhoc networks have gained a lot of significance in wireless communications. The data transmission between the nodes in the wireless communication was established by adopting the routing protocol. The node in mobile ad-hoc networks acts as routers as well as hosts in relaying packets from one node to another. The mobility of the nodes in the network makes the routing as a highly complex activity. To address the challenges of the routing issues and to overcome the problems several routing protocols are developed. Routing is the process of relaying information content from source to destination in the internetwork. For efficiently routing the data packets the network should have, at least, one intermediate neighbor node within the network. The routing of data packets in the network involves two activities: firstly, optimal routing path determination and secondly, relaying the data packets through an internetwork. In this paper, it is intensely discussed the different types on-demand routing protocols used for mobile ad hoc networks.
{"title":"Significance of scalability for on-demand routing protocols in MANETs","authors":"T. Prasannavenkatesan, T. Menakadevi","doi":"10.1109/ICEDSS.2016.7587794","DOIUrl":"https://doi.org/10.1109/ICEDSS.2016.7587794","url":null,"abstract":"On-demand routing protocols are the most commonly used protocols for the MANETs. It is the dynamic protocol and suitable for many applications. Wireless mobile adhoc networks have gained a lot of significance in wireless communications. The data transmission between the nodes in the wireless communication was established by adopting the routing protocol. The node in mobile ad-hoc networks acts as routers as well as hosts in relaying packets from one node to another. The mobility of the nodes in the network makes the routing as a highly complex activity. To address the challenges of the routing issues and to overcome the problems several routing protocols are developed. Routing is the process of relaying information content from source to destination in the internetwork. For efficiently routing the data packets the network should have, at least, one intermediate neighbor node within the network. The routing of data packets in the network involves two activities: firstly, optimal routing path determination and secondly, relaying the data packets through an internetwork. In this paper, it is intensely discussed the different types on-demand routing protocols used for mobile ad hoc networks.","PeriodicalId":399107,"journal":{"name":"2016 Conference on Emerging Devices and Smart Systems (ICEDSS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133725528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-04DOI: 10.1109/ICEDSS.2016.7587691
A. Akshay, D. Kiran, P. Chandramohan, P. Duraiswamy
Phase locked loops ( PLLs) with short locking time while still providing highest stability is required in today's wireless communication system. At high frequencies, the PLL locking time is affected by the large input capacitance of the Voltage Controlled Oscillator (VCO). In this paper, we propose a fast locking PLL operating at 2.4 GHz using a low mismatch gain boosted charge pump to reduce the current mismatches and switching errors. A 4-stage inverter buffer added to the charge pump increases the driving ability of the charge pump and reduces the locking time. Using the proposed charge pump, the PLL is implemented in 90nm CMOS technology. With a reference of 24 MHz, a locking time of 413.2ns is achieved. A locking time reduction of 65.5 percentage is obtained compared to the conventional charge pump. The PLL consumes a power of 265.4 microwatts with 1V DC.
{"title":"Design and analysis of Phase Locked Loop for low power wireless applications","authors":"A. Akshay, D. Kiran, P. Chandramohan, P. Duraiswamy","doi":"10.1109/ICEDSS.2016.7587691","DOIUrl":"https://doi.org/10.1109/ICEDSS.2016.7587691","url":null,"abstract":"Phase locked loops ( PLLs) with short locking time while still providing highest stability is required in today's wireless communication system. At high frequencies, the PLL locking time is affected by the large input capacitance of the Voltage Controlled Oscillator (VCO). In this paper, we propose a fast locking PLL operating at 2.4 GHz using a low mismatch gain boosted charge pump to reduce the current mismatches and switching errors. A 4-stage inverter buffer added to the charge pump increases the driving ability of the charge pump and reduces the locking time. Using the proposed charge pump, the PLL is implemented in 90nm CMOS technology. With a reference of 24 MHz, a locking time of 413.2ns is achieved. A locking time reduction of 65.5 percentage is obtained compared to the conventional charge pump. The PLL consumes a power of 265.4 microwatts with 1V DC.","PeriodicalId":399107,"journal":{"name":"2016 Conference on Emerging Devices and Smart Systems (ICEDSS)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115935044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-04DOI: 10.1109/ICEDSS.2016.7587773
H. S. Sridhar, M. Siddappa, G. C. Bhanu Prakash
Rising smart grid networks are depended upon to have huge measures of data continuously created from various measuring devices like sensors, meters, electric vehicle charging stations, and so on which are installed in the power grid. Data created from these measuring devises must be passed on securely and safely to utility control places for wide-territory control and observing and to evaluate the general system status in an advantageous and correct way. The gathered information is moreover utilized as a piece of customer investment for enhancing power security. The secured transport protocol is required for such smart grid. Measurement data are described as secure and solid conveyance reliable delivery over utility-Wide Area Networks (WANs). On the other hand, our overview demonstrates that there is no surely understood transport protocol that can support the above attributes in an adaptable and light-weight way. Inspired by this, we plan a Smart Grid Secure Protocol, SGSP, exploiting the notion of a “State-token” which is issued with each node message and which is along these lines joined to relating customer message conveyed to the utility. Differentiated and existing clearly comprehended transport and security schemes, SGSP enables versatile server connection with each node when it is needed. In this paper, we discussed the need secure connection in smart grid and shows that way of establishing the connection between the each smart grid nodes securely.
{"title":"Design of secure communication protocol for Smart Grid","authors":"H. S. Sridhar, M. Siddappa, G. C. Bhanu Prakash","doi":"10.1109/ICEDSS.2016.7587773","DOIUrl":"https://doi.org/10.1109/ICEDSS.2016.7587773","url":null,"abstract":"Rising smart grid networks are depended upon to have huge measures of data continuously created from various measuring devices like sensors, meters, electric vehicle charging stations, and so on which are installed in the power grid. Data created from these measuring devises must be passed on securely and safely to utility control places for wide-territory control and observing and to evaluate the general system status in an advantageous and correct way. The gathered information is moreover utilized as a piece of customer investment for enhancing power security. The secured transport protocol is required for such smart grid. Measurement data are described as secure and solid conveyance reliable delivery over utility-Wide Area Networks (WANs). On the other hand, our overview demonstrates that there is no surely understood transport protocol that can support the above attributes in an adaptable and light-weight way. Inspired by this, we plan a Smart Grid Secure Protocol, SGSP, exploiting the notion of a “State-token” which is issued with each node message and which is along these lines joined to relating customer message conveyed to the utility. Differentiated and existing clearly comprehended transport and security schemes, SGSP enables versatile server connection with each node when it is needed. In this paper, we discussed the need secure connection in smart grid and shows that way of establishing the connection between the each smart grid nodes securely.","PeriodicalId":399107,"journal":{"name":"2016 Conference on Emerging Devices and Smart Systems (ICEDSS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128748304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-04DOI: 10.1109/ICEDSS.2016.7587793
Muhammed P. P. Rajees, J. Rocky
Renewable energy sources have more importance. This importance is mainly because of limited resource and environmental problems of the conventional energy. Among the all renewable energy resources available, solar energy seems to be a major competitor as it is abundant in nature and also pollution-free. And we can convert this dc from solar panel to single phase AC source by using single phase inverter. This AC source is the supply for BLDC motor drive. And speed control method of BLDC motor with low cost for low power applications can be done by using a power factor corrected bridgeless buck-boost converter. Speed control is by controlling the dc link voltage of the voltage source inverter (VSI). Bridgeless converter reduces the conduction losses in the diode bridge rectifier. Commutation of the BLDC motor is by using VSI, which reduces the switching losses and it avoid the sparking and wear and tear by mechanical commutation and it is known as electronic commutation. Power factor improvement is done by designing the converter in discontinuous inductor current mode (DCM). As compared with other speed controlling method, speed control of BLDC motor by power factor corrected bridge less buck-boost convertor uses reduced number of components. This method has high efficiency and low cost as compared with other speed controlling method of BLDC motor and improved power quality is also achieved.
{"title":"Solar Powered Variable Speed Power Factor Corrected BLDC Motor drive","authors":"Muhammed P. P. Rajees, J. Rocky","doi":"10.1109/ICEDSS.2016.7587793","DOIUrl":"https://doi.org/10.1109/ICEDSS.2016.7587793","url":null,"abstract":"Renewable energy sources have more importance. This importance is mainly because of limited resource and environmental problems of the conventional energy. Among the all renewable energy resources available, solar energy seems to be a major competitor as it is abundant in nature and also pollution-free. And we can convert this dc from solar panel to single phase AC source by using single phase inverter. This AC source is the supply for BLDC motor drive. And speed control method of BLDC motor with low cost for low power applications can be done by using a power factor corrected bridgeless buck-boost converter. Speed control is by controlling the dc link voltage of the voltage source inverter (VSI). Bridgeless converter reduces the conduction losses in the diode bridge rectifier. Commutation of the BLDC motor is by using VSI, which reduces the switching losses and it avoid the sparking and wear and tear by mechanical commutation and it is known as electronic commutation. Power factor improvement is done by designing the converter in discontinuous inductor current mode (DCM). As compared with other speed controlling method, speed control of BLDC motor by power factor corrected bridge less buck-boost convertor uses reduced number of components. This method has high efficiency and low cost as compared with other speed controlling method of BLDC motor and improved power quality is also achieved.","PeriodicalId":399107,"journal":{"name":"2016 Conference on Emerging Devices and Smart Systems (ICEDSS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130848068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-04DOI: 10.1109/ICEDSS.2016.7587778
N. Balamurugan, M. Abirami, B. Buvaneswari, K. Sowmya
An analytical model for Quad gate MOSFETs considering the quantum mechanical effects that influences the performance of MOSFETs is proposed. A variable separable method used to solve the Poisson and Schrodinger equation which thereby reveals the quantum mechanical effects. An analytical expression of the inversion space charge density function for all region of the devices operation is developed. Using this expression, other parameters like Drain current, Lower sub band energy, Inversion charge sheet density, gate voltage are calculated. By considering Quantum Mechanical Effect (QME). This analytical solution gives simple and accurate insight into the quantization for various gate biases. This analytical result is compared with other existing multi gate MOSFET.
{"title":"Analytical modeling of nanoscale Quad Gate MOSFET including quantum mechanical effects","authors":"N. Balamurugan, M. Abirami, B. Buvaneswari, K. Sowmya","doi":"10.1109/ICEDSS.2016.7587778","DOIUrl":"https://doi.org/10.1109/ICEDSS.2016.7587778","url":null,"abstract":"An analytical model for Quad gate MOSFETs considering the quantum mechanical effects that influences the performance of MOSFETs is proposed. A variable separable method used to solve the Poisson and Schrodinger equation which thereby reveals the quantum mechanical effects. An analytical expression of the inversion space charge density function for all region of the devices operation is developed. Using this expression, other parameters like Drain current, Lower sub band energy, Inversion charge sheet density, gate voltage are calculated. By considering Quantum Mechanical Effect (QME). This analytical solution gives simple and accurate insight into the quantization for various gate biases. This analytical result is compared with other existing multi gate MOSFET.","PeriodicalId":399107,"journal":{"name":"2016 Conference on Emerging Devices and Smart Systems (ICEDSS)","volume":"213 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123297258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-01DOI: 10.1109/ICEDSS.2016.7587796
S. U. Raj, T. George
Conveyor systems allow quick and efficient transportation for a wide variety of materials, which make them very popular in the material handling and packaging industries. Many kinds of conveying systems are available and used according to the various needs of different industries. Adjustable speed drives are used for the operation of the conveyors used in a number of industries. We can use adjustable electric drives in a number of industrial applications. A typical adjustable speed drive consists of an induction motor and a power electronic converter. In most cases, motor speed is commanded so that the control system requires an actual speed signal for closing the speed loop. In industrial applications, speed sensors, as well as sensorless solutions, are used. Due to the possibility of current speed sensor noises and for maintenance and economic aspects, the trend is to substitute speed sensors by computational solutions. Comprehensive reviews of the sensorless drives show that there are still some persistent problems associated with the sensorless control, that needs new solutions. In ASDs, the advanced control approach of IM is the FOC method, used in modern industrial drives. The current stator controller is the integral part of various FOC systems. In the classical FOC solution, PI or hysteresis controllers are generally used. However, PCCs are reported to have better properties. System sensitivity to inaccuracy and changes of motor equivalent circuit parameters are another problem in electrical drives. Almost all of the FOC systems are very sensitive to such inaccuracies; therefore, some parameters should be estimated online, and a robust structure of the control is required. The real-time implementation of the system is an important task even for electric drives or power converters.
{"title":"Speed sensorless induction motor drive with PCC in conveyor systems","authors":"S. U. Raj, T. George","doi":"10.1109/ICEDSS.2016.7587796","DOIUrl":"https://doi.org/10.1109/ICEDSS.2016.7587796","url":null,"abstract":"Conveyor systems allow quick and efficient transportation for a wide variety of materials, which make them very popular in the material handling and packaging industries. Many kinds of conveying systems are available and used according to the various needs of different industries. Adjustable speed drives are used for the operation of the conveyors used in a number of industries. We can use adjustable electric drives in a number of industrial applications. A typical adjustable speed drive consists of an induction motor and a power electronic converter. In most cases, motor speed is commanded so that the control system requires an actual speed signal for closing the speed loop. In industrial applications, speed sensors, as well as sensorless solutions, are used. Due to the possibility of current speed sensor noises and for maintenance and economic aspects, the trend is to substitute speed sensors by computational solutions. Comprehensive reviews of the sensorless drives show that there are still some persistent problems associated with the sensorless control, that needs new solutions. In ASDs, the advanced control approach of IM is the FOC method, used in modern industrial drives. The current stator controller is the integral part of various FOC systems. In the classical FOC solution, PI or hysteresis controllers are generally used. However, PCCs are reported to have better properties. System sensitivity to inaccuracy and changes of motor equivalent circuit parameters are another problem in electrical drives. Almost all of the FOC systems are very sensitive to such inaccuracies; therefore, some parameters should be estimated online, and a robust structure of the control is required. The real-time implementation of the system is an important task even for electric drives or power converters.","PeriodicalId":399107,"journal":{"name":"2016 Conference on Emerging Devices and Smart Systems (ICEDSS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134268057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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