Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708710
M. Baláz, P. Malík, T. Pikula, M. Simlastík
Digital compression of audio signals has become increasingly more important with the advent of fast and inexpensive microprocessors and digital signal processors. Several compression schemes were developed and well established. Most of them adopt MDCT/IMDCT. This paper presents a new MDCT IP core generator. The software tool generates several MDCT architectures with adjustable parameters for FPGA-based design
{"title":"MDCT IP core generator","authors":"M. Baláz, P. Malík, T. Pikula, M. Simlastík","doi":"10.1109/DTIS.2006.1708710","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708710","url":null,"abstract":"Digital compression of audio signals has become increasingly more important with the advent of fast and inexpensive microprocessors and digital signal processors. Several compression schemes were developed and well established. Most of them adopt MDCT/IMDCT. This paper presents a new MDCT IP core generator. The software tool generates several MDCT architectures with adjustable parameters for FPGA-based design","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126324267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1080/00207210701827954
M. Dufils, J. Carbonéro, P. Planelle, P. Raynaud
This paper presents the current work that is done in order to simulate analog or mixed-signal tests and then transfer these simulations and their results to the ATE. After having stated the problem, the proposed flow will be reviewed, leading to a more detailed description of the VHDL-AMS simulations, of the STIL-AMS language under definition, as well as to its road map. One of the major decisions taken, a device-centric approach versus a tester-centric approach, will then be explained, before showing some of the actual limitations of the approach. Before concluding, the real case that has been implemented will be described, and some of the debug steps that have been done
{"title":"Mixed-signal simulation and test generation","authors":"M. Dufils, J. Carbonéro, P. Planelle, P. Raynaud","doi":"10.1080/00207210701827954","DOIUrl":"https://doi.org/10.1080/00207210701827954","url":null,"abstract":"This paper presents the current work that is done in order to simulate analog or mixed-signal tests and then transfer these simulations and their results to the ATE. After having stated the problem, the proposed flow will be reviewed, leading to a more detailed description of the VHDL-AMS simulations, of the STIL-AMS language under definition, as well as to its road map. One of the major decisions taken, a device-centric approach versus a tester-centric approach, will then be explained, before showing some of the actual limitations of the approach. Before concluding, the real case that has been implemented will be described, and some of the debug steps that have been done","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122664276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708680
S. Léomant, A. Turier, L. Ben Ammar, A. Amara
Leakage currents are of major concern in nanometer technologies. To address this issue, it is essential to have a good understanding of all leakage contributors, very soon during the new technology development step. This paper presents our methodology to accurately characterize leakage in SRAM cells, while keeping same environment of a product. Process control monitors, containing different structures to measure sub-threshold, gate, gate induced drain and junction leakages, in each SRAM bit-cell transistor, are described. Other structures are used to quantify the impact on leakage of edge effects and strap locations. Presented design and measurement methodology allows a separate characterizing of each leakage contributor; in order to optimize consumption in chips using ATMKL 130nm CMOS technology
{"title":"SRAM dedicated PCMs for leakage characterization in nanometer CMOS technologies","authors":"S. Léomant, A. Turier, L. Ben Ammar, A. Amara","doi":"10.1109/DTIS.2006.1708680","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708680","url":null,"abstract":"Leakage currents are of major concern in nanometer technologies. To address this issue, it is essential to have a good understanding of all leakage contributors, very soon during the new technology development step. This paper presents our methodology to accurately characterize leakage in SRAM cells, while keeping same environment of a product. Process control monitors, containing different structures to measure sub-threshold, gate, gate induced drain and junction leakages, in each SRAM bit-cell transistor, are described. Other structures are used to quantify the impact on leakage of edge effects and strap locations. Presented design and measurement methodology allows a separate characterizing of each leakage contributor; in order to optimize consumption in chips using ATMKL 130nm CMOS technology","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123096387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708696
A. Sobhani, M. Daneshtalab, Mohammad Hossein Neishaburi, M. D. Mottaghi, A. Afzali-Kusha, O. Fatemi, Z. Navabi
In this paper, we proposed a routing model for distributing hot spots within on-chip networks. It takes advantage of both adaptive minimal path and non-minimal path algorithms. To evaluate the efficiency of the model, a simulator developed using C++ is employed to compare the methods. The simulation results show that in realistic traffic models, like first transpose traffic, and in dense traffics the proposed algorithm has lower average delays compared to the previously proposed models
{"title":"Dynamic routing algorithm for avoiding hot spots in on-chip networks","authors":"A. Sobhani, M. Daneshtalab, Mohammad Hossein Neishaburi, M. D. Mottaghi, A. Afzali-Kusha, O. Fatemi, Z. Navabi","doi":"10.1109/DTIS.2006.1708696","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708696","url":null,"abstract":"In this paper, we proposed a routing model for distributing hot spots within on-chip networks. It takes advantage of both adaptive minimal path and non-minimal path algorithms. To evaluate the efficiency of the model, a simulator developed using C++ is employed to compare the methods. The simulation results show that in realistic traffic models, like first transpose traffic, and in dense traffics the proposed algorithm has lower average delays compared to the previously proposed models","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131461612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1080/00207210701828010
A. El-Sabban, H. Ragai
In this paper, an RF power amplifier intended for Class 1 Bluetooth application is designed using 0.35mum CMOS technology. A layout-aware macromodel for the BSIM3v3 MOSFET transistor for RF applications including substrate effect is investigated and used in this design. The model is validated for a 0.35mum CMOS process using a transistor with total width of 90mum and 18 fingers and it shows an excellent agreement with the ft, and S-parameter measurement data up to 6GHz. Effect of pads and bond wires are also taken into consideration during the design process of the PA. After post-layout simulations, the amplifier delivers an output power of 19dBm with 33.7% PAE under 3.3V supply. This amplifier has a power control feature. Its two stage circuit utilizes a cascode configuration in its first stage in order to use its bias pin as a power control input for the amplifier. Using this method, the power control range can be decreased down to 1.4 dBm which satisfies the Bluetooth standard. The chip is fabricated and is currently under testing
本文采用0.35 μ m CMOS技术，设计了一种适用于1类蓝牙应用的射频功率放大器。本文研究了一种用于射频应用的BSIM3v3 MOSFET晶体管的布局感知宏模型，并将其应用于本设计中。该模型在0.35 μ m CMOS工艺中使用总宽度为90μ m、18指的晶体管进行了验证，结果表明该模型与高达6GHz的ft和s参数测量数据具有良好的一致性。在设计过程中还考虑了焊盘和焊线的影响。经过布局后仿真，该放大器在3.3V电源下的输出功率为19dBm, PAE为33.7%。这个放大器有功率控制功能。其两级电路在其第一级采用级联码配置，以便将其偏置引脚用作放大器的功率控制输入。使用该方法，可以将功率控制范围减小到1.4 dBm，满足蓝牙标准。该芯片已制成，目前正在测试中
{"title":"Design of power-controlled Class1 Bluetooth CMOS power amplifier","authors":"A. El-Sabban, H. Ragai","doi":"10.1080/00207210701828010","DOIUrl":"https://doi.org/10.1080/00207210701828010","url":null,"abstract":"In this paper, an RF power amplifier intended for Class 1 Bluetooth application is designed using 0.35mum CMOS technology. A layout-aware macromodel for the BSIM3v3 MOSFET transistor for RF applications including substrate effect is investigated and used in this design. The model is validated for a 0.35mum CMOS process using a transistor with total width of 90mum and 18 fingers and it shows an excellent agreement with the ft, and S-parameter measurement data up to 6GHz. Effect of pads and bond wires are also taken into consideration during the design process of the PA. After post-layout simulations, the amplifier delivers an output power of 19dBm with 33.7% PAE under 3.3V supply. This amplifier has a power control feature. Its two stage circuit utilizes a cascode configuration in its first stage in order to use its bias pin as a power control input for the amplifier. Using this method, the power control range can be decreased down to 1.4 dBm which satisfies the Bluetooth standard. The chip is fabricated and is currently under testing","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132032405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708660
I. Voyiatzis, C. Efstathiou
Built-in self test (BIST) techniques are widely used in today's complex integrated circuits, since they employ on-chip test pattern generation and response verification. Arithmetic BIST techniques utilize modules that commonly exist in datapath modules (accumulators, counters etc.). In order to perform the test generation and response verification operations. In order to detect sequential faults that occur into current CMOS circuits, two-pattern tests are required. Furthermore, delay testing, commonly used to assure correct temporal circuit operation at clock speed, requires two-pattern tests. In this paper a novel algorithm for the generation of two-pattern tests is presented. The presented algorithm utilizes modules included in datapath circuitry to generate two-pattern tests; its implementation in hardware compares favorably with techniques that have been presented in the open literature
{"title":"Two-pattern generation based on accumulators with 1's complement adders","authors":"I. Voyiatzis, C. Efstathiou","doi":"10.1109/DTIS.2006.1708660","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708660","url":null,"abstract":"Built-in self test (BIST) techniques are widely used in today's complex integrated circuits, since they employ on-chip test pattern generation and response verification. Arithmetic BIST techniques utilize modules that commonly exist in datapath modules (accumulators, counters etc.). In order to perform the test generation and response verification operations. In order to detect sequential faults that occur into current CMOS circuits, two-pattern tests are required. Furthermore, delay testing, commonly used to assure correct temporal circuit operation at clock speed, requires two-pattern tests. In this paper a novel algorithm for the generation of two-pattern tests is presented. The presented algorithm utilizes modules included in datapath circuitry to generate two-pattern tests; its implementation in hardware compares favorably with techniques that have been presented in the open literature","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126785047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708684
A. K. Oudjida, A. Liacha, D. Benamrouche, M. Goudjil, R. Tiar, A. Ouchabane
Based on a recent market study of an important number of I2 C devices, all fully compliant with the Philips I2C-bus specification, version 2.1, release January 2000, this paper introduces a detailed I2C-slave VLSI-architecture that incorporates all necessary features required by modern ASK/SoC applications, except high speed mode. The design is a general purpose solution offering viable ways to controlling I2C-bus and highly flexible to suit any particular needs. The purpose of this paper is to provide a full description of an up-to-date I2C-slave VLSI-implementation. All related issues, starting from the elaboration of initial specifications, till the final verifications and synthesis, are comprehensively discussed and justified. This includes all issues from basic architectural operations to final software drivers and application. The whole design code, either for synthesis or verification, is implemented in Verilog 2001 (IEEE 1365.) The synthesis design code is technology independent and was simulated at both RTL and gate level with timing back annotation using ModelSim SE 5.8e and synthesized using both Leonardo Spectrum V2001_1d.45 and Xilinx's XST 6.1i
基于最近对大量i2c设备的市场研究，所有这些设备都完全符合Philips i2c总线规范，版本2.1,2000年1月发布，本文介绍了一个详细的i2c从vlsi架构，它包含了现代ASK/SoC应用所需的所有必要功能，除了高速模式。该设计是一种通用解决方案，提供了控制i2c总线的可行方法，并高度灵活地满足任何特定需求。本文的目的是提供最新的i2c从vlsi实现的完整描述。所有相关的问题，从最初的规范的阐述，直到最后的验证和综合，全面讨论和论证。这包括从基本架构操作到最终软件驱动程序和应用程序的所有问题。整个设计代码，无论是合成还是验证，都是在Verilog 2001 (IEEE 1365)中实现的。合成设计代码是独立于技术的，使用ModelSim SE 5.8e在RTL和门级进行了模拟，并使用Leonardo Spectrum v20011d进行了合成。45和Xilinx的XST 6.1i
{"title":"Universal low/medium speed I/sup 2/C-slave transceiver: a detailed VLSI implementation","authors":"A. K. Oudjida, A. Liacha, D. Benamrouche, M. Goudjil, R. Tiar, A. Ouchabane","doi":"10.1109/DTIS.2006.1708684","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708684","url":null,"abstract":"Based on a recent market study of an important number of I2 C devices, all fully compliant with the Philips I2C-bus specification, version 2.1, release January 2000, this paper introduces a detailed I2C-slave VLSI-architecture that incorporates all necessary features required by modern ASK/SoC applications, except high speed mode. The design is a general purpose solution offering viable ways to controlling I2C-bus and highly flexible to suit any particular needs. The purpose of this paper is to provide a full description of an up-to-date I2C-slave VLSI-implementation. All related issues, starting from the elaboration of initial specifications, till the final verifications and synthesis, are comprehensively discussed and justified. This includes all issues from basic architectural operations to final software drivers and application. The whole design code, either for synthesis or verification, is implemented in Verilog 2001 (IEEE 1365.) The synthesis design code is technology independent and was simulated at both RTL and gate level with timing back annotation using ModelSim SE 5.8e and synthesized using both Leonardo Spectrum V2001_1d.45 and Xilinx's XST 6.1i","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115985340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708718
F. Boussaid, C. Shoushun, A. Bermak
In this paper, the authors propose a scalable spiking pixel architecture for deep submicron CMOS technologies. The proposed pixel architecture uniquely combines counting and memory functions into a single compact circuit, providing for in-pixel storage capability; in-pixel analog-to-digital conversion and random read-out of digital pixel values. Pixel fill-factor is better than 15% for a 50times50mum pixel fabricated using AMI 0.35mum CMOS technology. Reported experimental results validate the proposed spiking pixel architecture for the next generation of deep submicron silicon processes
在本文中，作者提出了一种用于深亚微米CMOS技术的可扩展尖峰像素架构。提出的像素架构独特地将计数和存储功能结合到单个紧凑电路中，提供像素内存储能力;像素内模数转换和随机读出数字像素值。对于采用AMI 0.35 μ m CMOS技术制造的50倍50μ m像素，像素填充系数优于15%。实验结果验证了所提出的用于下一代深亚微米硅工艺的峰值像素架构
{"title":"A novel scalable spiking pixel architecture for deep submicron CMOS technologies","authors":"F. Boussaid, C. Shoushun, A. Bermak","doi":"10.1109/DTIS.2006.1708718","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708718","url":null,"abstract":"In this paper, the authors propose a scalable spiking pixel architecture for deep submicron CMOS technologies. The proposed pixel architecture uniquely combines counting and memory functions into a single compact circuit, providing for in-pixel storage capability; in-pixel analog-to-digital conversion and random read-out of digital pixel values. Pixel fill-factor is better than 15% for a 50times50mum pixel fabricated using AMI 0.35mum CMOS technology. Reported experimental results validate the proposed spiking pixel architecture for the next generation of deep submicron silicon processes","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117271735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/ICECS.2006.379945
M. Krid, Alima Damak Masmoudi, D. Masmoudi
This paper presents an implementation of a pulse mode multilayer neural network with on chip learning. Taking advantage of the compactness of the multiplierless solutions proposed in the literature, we apply a multiplierless architecture, in which the synapse is made up with a DDFS and the neuron uses a nonlinear adder. A programmable activation function is proposed by means of an adjustable pulse multiplier so that the activation function slope can be adjusted without any added hardware cost. The proposed architecture was tested in a signature recognition system. It shows good learning capability. The corresponding design was implemented into a Virtex II PRO XC2VP7 Xilinx FPGA
提出了一种具有片上学习功能的脉冲模式多层神经网络的实现方法。利用文献中提出的无乘法器解决方案的紧凑性，我们采用无乘法器架构，其中突触由DDFS组成，神经元使用非线性加法器。利用可调脉冲乘法器，提出了一种可编程的激活函数，使激活函数的斜率可以在不增加硬件成本的情况下进行调整。在签名识别系统中对所提出的体系结构进行了测试。表现出良好的学习能力。相应的设计在Virtex II PRO XC2VP7 Xilinx FPGA中实现
{"title":"FPGA implementation of programmable pulse mode neural network with on chip learning","authors":"M. Krid, Alima Damak Masmoudi, D. Masmoudi","doi":"10.1109/ICECS.2006.379945","DOIUrl":"https://doi.org/10.1109/ICECS.2006.379945","url":null,"abstract":"This paper presents an implementation of a pulse mode multilayer neural network with on chip learning. Taking advantage of the compactness of the multiplierless solutions proposed in the literature, we apply a multiplierless architecture, in which the synapse is made up with a DDFS and the neuron uses a nonlinear adder. A programmable activation function is proposed by means of an adjustable pulse multiplier so that the activation function slope can be adjusted without any added hardware cost. The proposed architecture was tested in a signature recognition system. It shows good learning capability. The corresponding design was implemented into a Virtex II PRO XC2VP7 Xilinx FPGA","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115364381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708658
R. Mendoza, A. Ferré, L. Balado, J. Figueras
Leakage power consumption in nanometric CMOS circuits is growing at exponential rate due to the aggressive scaling trends of channel lengths, gate oxide thickness and doping profiles. In this paper the analysis and characterization of leakage currents and the corresponding leakage power is studied at cell level. A characterization methodology is discussed and applied to inverter, NAND and NOR cells using the Berkeley predictive technology model BPTM for BSIM 4.50 and HSPICE. The simulation results for 65, 45 and 32nm CMOS performed in these cells show the high dependence of leakage power on the circuit state and the increasing impact of gate leakage on the variability of the total leakage of the cell
{"title":"CMOS leakage power at cell level","authors":"R. Mendoza, A. Ferré, L. Balado, J. Figueras","doi":"10.1109/DTIS.2006.1708658","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708658","url":null,"abstract":"Leakage power consumption in nanometric CMOS circuits is growing at exponential rate due to the aggressive scaling trends of channel lengths, gate oxide thickness and doping profiles. In this paper the analysis and characterization of leakage currents and the corresponding leakage power is studied at cell level. A characterization methodology is discussed and applied to inverter, NAND and NOR cells using the Berkeley predictive technology model BPTM for BSIM 4.50 and HSPICE. The simulation results for 65, 45 and 32nm CMOS performed in these cells show the high dependence of leakage power on the circuit state and the increasing impact of gate leakage on the variability of the total leakage of the cell","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128565027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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