Pub Date : 2006-10-16DOI: 10.1080/00207210701827863
M. Ben Amor, A. Fakhfakh, H. Mnif, M. Loulou
A new architecture of dual band receiver was introduced; it is able to make simultaneous operations at two different frequency bands. This architecture uses a new dual band low noise amplifier (LNA). A novel high gain and low noise amplifier topology is proposed. This paper presents a general methodology to design a LNA with current reuse topology for the two standards GSM and UMTS at 947.5MHz and 2.14GHz frequencies respectively, A fully integrated dual band LNA was designed using 0.35mum CMOS process. At 947.5MHz, the LNA exhibits a noise figure of 2.3dB, a voltage gain of 28dB, a CP1 of -12dBm. However, the LNA at 2.14GHz features a noise figure of 2.71dB, a voltage gain of 17dB and a CP1 of -4.5dBm. The power consumption is 37.5mW under a power supply voltage of 2.5V
介绍了一种新的双频接收机结构;它能够在两个不同的频段同时进行操作。该架构采用了一种新型双频低噪声放大器(LNA)。提出了一种新的高增益低噪声放大器拓扑结构。本文提出了一种针对GSM和UMTS两种标准(分别为947.5MHz和2.14GHz)的当前复用拓扑设计LNA的一般方法，采用0.35 μ m CMOS工艺设计了一种完全集成的双频LNA。在947.5MHz时，LNA的噪声系数为2.3dB，电压增益为28dB, CP1为-12dBm。然而，2.14GHz的LNA噪声系数为2.71dB，电压增益为17dB, CP1为-4.5dBm。电源电压为2.5V时，功耗为37.5mW
{"title":"Dual band CMOS LNA design with current reuse topology","authors":"M. Ben Amor, A. Fakhfakh, H. Mnif, M. Loulou","doi":"10.1080/00207210701827863","DOIUrl":"https://doi.org/10.1080/00207210701827863","url":null,"abstract":"A new architecture of dual band receiver was introduced; it is able to make simultaneous operations at two different frequency bands. This architecture uses a new dual band low noise amplifier (LNA). A novel high gain and low noise amplifier topology is proposed. This paper presents a general methodology to design a LNA with current reuse topology for the two standards GSM and UMTS at 947.5MHz and 2.14GHz frequencies respectively, A fully integrated dual band LNA was designed using 0.35mum CMOS process. At 947.5MHz, the LNA exhibits a noise figure of 2.3dB, a voltage gain of 28dB, a CP1 of -12dBm. However, the LNA at 2.14GHz features a noise figure of 2.71dB, a voltage gain of 17dB and a CP1 of -4.5dBm. The power consumption is 37.5mW under a power supply voltage of 2.5V","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126994206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708709
M. Alassir, J. Denoulet, O. Romain, P. Garda
The authors present the design of an intellectual property (IP) modeling the interface controller for an inter-integrated controller channel (I2C) bus. AMS IPs such as bus interfaces, whose behaviour follows the bus protocols in terms of packet structure, timing constraints or control modes can offer solutions for the issue of communications between a system on a chip and its external environment. The model of our controller is written in SystemC in association with a SystemC-AMS description of the analog block. Simulation results are presented
{"title":"A SystemC AMS model of an 12C bus controller","authors":"M. Alassir, J. Denoulet, O. Romain, P. Garda","doi":"10.1109/DTIS.2006.1708709","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708709","url":null,"abstract":"The authors present the design of an intellectual property (IP) modeling the interface controller for an inter-integrated controller channel (I2C) bus. AMS IPs such as bus interfaces, whose behaviour follows the bus protocols in terms of packet structure, timing constraints or control modes can offer solutions for the issue of communications between a system on a chip and its external environment. The model of our controller is written in SystemC in association with a SystemC-AMS description of the analog block. Simulation results are presented","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"236 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132220451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708716
P. Balasubramanian, Y. Sirisha
In this work, the authors consider the problem of logic minimization for a special class of Boolean networks, targeting low power implementation, using static CMOS logic. The authors start by framing a new binary minterm-value (BmV) matrix/binary max term-value (BMV) matrix for a binary 2-tuple, [mi (Mi), mj (Mj)], where HD (mi (Mi), mj (Mj)) is O(n), where n represents the support of a Boolean function. The quality of the resulting circuits, evaluated on the basis of established cost metrics for a modest 0.35mu TSMC CMOS process, demonstrate average savings in power by 14.39% for the samples mentioned in this paper, besides reduction in gate and literal count by 36.59% and 11.35% respectively, over the best of existing methods
{"title":"Power aware minimization of complementary logic functions based on maximal HD","authors":"P. Balasubramanian, Y. Sirisha","doi":"10.1109/DTIS.2006.1708716","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708716","url":null,"abstract":"In this work, the authors consider the problem of logic minimization for a special class of Boolean networks, targeting low power implementation, using static CMOS logic. The authors start by framing a new binary minterm-value (BmV) matrix/binary max term-value (BMV) matrix for a binary 2-tuple, [mi (Mi), mj (Mj)], where HD (mi (Mi), mj (Mj)) is O(n), where n represents the support of a Boolean function. The quality of the resulting circuits, evaluated on the basis of established cost metrics for a modest 0.35mu TSMC CMOS process, demonstrate average savings in power by 14.39% for the samples mentioned in this paper, besides reduction in gate and literal count by 36.59% and 11.35% respectively, over the best of existing methods","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115159987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708715
P. Balasubramanian, T. S.
This paper presents a synthesis framework for the important class of non-regenerative Boolean read-once functions (BROF). A two-pronged approach is adopted, where the satisfiability of the circuit functionality with minimum no. of active gates is first given priority. The gate level realizations are then translated into circuit level implementations viz., static CMOS LECTOR and stacked CMOS LECTOR styles, to evaluate the efficacy of our proposition on the basis of energy delay product (EDP) metric. Furthermore, the effect of transistor reordering on the delay of CMOS digital circuits is investigated. The SPICE based simulation results obtained for a modest 0.35mum TSMC process are promising, as it reports 41.5% savings in EDP, 10.5% reduction in power and 17.7% decrease in delay, over the best of conventional methods
本文给出了一类重要的非再生布尔读一次函数的综合框架。采用双管齐下的方法，其中电路功能的满意度与最小的no。活动门的优先级。然后将门级实现转换为电路级实现，即静态CMOS LECTOR和堆叠CMOS LECTOR样式，以基于能量延迟积(EDP)度量来评估我们的命题的有效性。此外，还研究了晶体管重排序对CMOS数字电路延时的影响。基于SPICE的模拟结果显示，与传统方法相比，0.35 μ m TSMC工艺的EDP降低了41.5%，功率降低了10.5%，延迟降低了17.7%
{"title":"EDP optimized synthesis scheme for Boolean read-once functions","authors":"P. Balasubramanian, T. S.","doi":"10.1109/DTIS.2006.1708715","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708715","url":null,"abstract":"This paper presents a synthesis framework for the important class of non-regenerative Boolean read-once functions (BROF). A two-pronged approach is adopted, where the satisfiability of the circuit functionality with minimum no. of active gates is first given priority. The gate level realizations are then translated into circuit level implementations viz., static CMOS LECTOR and stacked CMOS LECTOR styles, to evaluate the efficacy of our proposition on the basis of energy delay product (EDP) metric. Furthermore, the effect of transistor reordering on the delay of CMOS digital circuits is investigated. The SPICE based simulation results obtained for a modest 0.35mum TSMC process are promising, as it reports 41.5% savings in EDP, 10.5% reduction in power and 17.7% decrease in delay, over the best of conventional methods","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115077212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
SystemC language as well as the verification library going with (SCV), provides a rich set of features for dynamic control and parameterization of the constraints applied to a constrained-random stimulus generator. Besides, the property specification language (PSL) offers facilities for gathering and inspecting functional coverage information. This paper examines how SCV stimulus constraints can be modified dynamically using functional PSL coverage data, with the aim of avoiding the redundancy of stimulus within the regression test suite. In so doing we allow reducing simulation runtime needed to meet planned functional coverage
{"title":"Verification flow optimization using an automatic coverage driven testing policy","authors":"Younes Lahbib, Oualid Missaoui, Maher Hechkel, Dhafer Lahbib, Badreddine Mohamed-Yosri, R. Tourki","doi":"10.1109/DTIS.2006.1708699","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708699","url":null,"abstract":"SystemC language as well as the verification library going with (SCV), provides a rich set of features for dynamic control and parameterization of the constraints applied to a constrained-random stimulus generator. Besides, the property specification language (PSL) offers facilities for gathering and inspecting functional coverage information. This paper examines how SCV stimulus constraints can be modified dynamically using functional PSL coverage data, with the aim of avoiding the redundancy of stimulus within the regression test suite. In so doing we allow reducing simulation runtime needed to meet planned functional coverage","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121224576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708723
N. Nasri, H. Ben Hnia, A. Kachouri, M. Abdellaoui, M. Samet
In order to improve the efficiency multi band OFDM wireless underwater communication, the software technology offers the ability to develop OFDM transceiver architecture and his performance by using an optimal modulation and coding schema. The field programmable gate array (FPGA) represents a solution to have flexible mapping that adjusts several types of modulation. This paper aims to specify a new generic model that supports all modulations required by underwater communication. In order of achieving high-speed data transmission, high data throughputs, and low ratio of errors over many of the underwater channels
{"title":"Modulation/demodulation techniques with FPGA's architecture to improve OFDM wireless underwater communication transceiver","authors":"N. Nasri, H. Ben Hnia, A. Kachouri, M. Abdellaoui, M. Samet","doi":"10.1109/DTIS.2006.1708723","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708723","url":null,"abstract":"In order to improve the efficiency multi band OFDM wireless underwater communication, the software technology offers the ability to develop OFDM transceiver architecture and his performance by using an optimal modulation and coding schema. The field programmable gate array (FPGA) represents a solution to have flexible mapping that adjusts several types of modulation. This paper aims to specify a new generic model that supports all modulations required by underwater communication. In order of achieving high-speed data transmission, high data throughputs, and low ratio of errors over many of the underwater channels","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121274334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708702
W. Zhao, E. Belhaire, V. Javerliac, C. Chappert, B. Dieny
In this paper, the authors propose a non-volatile flip-flop, which presents simultaneously low power dissipation and high speed. This flip-flop is based on MRAM (magnetic RAM) technology on standard CMOS. In this non-volatile flip-flop design, the authors use magnetic tunnel junctions (MTJ) as storage element. Contrary to the complex sense amplifier circuit in standard MRAM circuits, a simple one based on SRAM cell is used to couple with two MTJs per bit in magnetic logic circuit. The flip-flop works exactly as a classical flip-flop hut the information is stored simultaneously in the two MTJs, which makes this flip-flop non-volatile. As the writing frequency has a strong impact on the power consumption, the MTJ writing frequency is designed to be defined by the users depending on different usage. During the startup or reset phase, the flip-flop master stage is used as the MTJ sense amplifier and the flip-flop is initialized to the previously stored state in about 200 ps. This figure has been demonstrated by electrical simulation on a 90 nm CMOS technology and with a complete and precise MTJ model
{"title":"A non-volatile flip-flop in magnetic FPGA chip","authors":"W. Zhao, E. Belhaire, V. Javerliac, C. Chappert, B. Dieny","doi":"10.1109/DTIS.2006.1708702","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708702","url":null,"abstract":"In this paper, the authors propose a non-volatile flip-flop, which presents simultaneously low power dissipation and high speed. This flip-flop is based on MRAM (magnetic RAM) technology on standard CMOS. In this non-volatile flip-flop design, the authors use magnetic tunnel junctions (MTJ) as storage element. Contrary to the complex sense amplifier circuit in standard MRAM circuits, a simple one based on SRAM cell is used to couple with two MTJs per bit in magnetic logic circuit. The flip-flop works exactly as a classical flip-flop hut the information is stored simultaneously in the two MTJs, which makes this flip-flop non-volatile. As the writing frequency has a strong impact on the power consumption, the MTJ writing frequency is designed to be defined by the users depending on different usage. During the startup or reset phase, the flip-flop master stage is used as the MTJ sense amplifier and the flip-flop is initialized to the previously stored state in about 200 ps. This figure has been demonstrated by electrical simulation on a 90 nm CMOS technology and with a complete and precise MTJ model","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133159983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708691
M. Renovell, M. Comte, I. Polian, P. Engelke, B. Becker
This paper analyzes the electrical behaviour of resistive opens as a function of its unpredictable resistance. It is demonstrated that the electrical behaviour depends on the value of the open resistance. It is also shown that, due to the memory effect detection of the open by a given vector Ti depends on all the vectors that have been applied to the circuit before Ti. An electrical analysis of this memory effect is presented
{"title":"Analyzing the memory effect of resistive open in CMOS random logic","authors":"M. Renovell, M. Comte, I. Polian, P. Engelke, B. Becker","doi":"10.1109/DTIS.2006.1708691","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708691","url":null,"abstract":"This paper analyzes the electrical behaviour of resistive opens as a function of its unpredictable resistance. It is demonstrated that the electrical behaviour depends on the value of the open resistance. It is also shown that, due to the memory effect detection of the open by a given vector Ti depends on all the vectors that have been applied to the circuit before Ti. An electrical analysis of this memory effect is presented","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128313945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708656
M. A. Ben Farah, A. Kachouri, M. Samet
Chaos-based communication can be applied advantageously only if the property of chaotic systems is suitably exploited. Chaos communication has been studied for only a little more than a decade while traditional communication schemes have been developed for nearly a century. The hope was (and still is) that for some application chaotic communication will prove to be better than traditional communication. Yet, after one decade of research, in most cases chaos communication did not take the place of traditional communication schemes. As far as communication efficiency is concerned, chaotic communication schemes are typically less efficient than their traditional counterpart. Still, the main advantage of chaotic communication schemes is for analogy implementation of secure communication. In traditional communication schemes data has to be digitized before encryption takes place. This is due to the fact that traditional encryption is based on discrete number theory. In this paper we study the performance of differential chaos shift key (DCSK) modulation and we compare it to BPSK modulation, a new application of DCSK modulation is presented (transmission of the image)
{"title":"Design of secure digital communication systems using DCSK chaotic modulation","authors":"M. A. Ben Farah, A. Kachouri, M. Samet","doi":"10.1109/DTIS.2006.1708656","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708656","url":null,"abstract":"Chaos-based communication can be applied advantageously only if the property of chaotic systems is suitably exploited. Chaos communication has been studied for only a little more than a decade while traditional communication schemes have been developed for nearly a century. The hope was (and still is) that for some application chaotic communication will prove to be better than traditional communication. Yet, after one decade of research, in most cases chaos communication did not take the place of traditional communication schemes. As far as communication efficiency is concerned, chaotic communication schemes are typically less efficient than their traditional counterpart. Still, the main advantage of chaotic communication schemes is for analogy implementation of secure communication. In traditional communication schemes data has to be digitized before encryption takes place. This is due to the fact that traditional encryption is based on discrete number theory. In this paper we study the performance of differential chaos shift key (DCSK) modulation and we compare it to BPSK modulation, a new application of DCSK modulation is presented (transmission of the image)","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123907138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708657
Wenbiao Zhou, Yan Zhang, Zhigang Mao
This paper presents a delay computing-model for a 2D-mesh worm hole based NoC architecture that is a widely used topology structure in NoC design. The model captures the core's message sending probability, packet length and the contention of link in the communication. The different solutions of core's mapping onto NoC architecture will cause different average delay and a genetic algorithm, which is based on the delay model, can automatically provide an approximately optimal mapping lor large scale NoCs. The algorithm aims to achieve a minimum NoC average delay. Experimental results for random traffics and various NoC sizes show that an average approximately 20% reductions in the execution time than random mapping
{"title":"An application specific NoC mapping for optimized delay","authors":"Wenbiao Zhou, Yan Zhang, Zhigang Mao","doi":"10.1109/DTIS.2006.1708657","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708657","url":null,"abstract":"This paper presents a delay computing-model for a 2D-mesh worm hole based NoC architecture that is a widely used topology structure in NoC design. The model captures the core's message sending probability, packet length and the contention of link in the communication. The different solutions of core's mapping onto NoC architecture will cause different average delay and a genetic algorithm, which is based on the delay model, can automatically provide an approximately optimal mapping lor large scale NoCs. The algorithm aims to achieve a minimum NoC average delay. Experimental results for random traffics and various NoC sizes show that an average approximately 20% reductions in the execution time than random mapping","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127564264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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