Pub Date : 2006-05-01DOI: 10.1109/DTIS.2006.1708706
A. Bounceur, S. Mir, E. Simeu, L. Rolíndez
The estimation of test metrics such as defect level, test yield or yield loss is important in order to quantify the quality and cost of a test approach. In the analogue domain, previous works have considered the estimation of these metrics for the case of single faults, either catastrophic or parametric. The consideration of single parametric faults is sensible for a production test technique if the design is robust. However, in the case that production test limits are tight, test escapes resulting from multiple parametric deviations become important. In addition, aging mechanisms result in field failures that are often caused by multiple parametric deviations. In this paper, we present a statistical technique for estimating test metrics for the case of multiple analogue parametric deviations, requiring a Monte Carlo simulation of the circuit under test. This technique assumes Gaussian probability density functions (PDFs) for the parameter and performance deviations but the technique can be adapted to other types of PDFs. We will illustrate the technique for the case of testing a fully differential operational amplifier, proving the validity in the case of this circuit of the Gaussian PDF
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Pub Date : 2005-06-01DOI: 10.1109/DTIS.2006.1708687
H. Mrabet, Z. Marrakchi, H. Mehrez, A. Tissot
Integrating an embedded FPGA into SoC allows post-fabrication changes. Thanks to their unlimited reconfigurability, eFPGAs are able to implement specific functions, thus improves the systems performance. In this paper the authors present an SRAM-based eFPGA architecture. The authors explore the hardware aspects of the eFPGA including internal structure and external coupling with a VCI interconnect. The authors also focus on the design flow for the implementation and the configuration
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Pub Date : 1900-01-01DOI: 10.1109/DTIS.2006.1708685
S. Laurent
Microelectronics components are made with different technological steps which uses dedicated masks: for example, the poly mask is used for the polysilicon deposition on the silicon active area. These masks include the design itself and shapes which are called the mask patterns. These features enable a mechanical isolation during the die sawing and a visual check for each technological step. The mask patterns layout generators are developed by the foundry and used during the layout finishing step of the design. The proposed work gives a validation solution using the Calibre SVRF set of rules and the signature approach already introduced for other applications in ST Design Solutions
{"title":"Physical verification of microelectronics \"mask patterns\" with calibre SVRF rule files","authors":"S. Laurent","doi":"10.1109/DTIS.2006.1708685","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708685","url":null,"abstract":"Microelectronics components are made with different technological steps which uses dedicated masks: for example, the poly mask is used for the polysilicon deposition on the silicon active area. These masks include the design itself and shapes which are called the mask patterns. These features enable a mechanical isolation during the die sawing and a visual check for each technological step. The mask patterns layout generators are developed by the foundry and used during the layout finishing step of the design. The proposed work gives a validation solution using the Calibre SVRF set of rules and the signature approach already introduced for other applications in ST Design Solutions","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133051731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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