Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708676
S. Douss, M. Loulou
The design of multi-standards CMOS mixers is presented in this paper. The front-end is designed to be operational for three standards at the same time: Global System Mobile (GSM), Digital Enhanced Cordless Telephone systems (DECT) and Universal Mobile Telecommunication System (UMTS). The required specifications for those standards are: a noise figure NF < 10dB, a -1dB compression point CP1 < -10dBm and a conversion gain CG > 15dB for a frequency operation up to 2.5 GHz. Three active mixer's structures are presented. The first is based on the Gilbert cell to which is added an output IF stage, a common mode feedback stage, and an isolation stage between the mixer LO and RF input terminals. This structure presents a good linearity and noise figure, but it produces a low conversion gain. The second structure consists in adding two PMOS transistors with the NMOS RF stage transistors in order to increase conversion gain. In the third structure, the authors replaced PMOS transistors by resistive loads. This work is achieved by a figure of merit development, in order to make possible the mixers topology's comparison. According to the developed figure of merit, folded switching mixer (2nd structure) achieves the best performances. With this topology the following simulation results are: noise figure (NF) 7.98 dB, conversion gain 14.8 dB, linearity (CP1) -4 dBm with a power consumption of 30 mW
{"title":"Design of enhanced performances CMOS RF mixers suitable for multi-standards receiver","authors":"S. Douss, M. Loulou","doi":"10.1109/DTIS.2006.1708676","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708676","url":null,"abstract":"The design of multi-standards CMOS mixers is presented in this paper. The front-end is designed to be operational for three standards at the same time: Global System Mobile (GSM), Digital Enhanced Cordless Telephone systems (DECT) and Universal Mobile Telecommunication System (UMTS). The required specifications for those standards are: a noise figure NF < 10dB, a -1dB compression point CP1 < -10dBm and a conversion gain CG > 15dB for a frequency operation up to 2.5 GHz. Three active mixer's structures are presented. The first is based on the Gilbert cell to which is added an output IF stage, a common mode feedback stage, and an isolation stage between the mixer LO and RF input terminals. This structure presents a good linearity and noise figure, but it produces a low conversion gain. The second structure consists in adding two PMOS transistors with the NMOS RF stage transistors in order to increase conversion gain. In the third structure, the authors replaced PMOS transistors by resistive loads. This work is achieved by a figure of merit development, in order to make possible the mixers topology's comparison. According to the developed figure of merit, folded switching mixer (2nd structure) achieves the best performances. With this topology the following simulation results are: noise figure (NF) 7.98 dB, conversion gain 14.8 dB, linearity (CP1) -4 dBm with a power consumption of 30 mW","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122025827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708694
H. Aininzadeh, Mohammad Danaie, R. Lotfi
Considering the importance of settling behavior of an operational amplifier for a given accuracy in many applications such as switched-capacitor circuits, the analysis of single-stage operational amplifiers based on settling time is performed. A simple yet accurate model for the settling response of first-order op amps that modifies the conventional models is presented. The mentioned analysis leads to a new simple settling-based design methodology for single-stage operational amplifiers. Simulation results are presented to show the effectiveness of the proposed model and design methodology
{"title":"A low-power design methodology for single-stage operational amplifiers","authors":"H. Aininzadeh, Mohammad Danaie, R. Lotfi","doi":"10.1109/DTIS.2006.1708694","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708694","url":null,"abstract":"Considering the importance of settling behavior of an operational amplifier for a given accuracy in many applications such as switched-capacitor circuits, the analysis of single-stage operational amplifiers based on settling time is performed. A simple yet accurate model for the settling response of first-order op amps that modifies the conventional models is presented. The mentioned analysis leads to a new simple settling-based design methodology for single-stage operational amplifiers. Simulation results are presented to show the effectiveness of the proposed model and design methodology","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"285 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123914522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708688
B. Mezghani, K. Haboura, Fares Tounsi, S. Smaoui, S. El-Borgi, S. Choura, M. Masmoudi
In this paper, we present theoretical and numerical modeling done on a new structure of CMOS micromachined inductive microphone. Its mode of operation is based on the variation of the mutual inductance between an external fixed inductor and an internal suspended inductor. This internal inductor is designed on a 1.4timesl.4mm2 suspended membrane. The displacement of the suspended membrane with two different attachment structures, the I-shaped and the L-shaped beams, is studied, losing a theoretical mechanical modeling, we get displacement values of 13.11 mum and 68.82 mum, for the I-shaped and L-shaped beam design, respectively. With a numerical FEM analysis, using the Ansys software, displacement values of 12.7 mum and 63.5 mum were found for the I-shaped and L-shaped beam design, respectively. Using the analogy between acoustic, mechanical and electrical domains, the dynamic behavior of the L-shaped beam design sensor is studied and a corner frequency around 200 kHz is found. This value is also found when applying analytical dynamics principles to determine the equations of motion for the suspended membrane. A FEM analysis, using the Ansys software, is conducted in order to validate this theoretical model
{"title":"Theoretical and numerical modeling of a CMOS micromachined acoustic sensor","authors":"B. Mezghani, K. Haboura, Fares Tounsi, S. Smaoui, S. El-Borgi, S. Choura, M. Masmoudi","doi":"10.1109/DTIS.2006.1708688","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708688","url":null,"abstract":"In this paper, we present theoretical and numerical modeling done on a new structure of CMOS micromachined inductive microphone. Its mode of operation is based on the variation of the mutual inductance between an external fixed inductor and an internal suspended inductor. This internal inductor is designed on a 1.4timesl.4mm2 suspended membrane. The displacement of the suspended membrane with two different attachment structures, the I-shaped and the L-shaped beams, is studied, losing a theoretical mechanical modeling, we get displacement values of 13.11 mum and 68.82 mum, for the I-shaped and L-shaped beam design, respectively. With a numerical FEM analysis, using the Ansys software, displacement values of 12.7 mum and 63.5 mum were found for the I-shaped and L-shaped beam design, respectively. Using the analogy between acoustic, mechanical and electrical domains, the dynamic behavior of the L-shaped beam design sensor is studied and a corner frequency around 200 kHz is found. This value is also found when applying analytical dynamics principles to determine the equations of motion for the suspended membrane. A FEM analysis, using the Ansys software, is conducted in order to validate this theoretical model","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"285 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124551983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708650
M. Miranda, A. Papanikolaou, Hua Wang, M. Kaspiris, P. David, F. Catthoor
At nanometer nodes (e.g., 45nm and beyond), stochastic fluctuations on the implemented features and doping levels during the processing of devices is making the electrical parameters of wires and transistors to become more unpredictable, resulting in process variability. Designers cannot neglect the impact of variability on their designs any more, not only during physical design but also during logic synthesis. They need to account for its impact on the timing of the interconnect to make sure that timing closure is achieved and that the design is manufacturable with an acceptable parametric yield. This paper presents a high-level timing model and tool for analyzing typical interconnect circuits accounting for modeling of process variability in the drivers present in the net which is fast enough to be used for Monte-Carlo variability characterization. The approach provides speed-ups between three to four orders of magnitude with very high accuracy when compared to plain SPICE simulation using a 32nn predictive technology model BSIM4 model card
{"title":"A high-level timing model for variability characterization of interconnect circuits","authors":"M. Miranda, A. Papanikolaou, Hua Wang, M. Kaspiris, P. David, F. Catthoor","doi":"10.1109/DTIS.2006.1708650","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708650","url":null,"abstract":"At nanometer nodes (e.g., 45nm and beyond), stochastic fluctuations on the implemented features and doping levels during the processing of devices is making the electrical parameters of wires and transistors to become more unpredictable, resulting in process variability. Designers cannot neglect the impact of variability on their designs any more, not only during physical design but also during logic synthesis. They need to account for its impact on the timing of the interconnect to make sure that timing closure is achieved and that the design is manufacturable with an acceptable parametric yield. This paper presents a high-level timing model and tool for analyzing typical interconnect circuits accounting for modeling of process variability in the drivers present in the net which is fast enough to be used for Monte-Carlo variability characterization. The approach provides speed-ups between three to four orders of magnitude with very high accuracy when compared to plain SPICE simulation using a 32nn predictive technology model BSIM4 model card","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131141550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708651
Anissa Djellid-Ouar, Guy Cathebras, Frédéric Bancel
Among the attacks applied on secure circuits, fault injection techniques consist in the use of a combination of environmental conditions that induce computational errors in the chip that can leak protected informations. The purpose of our study is to build an accurate model able to describe the behaviour of CMOS circuits in presence of deliberated short supply voltage variations. This behaviour depends strongly on the basic gates (combinational logic, registers...) that make up the circuit. In this paper, we show why D-flip-flop are resistant to power supply glitches occurring between clock transitions and we propose an approach to evaluate the basic elements sensitivities towards faults generated by power glitches. Our aimed model will consequently be dependent on this sensitivity
{"title":"Supply voltage glitches effects on CMOS circuits","authors":"Anissa Djellid-Ouar, Guy Cathebras, Frédéric Bancel","doi":"10.1109/DTIS.2006.1708651","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708651","url":null,"abstract":"Among the attacks applied on secure circuits, fault injection techniques consist in the use of a combination of environmental conditions that induce computational errors in the chip that can leak protected informations. The purpose of our study is to build an accurate model able to describe the behaviour of CMOS circuits in presence of deliberated short supply voltage variations. This behaviour depends strongly on the basic gates (combinational logic, registers...) that make up the circuit. In this paper, we show why D-flip-flop are resistant to power supply glitches occurring between clock transitions and we propose an approach to evaluate the basic elements sensitivities towards faults generated by power glitches. Our aimed model will consequently be dependent on this sensitivity","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128990012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708707
Jacques-Olivier Klein, E. Belhaire, C. Chappert, R. Cowburn, D. Read, D. Petit
The demonstration of NOT and OR logic gates using magnetic domain walls could suggest that digital circuit design methodology may apply directly to this new technology to build complex circuits. In this paper, the authors show that the use of an external rotating field which propagates domain walls of opposite magnetization at different times, reveals unforeseen delays which modify the operation of sequential logic circuits. To overcome this difficulty, the authors present a new device capable of re-synchronizing the signals
{"title":"Magnetic domain wall logic requires new synthesis methodologies","authors":"Jacques-Olivier Klein, E. Belhaire, C. Chappert, R. Cowburn, D. Read, D. Petit","doi":"10.1109/DTIS.2006.1708707","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708707","url":null,"abstract":"The demonstration of NOT and OR logic gates using magnetic domain walls could suggest that digital circuit design methodology may apply directly to this new technology to build complex circuits. In this paper, the authors show that the use of an external rotating field which propagates domain walls of opposite magnetization at different times, reveals unforeseen delays which modify the operation of sequential logic circuits. To overcome this difficulty, the authors present a new device capable of re-synchronizing the signals","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"30 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114045812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708733
C. Maneux, J. Goguet, S. Frégonèse, T. Zimmer, H. C. d’Honincthun, S. Galdin-Retailleau
On the basis of acquired knowledge, the paper present a DC compact model designed for the conventional CNTFET (C-CNTFET) featuring a doping profile similar to n-MOSFET. The specific enhancement lies on the implementation of a physical based calculation of the minima of energy conduction subbands. This improvement allows a realistic analysis of the impact of CNT helicity and radius on the DC characteristics. The purpose is to enable the circuit designers to challenge CNTFET potentialities for performing logical or analogical functionalities within complex circuits
{"title":"Analysis of CNTFET physical compact model","authors":"C. Maneux, J. Goguet, S. Frégonèse, T. Zimmer, H. C. d’Honincthun, S. Galdin-Retailleau","doi":"10.1109/DTIS.2006.1708733","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708733","url":null,"abstract":"On the basis of acquired knowledge, the paper present a DC compact model designed for the conventional CNTFET (C-CNTFET) featuring a doping profile similar to n-MOSFET. The specific enhancement lies on the implementation of a physical based calculation of the minima of energy conduction subbands. This improvement allows a realistic analysis of the impact of CNT helicity and radius on the DC characteristics. The purpose is to enable the circuit designers to challenge CNTFET potentialities for performing logical or analogical functionalities within complex circuits","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126240456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708728
N. Khouja, K. Grati, A. Ghazel
In this work a low power solution is provided for the implementation of decimation filter for multistandard wireless receiver. The reduced switching activity and low power dissipation are achieved through the reduction of the energy wasted by the clocking of storage units on every cycle. This technique known as the "clock gating" allows enabling the clock only when a load to a register is required. This also serves to "turn off" parts of the design by holding the clock steady during inactive periods. Analysis showed that by reducing switching activity in the overall system power consumption is reduced by about 23% compared to the same architecture where no clock gating is used
{"title":"Low power FPGA-based implementation of decimating filters for multistandard receiver","authors":"N. Khouja, K. Grati, A. Ghazel","doi":"10.1109/DTIS.2006.1708728","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708728","url":null,"abstract":"In this work a low power solution is provided for the implementation of decimation filter for multistandard wireless receiver. The reduced switching activity and low power dissipation are achieved through the reduction of the energy wasted by the clocking of storage units on every cycle. This technique known as the \"clock gating\" allows enabling the clock only when a load to a register is required. This also serves to \"turn off\" parts of the design by holding the clock steady during inactive periods. Analysis showed that by reducing switching activity in the overall system power consumption is reduced by about 23% compared to the same architecture where no clock gating is used","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125821429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708652
P. Vanhairoaert, R. Leveugle, P. Roche
Prototyping-based fault injection environments are employed to perform dependability analysis and thus predict the behavior of circuits in presence of faults. A novel environment has been recently proposed to perform several types of dependability analyses in a common optimized framework. The approach takes advantage of hardware speed and of software flexibility to achieve optimized trade-offs between experiment duration and processing complexity. This paper discusses the possible repartition of tasks between hardware and embedded software with respect to the type of circuit to analyze and to the instrumentation achieved. The performances of the approach are evaluated for each configuration of the environment
{"title":"Dependability analysis: performance evaluation of environment configurations","authors":"P. Vanhairoaert, R. Leveugle, P. Roche","doi":"10.1109/DTIS.2006.1708652","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708652","url":null,"abstract":"Prototyping-based fault injection environments are employed to perform dependability analysis and thus predict the behavior of circuits in presence of faults. A novel environment has been recently proposed to perform several types of dependability analyses in a common optimized framework. The approach takes advantage of hardware speed and of software flexibility to achieve optimized trade-offs between experiment duration and processing complexity. This paper discusses the possible repartition of tasks between hardware and embedded software with respect to the type of circuit to analyze and to the instrumentation achieved. The performances of the approach are evaluated for each configuration of the environment","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127667428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708719
S. Kamel, L. Bennour, A. Baganne, R. Tourki, A. Jemai
Among factors limiting the reuse of intellectual property (IPs) blocks into wide range of systems on chips (SoCs) is the inflexibility of their communication protocols. This paper presents an approach for designing IP blocks with relaxed timing constraints to exchange data with various environments. The approach is based on decoupling computation from communication and on an adequate scheduling of operations during the high level synthesis of computation units. Experimentations performed on the MPEG4 intraprediction IP block show the efficiency of our solution
{"title":"Behavioral synthesis technique for flexible IP's communications","authors":"S. Kamel, L. Bennour, A. Baganne, R. Tourki, A. Jemai","doi":"10.1109/DTIS.2006.1708719","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708719","url":null,"abstract":"Among factors limiting the reuse of intellectual property (IPs) blocks into wide range of systems on chips (SoCs) is the inflexibility of their communication protocols. This paper presents an approach for designing IP blocks with relaxed timing constraints to exchange data with various environments. The approach is based on decoupling computation from communication and on an adequate scheduling of operations during the high level synthesis of computation units. Experimentations performed on the MPEG4 intraprediction IP block show the efficiency of our solution","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"301 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132967384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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