Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708697
F. Martorell, A. Rubio
Several nanoelectronic devices have been already proved. However, no architecture which makes use of them provides a feasible opportunity to build a medium/large system. Nanoarchitecture proposals only solve a small part or the problems needed to achieve a real design. In this paper we review the two main approaches to nanoarchitectures showing some of their shortcomings. Taking into account these limitations, we propose and analyze a cell architecture that overcomes most of them. This architecture combines nanodevices with MOS technology to define a new architecture able to take advantage of both of them in a structure feasible for practical implementation. Using the cell structure we build 2 and 3-input NAND gates showing their error probabilities. Finally, we outline a method to further improve the structure's tolerance by taking advantage of interferences among nanodevices
{"title":"Defect and fault tolerant cell architecture for feasible nanoelectronic designs","authors":"F. Martorell, A. Rubio","doi":"10.1109/DTIS.2006.1708697","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708697","url":null,"abstract":"Several nanoelectronic devices have been already proved. However, no architecture which makes use of them provides a feasible opportunity to build a medium/large system. Nanoarchitecture proposals only solve a small part or the problems needed to achieve a real design. In this paper we review the two main approaches to nanoarchitectures showing some of their shortcomings. Taking into account these limitations, we propose and analyze a cell architecture that overcomes most of them. This architecture combines nanodevices with MOS technology to define a new architecture able to take advantage of both of them in a structure feasible for practical implementation. Using the cell structure we build 2 and 3-input NAND gates showing their error probabilities. Finally, we outline a method to further improve the structure's tolerance by taking advantage of interferences among nanodevices","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133963656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708673
S. Ben Salem, D. Sellami Masmoudi, M. Fakhfakh, M. Loulou, N. Masmoudi
In this paper, high frequency CCII based oscillators and multifunction filters are presented. A system level investigation of these configurations characteristics and CCII nonidealities effects are done. The authors emphasize the fact that the proposed applications are well suited for integration since their characteristics can be tuned by simple action on their bias current. Implementations of these topologies based on an improved high frequency translinear CCII were done. The oscillator has a variable oscillation frequency tunable in the range [333 MHz-867MHz] by varying a dc current between 50muA and 400muA. Moreover, two based current mode and voltage mode multifunction filters were implemented. The current mode filter has a tunable natural frequency in the range [512MHz-1GHz] and the voltage mode filter is also implemented having a natural frequency equal to 100MHz
{"title":"High frequency CCII based oscillators and multifunction filters","authors":"S. Ben Salem, D. Sellami Masmoudi, M. Fakhfakh, M. Loulou, N. Masmoudi","doi":"10.1109/DTIS.2006.1708673","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708673","url":null,"abstract":"In this paper, high frequency CCII based oscillators and multifunction filters are presented. A system level investigation of these configurations characteristics and CCII nonidealities effects are done. The authors emphasize the fact that the proposed applications are well suited for integration since their characteristics can be tuned by simple action on their bias current. Implementations of these topologies based on an improved high frequency translinear CCII were done. The oscillator has a variable oscillation frequency tunable in the range [333 MHz-867MHz] by varying a dc current between 50muA and 400muA. Moreover, two based current mode and voltage mode multifunction filters were implemented. The current mode filter has a tunable natural frequency in the range [512MHz-1GHz] and the voltage mode filter is also implemented having a natural frequency equal to 100MHz","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115813276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708731
T. Dang, L. Anghel, R. Leveugle
This paper provides an overview of current types of CNTFETs and of some compact models. Using the available models, the influence of the parameters on the device characteristics was simulated and analyzed. The conclusion is that the tube diameter influences not only the current level, but also the threshold voltage of the CNTFET, while the contact resistance influences only the current level. From a designer's point of view, taking care of the parameter variations and in particular of the nanotube diameters is crucial to achieve reliable circuits
{"title":"CNTFET basics and simulation","authors":"T. Dang, L. Anghel, R. Leveugle","doi":"10.1109/DTIS.2006.1708731","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708731","url":null,"abstract":"This paper provides an overview of current types of CNTFETs and of some compact models. Using the available models, the influence of the parameters on the device characteristics was simulated and analyzed. The conclusion is that the tube diameter influences not only the current level, but also the threshold voltage of the CNTFET, while the contact resistance influences only the current level. From a designer's point of view, taking care of the parameter variations and in particular of the nanotube diameters is crucial to achieve reliable circuits","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123632841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708727
T. Finateu, J. Bégueret, Y. Deval, F. Badets
In this paper a new concept of RF transmitter dedicated to low-power low-voltage applications using injection locked oscillator is described. A 2-GHz injection locked oscillator was implemented in a 0.35 mum BiCMOS STMicroelectronics technology in order to validate the theoretical results of the GMSK modulation of such oscillators
本文介绍了一种采用注入锁定振荡器的低功率低压射频发射机的新概念。为了验证2 ghz注入锁定振荡器GMSK调制的理论结果，采用0.35 μ m BiCMOS意法半导体技术实现了2 ghz注入锁定振荡器
{"title":"Injection locked oscillator based RF transmitters","authors":"T. Finateu, J. Bégueret, Y. Deval, F. Badets","doi":"10.1109/DTIS.2006.1708727","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708727","url":null,"abstract":"In this paper a new concept of RF transmitter dedicated to low-power low-voltage applications using injection locked oscillator is described. A 2-GHz injection locked oscillator was implemented in a 0.35 mum BiCMOS STMicroelectronics technology in order to validate the theoretical results of the GMSK modulation of such oscillators","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121799979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708693
N. Badereddine, P. Girard, S. Pravossoudovitch, C. Landrault, A. Virazel, H. Wunderlich
Scan architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we discuss the issues of excessive peak power consumption during scan testing. We show that taking care of high current levels during the test cycle (i.e. between launch and capture) is highly relevant to avoid noise phenomena such as IR-drop or ground bounce. We propose a solution based on power-aware assignment of don't care bits in deterministic test patterns. For ISCAS'89 and ITC'99 benchmark circuits, this approach reduces peak power during the test cycle up to 89% compared to a random filling solution
{"title":"Minimizing peak power consumption during scan testing: test pattern modification with X filling heuristics","authors":"N. Badereddine, P. Girard, S. Pravossoudovitch, C. Landrault, A. Virazel, H. Wunderlich","doi":"10.1109/DTIS.2006.1708693","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708693","url":null,"abstract":"Scan architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we discuss the issues of excessive peak power consumption during scan testing. We show that taking care of high current levels during the test cycle (i.e. between launch and capture) is highly relevant to avoid noise phenomena such as IR-drop or ground bounce. We propose a solution based on power-aware assignment of don't care bits in deterministic test patterns. For ISCAS'89 and ITC'99 benchmark circuits, this approach reduces peak power during the test cycle up to 89% compared to a random filling solution","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134094196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708732
F. Prégaldiny, C. Lallement, J. Kammerer
This paper deals with the compact modeling of an emerging technology: the carbon nanotube field-effect transistor (CNTFET). The paper proposed two design-oriented compact models, the first one for CNTFET with a classical behavior (MOSFET-like CNTFET), and the second one for CNTFET with an ambipolar behavior (Schottky-barrier CNTFET). Both models have been compared with exact numerical simulations and then implemented in VHDL-AMS
{"title":"Design-oriented compact models for CNTFETs","authors":"F. Prégaldiny, C. Lallement, J. Kammerer","doi":"10.1109/DTIS.2006.1708732","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708732","url":null,"abstract":"This paper deals with the compact modeling of an emerging technology: the carbon nanotube field-effect transistor (CNTFET). The paper proposed two design-oriented compact models, the first one for CNTFET with a classical behavior (MOSFET-like CNTFET), and the second one for CNTFET with an ambipolar behavior (Schottky-barrier CNTFET). Both models have been compared with exact numerical simulations and then implemented in VHDL-AMS","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":" 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113949193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708653
F. Dadouche, A. Pinna, P. Ganfla, A. Alexamlr
The design of mixed signal systems on chip is in a continuous growth these last few years. So the technical progress for systems integration allows the implementation of millions of active or passive pixel sensors (APS or PPS) on a same chip in order to define image matrix (system on chip). It has become crucial for the design of these systems to accurately predict their behavior prior to manufacture. Now the emergence of standard description languages as VHDL-AMS offers an effective and efficient way to describe these multiple domain and mixed-signal electronic systems. The aim of this work is the modeling of pixel sensors (APS and PPS), basic cells of CMOS image systems. Pixel sensors are composed of photodetectors for photogeneration of current and photocircuit for conversion and/or pre amplification of this current. PPS are usually associated to an operational amplifier (OPA). So in this paper the authors present models for each one of these parts and we instantiate them to simulate PPS and APS cells
{"title":"Modeling of pixel sensors for image systems with VHDL-AMS","authors":"F. Dadouche, A. Pinna, P. Ganfla, A. Alexamlr","doi":"10.1109/DTIS.2006.1708653","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708653","url":null,"abstract":"The design of mixed signal systems on chip is in a continuous growth these last few years. So the technical progress for systems integration allows the implementation of millions of active or passive pixel sensors (APS or PPS) on a same chip in order to define image matrix (system on chip). It has become crucial for the design of these systems to accurately predict their behavior prior to manufacture. Now the emergence of standard description languages as VHDL-AMS offers an effective and efficient way to describe these multiple domain and mixed-signal electronic systems. The aim of this work is the modeling of pixel sensors (APS and PPS), basic cells of CMOS image systems. Pixel sensors are composed of photodetectors for photogeneration of current and photocircuit for conversion and/or pre amplification of this current. PPS are usually associated to an operational amplifier (OPA). So in this paper the authors present models for each one of these parts and we instantiate them to simulate PPS and APS cells","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114251510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708670
K. Taniguchi, H. Fujii, S. Kajihara, X. Wen
In this paper, we propose a method to speed-up fault simulation. The proposed method takes a hybrid approach with compiled simulation and event-driven simulation. Compiled simulation is applied for fan-out free regions (FFRs). FFRs to be simulated are selected with the event-driven manner. Since the event-driven simulation contributes to avoidance of waste simulation and the compiled simulation contributes to reduction of memory access, the proposed method can reduce the simulation time effectively. Note that this work targets on combinational circuits or a full-scan sequential circuit, and the single stuck-at fault model is assumed. Experimental results for benchmark circuits show that the proposed method could reduce runtime in half compared with concurrent (event-driven) fault simulation
{"title":"Hybrid fault simulation with compiled and event-driven methods","authors":"K. Taniguchi, H. Fujii, S. Kajihara, X. Wen","doi":"10.1109/DTIS.2006.1708670","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708670","url":null,"abstract":"In this paper, we propose a method to speed-up fault simulation. The proposed method takes a hybrid approach with compiled simulation and event-driven simulation. Compiled simulation is applied for fan-out free regions (FFRs). FFRs to be simulated are selected with the event-driven manner. Since the event-driven simulation contributes to avoidance of waste simulation and the compiled simulation contributes to reduction of memory access, the proposed method can reduce the simulation time effectively. Note that this work targets on combinational circuits or a full-scan sequential circuit, and the single stuck-at fault model is assumed. Experimental results for benchmark circuits show that the proposed method could reduce runtime in half compared with concurrent (event-driven) fault simulation","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"20 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134500246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708721
O. Ginez, J. Daga, P. Girard, C. Landrault, Serge, Pravossoudovitch, A. Virazel
The evolution of system-on-chip (SoC) designs involves the development of non-volatile memory technologies like flash. Embedded flash (eFlash) memories are based on the floating-gate transistor concept and can be subject to complex hard defects creating functional faults. In this paper, we present a complete analysis of a particular failure mechanism, referred as disturb phenomenon. Moreover, we analyze the efficiency of a particular test sequence to detect this disturb phenomenon. Finally we conclude on the interest to develop new test infrastructure well adapted to the eFlash environment
{"title":"Embedded flash testing: overview and perspectives","authors":"O. Ginez, J. Daga, P. Girard, C. Landrault, Serge, Pravossoudovitch, A. Virazel","doi":"10.1109/DTIS.2006.1708721","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708721","url":null,"abstract":"The evolution of system-on-chip (SoC) designs involves the development of non-volatile memory technologies like flash. Embedded flash (eFlash) memories are based on the floating-gate transistor concept and can be subject to complex hard defects creating functional faults. In this paper, we present a complete analysis of a particular failure mechanism, referred as disturb phenomenon. Moreover, we analyze the efficiency of a particular test sequence to detect this disturb phenomenon. Finally we conclude on the interest to develop new test infrastructure well adapted to the eFlash environment","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121975286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708662
R. Barrak, Adel Ghazel, F. Ghannouchi
This paper presents an improved sampling-based down conversion topology design with double RF filters for multi-standard RF subsampling receiver. Proposed architecture is limiting down conversion to IF domain and adding a first tunable RF filter to select multistandard RF bands. To overcome subsampling negative effects on receiver performances a second RF filter is inserted before subsampling operation to perform anti-aliasing and limit wide band noise. RF filters design methodology and ADS simulation results are presented for GSM, UMTS and IEEE-802.11g standards. Good performance improvement is obtained with reduced complexity architecture and circuits
{"title":"Design and optimisation of RF filters for multistandard RF sub-sampling receiver","authors":"R. Barrak, Adel Ghazel, F. Ghannouchi","doi":"10.1109/DTIS.2006.1708662","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708662","url":null,"abstract":"This paper presents an improved sampling-based down conversion topology design with double RF filters for multi-standard RF subsampling receiver. Proposed architecture is limiting down conversion to IF domain and adding a first tunable RF filter to select multistandard RF bands. To overcome subsampling negative effects on receiver performances a second RF filter is inserted before subsampling operation to perform anti-aliasing and limit wide band noise. RF filters design methodology and ADS simulation results are presented for GSM, UMTS and IEEE-802.11g standards. Good performance improvement is obtained with reduced complexity architecture and circuits","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125059296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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