Igor Krause, Leandro Poloni Dantas, Salvador Pinillos Gimenez
Abstract—This work studies the impact in the parallel processing of the Interlocked-Hardware-Microkernel (IHM) Plasma microprocessor (IHM-Plasma) by implementing the Earliest-Deadline-First (EDF) algorithm by hardware in the task-scheduler block that belongs to those task-based operational systems, such as that related to the real-time operational systems (RTOS). IHM-Plasma presents Reduced Instruction Set Computer (RISC) architecture. The main results have observed by this study show that the IHM-Plasma running the EDF algorithm by hardware has increased the tasks executed per second in 174% while running a task-based operational system with 14 active tasks in comparison to the original Plasma running the EDF algorithm by software. The developed work has great potential use in Hard Real-Time Systems and others where a rigid control of deadlines is essential and hold many tasks.
{"title":"Impact in the Parallel Processing of IHM-Plasma Using the Earliest-Deadline-First Algorithm for the Task-Scheduler Realized by Hardware","authors":"Igor Krause, Leandro Poloni Dantas, Salvador Pinillos Gimenez","doi":"10.29292/jics.v18i1.576","DOIUrl":"https://doi.org/10.29292/jics.v18i1.576","url":null,"abstract":"Abstract—This work studies the impact in the parallel processing of the Interlocked-Hardware-Microkernel (IHM) Plasma microprocessor (IHM-Plasma) by implementing the Earliest-Deadline-First (EDF) algorithm by hardware in the task-scheduler block that belongs to those task-based operational systems, such as that related to the real-time operational systems (RTOS). IHM-Plasma presents Reduced Instruction Set Computer (RISC) architecture. The main results have observed by this study show that the IHM-Plasma running the EDF algorithm by hardware has increased the tasks executed per second in 174% while running a task-based operational system with 14 active tasks in comparison to the original Plasma running the EDF algorithm by software. The developed work has great potential use in Hard Real-Time Systems and others where a rigid control of deadlines is essential and hold many tasks. ","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44832935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Roberta Palau, Wagner Penny, Ramiro Viana, J. Goebel, G. Corrêa, M. Porto, L. Agostini
This paper presents a high-throughput hardware design for the Switchable Loop Restoration Filter (SLRF) of the AOM Video 1 (AV1) video format. This hardware includes the two filters defined at the AV1 SLRF: the Separable Symmetric Normalized Wiener Filter (SSNWF) and the Dual Self- Guided Filter (DSGF). The SLRF is the last step in the AV1 loop restoration filters, and it is used to attenuate blurring artifacts, improving the subjective video quality and the coding efficiency. The designed hardware targeted the AV1 decoderand is able to process up to 4K Ultra-High Definition (4K UHD) videos (with 3840x2160 pixels) at 60 frames per second (fps) in real-time. In order to cover different scenarios, two other target throughputs were also evaluated: 4K UHD at 30fps and Full HD (FHD) (with 1920x1080 pixels) at 30fps. The architectures were synthesized for standard cells using the 40 nm TSMC library. The SSNWF and DSGF architectures used 37.38 Kgates and 177.58 kgates in all evaluated scenarios. Depending on the evaluated scenario, the SSNWF power dissipation varied from 8.25mWto 26.95mWand the DSGF power varied from 57.19 mW to 115.02 mW. This is the first paper in the literature presenting a hardware design for the AV1 SLRF with its two filters.
{"title":"High-Throughput Hardware Design for the AV1 Decoder Switchable Loop Restoration Filters","authors":"Roberta Palau, Wagner Penny, Ramiro Viana, J. Goebel, G. Corrêa, M. Porto, L. Agostini","doi":"10.29292/jics.v18i1.667","DOIUrl":"https://doi.org/10.29292/jics.v18i1.667","url":null,"abstract":"This paper presents a high-throughput hardware design for the Switchable Loop Restoration Filter (SLRF) of the AOM Video 1 (AV1) video format. This hardware includes the two filters defined at the AV1 SLRF: the Separable Symmetric Normalized Wiener Filter (SSNWF) and the Dual Self- Guided Filter (DSGF). The SLRF is the last step in the AV1 loop restoration filters, and it is used to attenuate blurring artifacts, improving the subjective video quality and the coding efficiency. The designed hardware targeted the AV1 decoderand is able to process up to 4K Ultra-High Definition (4K UHD) videos (with 3840x2160 pixels) at 60 frames per second (fps) in real-time. In order to cover different scenarios, two other target throughputs were also evaluated: 4K UHD at 30fps and Full HD (FHD) (with 1920x1080 pixels) at 30fps. The architectures were synthesized for standard cells using the 40 nm TSMC library. The SSNWF and DSGF architectures used 37.38 Kgates and 177.58 kgates in all evaluated scenarios. Depending on the evaluated scenario, the SSNWF power dissipation varied from 8.25mWto 26.95mWand the DSGF power varied from 57.19 mW to 115.02 mW. This is the first paper in the literature presenting a hardware design for the AV1 SLRF with its two filters.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44457252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Fontana, R. Netto, S. Almeida, Erfan Aghaeekiasaraee, L. Behjat, José Luís Almada Güntzel
Due to the complexity of contemporary circuits, physical synthesis has become a crucial step for achieving design closure. The placement of cells direct impacts the routing solution. For example, a region with a high cell density can lead to pin access issues in detailed routing. Therefore, small inefficiencies in the placement solution can be boosted during routing, which has a negative impact on design quality and convergence. Unfortunately, most academic research works evaluate the results only in the target step without considering the complete place and route flows. In this work, we experimentally explored different flows built up from academic placers and routers to find which one leads to the best overall results so that researchers can use them as a reference. In order to evaluate those flows, we used the ISPD 2018 and ISPD 2019 CAD Contest benchmarks, which are the most realistic academic benchmarks available with placement and routing information. Considering the evaluator reports, no combination of tools achieved the best result for all circuits. Nevertheless, the flow Contest placement + CUGR + TritonRoute achieved the best results in fifteen out of twenty benchmarks.
{"title":"Towards a Reference Place and Route Flow for Academic Research","authors":"T. Fontana, R. Netto, S. Almeida, Erfan Aghaeekiasaraee, L. Behjat, José Luís Almada Güntzel","doi":"10.29292/jics.v17i3.648","DOIUrl":"https://doi.org/10.29292/jics.v17i3.648","url":null,"abstract":"Due to the complexity of contemporary circuits, physical synthesis has become a crucial step for achieving design closure. The placement of cells direct impacts the routing solution. For example, a region with a high cell density can lead to pin access issues in detailed routing. Therefore, small inefficiencies in the placement solution can be boosted during routing, which has a negative impact on design quality and convergence. Unfortunately, most academic research works evaluate the results only in the target step without considering the complete place and route flows. In this work, we experimentally explored different flows built up from academic placers and routers to find which one leads to the best overall results so that researchers can use them as a reference. In order to evaluate those flows, we used the ISPD 2018 and ISPD 2019 CAD Contest benchmarks, which are the most realistic academic benchmarks available with placement and routing information. Considering the evaluator reports, no combination of tools achieved the best result for all circuits. Nevertheless, the flow Contest placement + CUGR + TritonRoute achieved the best results in fifteen out of twenty benchmarks.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48312871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The development of any integrated circuit depends heavily on the quality of the EDA (Electronic Design Automation) tools used in the design flow. Improved CAD tools and algo-rithms are needed to cope with new fabrication technology requirements, advanced performance constraints, or simply the enormous number of elements involved. In this paper it is giving an overview of the importance of automation in the design process, and it is done a survey of different types of tools presenting some classifications of the tools. Then some few trends on EDA that are needed to deal with the evolution of manufacturing processes will be presented. Some optimi-zation techniques will be presented for selected physical de-sign problems (layout). An important aspect of the design is to reduce power consumption at all levels of abstraction. Power optimization is fundamental in nanoCMOS and in the IoT world. At logic and physical levels, one approach that can be used to optimize the circuit, especially reducing static leakage power and using the automatic generation of the cell layout. With on-the-fly cell generation, the same function can be implemented with a reduced number of transistors, requiring less area and significantly optimizing power and performance. Finally, the use of estimation and visualiza-tion tools is equally important. They can be applied either in the design flow or in the tool's development and research en-vironments as a way to observe and understand the behavior and interactions of algorithms and their operation on real designs and benchmarks.
{"title":"EDA: Overview and Some Trends","authors":"R. da Luz Reis","doi":"10.29292/jics.v17i3.679","DOIUrl":"https://doi.org/10.29292/jics.v17i3.679","url":null,"abstract":"The development of any integrated circuit depends heavily on the quality of the EDA (Electronic Design Automation) tools used in the design flow. Improved CAD tools and algo-rithms are needed to cope with new fabrication technology requirements, advanced performance constraints, or simply the enormous number of elements involved. In this paper it is giving an overview of the importance of automation in the design process, and it is done a survey of different types of tools presenting some classifications of the tools. Then some few trends on EDA that are needed to deal with the evolution of manufacturing processes will be presented. Some optimi-zation techniques will be presented for selected physical de-sign problems (layout). An important aspect of the design is to reduce power consumption at all levels of abstraction. Power optimization is fundamental in nanoCMOS and in the IoT world. At logic and physical levels, one approach that can be used to optimize the circuit, especially reducing static leakage power and using the automatic generation of the cell layout. With on-the-fly cell generation, the same function can be implemented with a reduced number of transistors, requiring less area and significantly optimizing power and performance. Finally, the use of estimation and visualiza-tion tools is equally important. They can be applied either in the design flow or in the tool's development and research en-vironments as a way to observe and understand the behavior and interactions of algorithms and their operation on real designs and benchmarks.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45885063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper largely focuses on enhancing device parameters of a Double Gate Tunnel Field Effect Transistor structure such as ON current, OFF Current,transconductance and ratio of ON current to OFF current (ION / IOFF) using hetero dielectric gate material. The paper presents three state of art of dual gate TFET i.e., Conventional Double Gate TFET (CDGTFET), horizontally placed Dual Material Double Gate TFET (HDMDGTFET), vertically placed Dual Material Double Gate TFET (VDMDGTFET). The dual material dielectric combinations used in the structures are (SiO2-TiO2), (HfO2-TiO2) and (SiO2-SiC). The Structures are being modeled using Silvaco Atlas tool. Simulations of these structures are carried out and various electrical parameters have been obtained. The results obtained from simulation of these structures are being presented and discussed in this paper. Comparison of the three structures is carried out and resulted in the reduction of ON Current and OFF Current is observed.
{"title":"Qualitative Analysis of DG-TFET Structures with Gate Material Engineering","authors":"B. Balaji, Sadhu Satya Sravani, K. Srinivasa Rao","doi":"10.29292/jics.v17i3.635","DOIUrl":"https://doi.org/10.29292/jics.v17i3.635","url":null,"abstract":"The paper largely focuses on enhancing device parameters of a Double Gate Tunnel Field Effect Transistor structure such as ON current, OFF Current,transconductance and ratio of ON current to OFF current (ION / IOFF) using hetero dielectric gate material. The paper presents three state of art of dual gate TFET i.e., Conventional Double Gate TFET (CDGTFET), horizontally placed Dual Material Double Gate TFET (HDMDGTFET), vertically placed Dual Material Double Gate TFET (VDMDGTFET). The dual material dielectric combinations used in the structures are (SiO2-TiO2), (HfO2-TiO2) and (SiO2-SiC). The Structures are being modeled using Silvaco Atlas tool. Simulations of these structures are carried out and various electrical parameters have been obtained. The results obtained from simulation of these structures are being presented and discussed in this paper. Comparison of the three structures is carried out and resulted in the reduction of ON Current and OFF Current is observed.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46165917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. G. Junior, Jeverson Cardoso da Silva, E. Martins, Maria Glória Caño De Andrade
Abstract— For the first time, Ultra-Thin Body and Buried Oxide Fully Depleted Silicon-On-Insulator (UTBB FDSOI) n-channel with Dynamic Threshold MOS configuration (DTMOS) using the SELBOX (Selective Buried OXide) substrate will be analyzed. The drain and substrate current, transconductance (gm) and Subthreshold Slope (SS) will be compared in the DTMOS mode and the standard biasing configuration for different gap width (WGAP) of SELBOX. Additionally, the output conductance and the transconductance gain also studied through numerical simulations. The results indicate that the SELBOX structure in DTMOS mode is competitive candidates for analog applications.
{"title":"UTBB FD-SOI MOSFET with SELBOX in DTMOS Configuration","authors":"N. G. Junior, Jeverson Cardoso da Silva, E. Martins, Maria Glória Caño De Andrade","doi":"10.29292/jics.v17i3.641","DOIUrl":"https://doi.org/10.29292/jics.v17i3.641","url":null,"abstract":"Abstract— For the first time, Ultra-Thin Body and Buried Oxide Fully Depleted Silicon-On-Insulator (UTBB FDSOI) n-channel with Dynamic Threshold MOS configuration (DTMOS) using the SELBOX (Selective Buried OXide) substrate will be analyzed. The drain and substrate current, transconductance (gm) and Subthreshold Slope (SS) will be compared in the DTMOS mode and the standard biasing configuration for different gap width (WGAP) of SELBOX. Additionally, the output conductance and the transconductance gain also studied through numerical simulations. The results indicate that the SELBOX structure in DTMOS mode is competitive candidates for analog applications.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43101460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Electronic Design Automation has been the driving force of VLSI design since those circuits are far more complex beyond what a human designer can comprehend. Today, the most advanced circuits have billions of components, mostly transistors, arranged in random logic, memory, data path, analog, mixed signal, IPs, etc. The process of automation of a large VLSI chip is extremely complex, generally decomposed into several categories and steps that are part of most existing commercial tool flows. Furthermore, timing and power optimization enable a wide range of applications we see today such as computing, mobile, internet of things (IoT), etc., and can only happen with creative innovations in EDA. For its complexity, any researcher in the field must invest heavily in finding and reading appropriate literature. In this special edition, the Journal of Integrated Circuits and Systems is collecting and surveying the key topics, algorithms and approaches that pertain to the current state-of-the-art in EDA research.
{"title":"Guest Editors' Words","authors":"R. Hentschke, C. Meinhardt","doi":"10.29292/jics.v17i3.681","DOIUrl":"https://doi.org/10.29292/jics.v17i3.681","url":null,"abstract":"Electronic Design Automation has been the driving force of VLSI design since those circuits are far more complex beyond what a human designer can comprehend. Today, the most advanced circuits have billions of components, mostly transistors, arranged in random logic, memory, data path, analog, mixed signal, IPs, etc. The process of automation of a large VLSI chip is extremely complex, generally decomposed into several categories and steps that are part of most existing commercial tool flows. Furthermore, timing and power optimization enable a wide range of applications we see today such as computing, mobile, internet of things (IoT), etc., and can only happen with creative innovations in EDA. For its complexity, any researcher in the field must invest heavily in finding and reading appropriate literature. In this special edition, the Journal of Integrated Circuits and Systems is collecting and surveying the key topics, algorithms and approaches that pertain to the current state-of-the-art in EDA research.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42739249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
José Roberto Banin Júnior, Rodrigo Alves de Lima Moreto, G. A. da Silva, Salvador Pinillos Gimenez
Analog designers usually cascade several basic analog building blocks that were previously optimized to increase the open-loop voltage gain (AV0) and to avoid the increasing of the Design and Optimization Cycle Time (DOCT) of a given System-On-a-Chip. However, still exist a big doubt about if this approach is really better than that considering the implementation of amplifiers in cascade, without considering previously optimized analog building blocks. Thus, the main objective of this paper is to perform a detailed comparative study between robust amplifiers in cascade implemented without using analog building blocks previously designed and optimized and a similar one that uses analog building blocks previously designed and optimized (typical design approach). The computational design and optimization tool, named iMTGSPICE, which uses heuristics algorithms of the Artificial Intelligence integrated to the expertise of the analog designers (Human Intelligence), is used to perform these implementations to remarkably reduce DOCT of these implementations. This work demonstrates that it is possible to reduce the total gate area (44.6%) and to increase the operating temperature range from 0oC to 36oC to -40oC to 125oC of the robust amplifier in cascade that was implemented without using analog building blocks previously designed and optimized compared to one that was implemented by using analog building blocks previously designed and optimized.
{"title":"Using iMTGSPICE to Optimize Cascaded Miller OTAs and Boost Electrical Performance, Robustness and Reduce Die Area","authors":"José Roberto Banin Júnior, Rodrigo Alves de Lima Moreto, G. A. da Silva, Salvador Pinillos Gimenez","doi":"10.29292/jics.v17i3.672","DOIUrl":"https://doi.org/10.29292/jics.v17i3.672","url":null,"abstract":"Analog designers usually cascade several basic analog building blocks that were previously optimized to increase the open-loop voltage gain (AV0) and to avoid the increasing of the Design and Optimization Cycle Time (DOCT) of a given System-On-a-Chip. However, still exist a big doubt about if this approach is really better than that considering the implementation of amplifiers in cascade, without considering previously optimized analog building blocks. Thus, the main objective of this paper is to perform a detailed comparative study between robust amplifiers in cascade implemented without using analog building blocks previously designed and optimized and a similar one that uses analog building blocks previously designed and optimized (typical design approach). The computational design and optimization tool, named iMTGSPICE, which uses heuristics algorithms of the Artificial Intelligence integrated to the expertise of the analog designers (Human Intelligence), is used to perform these implementations to remarkably reduce DOCT of these implementations. This work demonstrates that it is possible to reduce the total gate area (44.6%) and to increase the operating temperature range from 0oC to 36oC to -40oC to 125oC of the robust amplifier in cascade that was implemented without using analog building blocks previously designed and optimized compared to one that was implemented by using analog building blocks previously designed and optimized.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":"92 3","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41330864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Omar Paranaiba, Poliana A. C. Oliveira, Renan A. Marks, Gabriel Novy, Maria D. Vieira, Laysson Oliveira Luz, P. A. Silva, Ricardo Ferreira, J. Ramirez, J. Nacif, Guilherme Caporali
After the continuous development of CMOS technology driven by transistor miniaturization and Moore’s law, the scientific community is witnessing the exploration of emerging paradigms to find new ways to develop computational systems. This paper presents critical concepts for understanding some of these new nanocomputing technologies, specifically field-coupled, quantum-dot cellular automata, nanomagnetic logic, silicon dangling bounds, photonic crystal logic, and DNA computing. Next, it shows emerging design automation tools for each of these areas and how they can be applied to support the development of new computing systems. The level of maturity and production speed of solutions achieved by conventional silicon technology thanks to very efficient electronic design automation (EDA) is remarkable. However, here we are dealing with technologies still in their infancy. Therefore, improvements in design automation tools are undoubtedly a way to accelerate the growth of new substrate alternatives and modern applications.
{"title":"Design Automation for Emerging Technologies","authors":"Omar Paranaiba, Poliana A. C. Oliveira, Renan A. Marks, Gabriel Novy, Maria D. Vieira, Laysson Oliveira Luz, P. A. Silva, Ricardo Ferreira, J. Ramirez, J. Nacif, Guilherme Caporali","doi":"10.29292/jics.v17i3.652","DOIUrl":"https://doi.org/10.29292/jics.v17i3.652","url":null,"abstract":"After the continuous development of CMOS technology driven by transistor miniaturization and Moore’s law, the scientific community is witnessing the exploration of emerging paradigms to find new ways to develop computational systems. This paper presents critical concepts for understanding some of these new nanocomputing technologies, specifically field-coupled, quantum-dot cellular automata, nanomagnetic logic, silicon dangling bounds, photonic crystal logic, and DNA computing. Next, it shows emerging design automation tools for each of these areas and how they can be applied to support the development of new computing systems. The level of maturity and production speed of solutions achieved by conventional silicon technology thanks to very efficient electronic design automation (EDA) is remarkable. However, here we are dealing with technologies still in their infancy. Therefore, improvements in design automation tools are undoubtedly a way to accelerate the growth of new substrate alternatives and modern applications.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44829810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In VLSI manufacturing, certain steps such as Chemical Mechanical Polishing (CMP) could affect the functioning of the chip thereby affecting yield. The fill flow adds additional metal and via features to the layout so that the density of metal and vias are uniform across the layout. When metal and vias are uniformly spread across the layout, the side effects of the chemical mechanical polishing step are minimized because variation in polishing depth is minimized. Since the fill process involves addition of metal and via features to the finished layout, this could affect critical layout metrics such as timing. Therefore, it is best if the layout synthesis flow i.e. the place and route flow is made fill-aware to improve performance predictability and enable faster layout convergence. In this paper, we provide a brief overview of the fill problem, algorithms to analyze density and fill synthesis.
{"title":"An Introduction to Metal and Via Fill","authors":"K. Ramkumar","doi":"10.29292/jics.v17i3.673","DOIUrl":"https://doi.org/10.29292/jics.v17i3.673","url":null,"abstract":"In VLSI manufacturing, certain steps such as Chemical Mechanical Polishing (CMP) could affect the functioning of the chip thereby affecting yield. The fill flow adds additional metal and via features to the layout so that the density of metal and vias are uniform across the layout. When metal and vias are uniformly spread across the layout, the side effects of the chemical mechanical polishing step are minimized because variation in polishing depth is minimized. Since the fill process involves addition of metal and via features to the finished layout, this could affect critical layout metrics such as timing. Therefore, it is best if the layout synthesis flow i.e. the place and route flow is made fill-aware to improve performance predictability and enable faster layout convergence. In this paper, we provide a brief overview of the fill problem, algorithms to analyze density and fill synthesis.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45149187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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