Michel Santana de Deus, Sebastian Yuri Cavalcanti Catunda, Antônio Wallace Antunes Soares, Diomadson Rodrigues Belfort
Variable and programmable gain amplifiers have been a recurrent subject of study over the last 50 years, and, are increasingly used in different applications today. This work presents an overview of these amplifiers as to serve as an up-to-date source of information for studies and designs. Different architectures and techniques are presented and classified for both radio and intermediate frequencies, since there are major differences in the requirements according to bandwidth. Typical applications where VGAs and PGAs are employed are also presented.
{"title":"Review on Variable and Programmable Gain Amplifiers and Applications","authors":"Michel Santana de Deus, Sebastian Yuri Cavalcanti Catunda, Antônio Wallace Antunes Soares, Diomadson Rodrigues Belfort","doi":"10.29292/jics.v17i1.583","DOIUrl":"https://doi.org/10.29292/jics.v17i1.583","url":null,"abstract":"Variable and programmable gain amplifiers have been a recurrent subject of study over the last 50 years, and, are increasingly used in different applications today. This work presents an overview of these amplifiers as to serve as an up-to-date source of information for studies and designs. Different architectures and techniques are presented and classified for both radio and intermediate frequencies, since there are major differences in the requirements according to bandwidth. Typical applications where VGAs and PGAs are employed are also presented.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44651110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rodrigo Aparecido da Silva Braga, Paulo M. Moreira e Silva, Dean Bicudo Karolak
Operational Transconductance Amplifiers (OTAs) are essential building blocks in analog circuits. Since the early years of integrated circuit science, OTAs have been used in industry and researched in academia. Over the years, a number of techniques and approaches to OTA design have been observed in the literature. With this systematic review, we aim to provide a overview of top journal papers published from 2017 to 2021 containing OTA design. In our investigation we initially found 128 manuscripts and 24 primary studies of OTA design. A set of 10 different techniques have been found. Furthermore, we also evaluate used technology, inversion level and characterization process. With this study we contribute to highlight recent OTA design innovations.
{"title":"Are CMOS Operational Transconductance Amplifiers Old Fashioned? A Systematic Review","authors":"Rodrigo Aparecido da Silva Braga, Paulo M. Moreira e Silva, Dean Bicudo Karolak","doi":"10.29292/jics.v17i1.574","DOIUrl":"https://doi.org/10.29292/jics.v17i1.574","url":null,"abstract":"Operational Transconductance Amplifiers (OTAs) are essential building blocks in analog circuits. Since the early years of integrated circuit science, OTAs have been used in industry and researched in academia. Over the years, a number of techniques and approaches to OTA design have been observed in the literature. With this systematic review, we aim to provide a overview of top journal papers published from 2017 to 2021 containing OTA design. In our investigation we initially found 128 manuscripts and 24 primary studies of OTA design. A set of 10 different techniques have been found. Furthermore, we also evaluate used technology, inversion level and characterization process. With this study we contribute to highlight recent OTA design innovations.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41633311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Alexander Aponte-Moreno, Felipe Restrepo-Calle, C. Pedraza
Approximate Computing techniques have been successfully used to reduce the overhead associated with redundancy in fault-tolerant system designs. This paper presents a fault tolerance method to reduce the execution time overhead of the well-known Time Redundancy technique by means of an improvement proposed for the Approximate Computing software-based technique known as loop perforation. Time Redundancy is a software-based fault tolerance technique that involves executing replicas of a task at different times. We propose to approximate the tasks to be executed using a new approximate computing technique based on loop perforation, i.e., simplified iterations. The novelty of this method is the combined use of the fault tolerance technique, temporal redundancy, jointly with the new proposed Approximate Computing technique, simplified iterations. The proposal is validated through simulation-based fault injection campaigns on several test programs for the ARM and RISC-V microprocessor architectures. Experimental results verified not only the applicability of the proposal in different architectures, but also its effectiveness, showing a good trade-off between reliability, error and overhead. Results showed that using the proposed method, a normalized mean work to failure (MWTF) up to 5.28× was obtained with approximation errors lower than those obtained using the traditional loop perforation technique.
{"title":"A Low-cost Fault Tolerance Method for ARM and RISC-V Microprocessor-based Systems using Temporal Redundancy and Approximate Computing through Simplified Iterations","authors":"Alexander Aponte-Moreno, Felipe Restrepo-Calle, C. Pedraza","doi":"10.29292/jics.v16i3.539","DOIUrl":"https://doi.org/10.29292/jics.v16i3.539","url":null,"abstract":"Approximate Computing techniques have been successfully used to reduce the overhead associated with redundancy in fault-tolerant system designs. This paper presents a fault tolerance method to reduce the execution time overhead of the well-known Time Redundancy technique by means of an improvement proposed for the Approximate Computing software-based technique known as loop perforation. Time Redundancy is a software-based fault tolerance technique that involves executing replicas of a task at different times. We propose to approximate the tasks to be executed using a new approximate computing technique based on loop perforation, i.e., simplified iterations. The novelty of this method is the combined use of the fault tolerance technique, temporal redundancy, jointly with the new proposed Approximate Computing technique, simplified iterations. The proposal is validated through simulation-based fault injection campaigns on several test programs for the ARM and RISC-V microprocessor architectures. Experimental results verified not only the applicability of the proposal in different architectures, but also its effectiveness, showing a good trade-off between reliability, error and overhead. Results showed that using the proposed method, a normalized mean work to failure (MWTF) up to 5.28× was obtained with approximation errors lower than those obtained using the traditional loop perforation technique.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47368076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, the use of the Adaptive Neuro Fuzzy Inference System (ANFIS) to model the CMOS inverter is discussed as a tool for developing and simulating CMOS logic circuits at the ultradeep submicron technology node of 22nm. The ANFIS structures are built and trained using MATLAB software. The ANFIS network was trained using data obtained from the analytical model (at 298.15K and 398.15K). For training, two methodologies are used: a hybrid learning method based on back-propagation and least-squares estimation, and back-propagation. The effect of the ANFIS model's structure on the accuracy and performance of the CMOS inverter has also been investigated. Further, simulation through HSPICE using (Predictive Technology Model) PTM nominal parameters has been done to compare with ANFIS (trained using an analytical model) results. The comparison of ANFIS and HSPICE suggests the ANFIS modelling procedure's practicality and correctness. The findings demonstrate that the ANFIS simulation is significantly faster and more comparable than the HSPICE simulation and that it can be easily integrated into software tools for designing and simulating complicated CMOS logic circuits.
{"title":"ANFIS Based Thermal Estimation of Ultradeep Submicron Digital Circuit Design","authors":"Ruby Beniwal, Shruti Kalra","doi":"10.29292/jics.v16i3.507","DOIUrl":"https://doi.org/10.29292/jics.v16i3.507","url":null,"abstract":"In this paper, the use of the Adaptive Neuro Fuzzy Inference System (ANFIS) to model the CMOS inverter is discussed as a tool for developing and simulating CMOS logic circuits at the ultradeep submicron technology node of 22nm. The ANFIS structures are built and trained using MATLAB software. The ANFIS network was trained using data obtained from the analytical model (at 298.15K and 398.15K). For training, two methodologies are used: a hybrid learning method based on back-propagation and least-squares estimation, and back-propagation. The effect of the ANFIS model's structure on the accuracy and performance of the CMOS inverter has also been investigated. Further, simulation through HSPICE using (Predictive Technology Model) PTM nominal parameters has been done to compare with ANFIS (trained using an analytical model) results. The comparison of ANFIS and HSPICE suggests the ANFIS modelling procedure's practicality and correctness. The findings demonstrate that the ANFIS simulation is significantly faster and more comparable than the HSPICE simulation and that it can be easily integrated into software tools for designing and simulating complicated CMOS logic circuits.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45163123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This Special Issues brings four invited papers that describe the state of the art techniques to improve fault tolerance on complex designs. Integrated circuits operating under radiation can experience undesirable faults that must be evaluated and mitigated. Mitigation can be implemented by redundancy in hardware or in software, and by selecting and protecting the most critical parts of the system. Radiation effects test and analysis also play an important step in identifying the criticality of the system and helping designers to better apply fault mitigation techniques.
{"title":"Guest Editors' Words","authors":"Fernanda Lima Kastensmidt, S. C. Asensi","doi":"10.29292/jics.v16i3.575","DOIUrl":"https://doi.org/10.29292/jics.v16i3.575","url":null,"abstract":"This Special Issues brings four invited papers that describe the state of the art techniques to improve fault tolerance on complex designs. Integrated circuits operating under radiation can experience undesirable faults that must be evaluated and mitigated. Mitigation can be implemented by redundancy in hardware or in software, and by selecting and protecting the most critical parts of the system. Radiation effects test and analysis also play an important step in identifying the criticality of the system and helping designers to better apply fault mitigation techniques.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-02-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48332641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. C. Vilas Bôas, Saulo Gabriel Alberton, Nilberto H. Medina, Vitor Ângelo Paulino, Marco Antonio Assis Melo, Roberto Baginski Santos, R. Giacomini, T. Cavalcante, Rafael Galhardo Vaz, E. Junior, L. Seixas, S. Finco, M. Guazzelli
In this work, measurements were taken to investigate the robustness of a GaN HEMT to TID by a 60CO Source. These results will be compared with a previous X-ray based work. The robustness was investigated through IxV curves and characteristic parameters of the irradiated device. The analysis included data acquired both from on- and off- state modes. The work concludes that the device is robust to TID, as it quickly recovered important parameters. Mainly, the on-state mode, which presented a better performance compared to the off-mode. An analogous behavior was seen for X-ray. Finally, the VTH values due to the TID, in this device is independent of the dose rate and the radiation source.
{"title":"Reliability analysis of gamma- and X-ray TID effects, on a commercial AlGaN/GaN based FET","authors":"A. C. Vilas Bôas, Saulo Gabriel Alberton, Nilberto H. Medina, Vitor Ângelo Paulino, Marco Antonio Assis Melo, Roberto Baginski Santos, R. Giacomini, T. Cavalcante, Rafael Galhardo Vaz, E. Junior, L. Seixas, S. Finco, M. Guazzelli","doi":"10.29292/jics.v16i3.566","DOIUrl":"https://doi.org/10.29292/jics.v16i3.566","url":null,"abstract":"In this work, measurements were taken to investigate the robustness of a GaN HEMT to TID by a 60CO Source. These results will be compared with a previous X-ray based work. The robustness was investigated through IxV curves and characteristic parameters of the irradiated device. The analysis included data acquired both from on- and off- state modes. The work concludes that the device is robust to TID, as it quickly recovered important parameters. Mainly, the on-state mode, which presented a better performance compared to the off-mode. An analogous behavior was seen for X-ray. Finally, the VTH values due to the TID, in this device is independent of the dose rate and the radiation source. ","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43450217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sima Honarmand, M. Pourahmadi, M. Shayesteh, K. Abbasi
This article discusses a multi-stage transimpedance amplifier (TIA), which is based on three stages of a modified inverter structure. The traditional inverter structures’ performances are improved adding two cascoded transistors. This new structure benefits from elimination of the Miller-capacitances in comparison with the traditional inverters, which can provide higher speed and wider frequency bandwidth. Manipulating the trade-offs among bandwidth, gain and power consumption beside using Gm/ID technique, this paper introduces a low-power transimpedance amplifier for high-bit rates in optical communication receiver systems. Moreover, active types of inductors are also used to lesson the occupied area and increase the frequency bandwidth. Transferring poles of the improved circuit to higher frequencies means less required DC current for a fixed bandwidth range, which results in low-power characteristic.
{"title":"A Multi-Stage TIA based on Cascoded-Inverter Structures for Low-power Applications","authors":"Sima Honarmand, M. Pourahmadi, M. Shayesteh, K. Abbasi","doi":"10.29292/jics.v16i3.520","DOIUrl":"https://doi.org/10.29292/jics.v16i3.520","url":null,"abstract":"This article discusses a multi-stage transimpedance amplifier (TIA), which is based on three stages of a modified inverter structure. The traditional inverter structures’ performances are improved adding two cascoded transistors. This new structure benefits from elimination of the Miller-capacitances in comparison with the traditional inverters, which can provide higher speed and wider frequency bandwidth. Manipulating the trade-offs among bandwidth, gain and power consumption beside using Gm/ID technique, this paper introduces a low-power transimpedance amplifier for high-bit rates in optical communication receiver systems. Moreover, active types of inductors are also used to lesson the occupied area and increase the frequency bandwidth. Transferring poles of the improved circuit to higher frequencies means less required DC current for a fixed bandwidth range, which results in low-power characteristic.\u0000 ","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42886560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sreeteja Reddy Kotha, Karuppanan P, A. K. Gautam, Manmath Suryavanshi
This article employs a nested state feedback compensation technique to a three-stage bulk-driven operational transconductance amplifier (OTA). The projected OTA circuit consists of a bulk-driven PMOS amplifier, gate-driven NMOS amplifier, and common source (CS) amplifier. The entire transistors in the amplifier core are configuredwith self-cascode transistor topology to increase its output impedance. All transistors are designed to operate in a weak inversion in order to dissipate less power. Cross-coupled transistor pair topology in the bulk-driven stage allows to improve the effective transconductance of OTA. The CS amplifier can drive a large load capacitor. The polarities and transconductance gains of feedback blocks are controlled appropriately to obtain the desired DC gain and bandwidth. The capacitor-less compensation strategy allows the fabrication of the OTA using the minimum area. Conventional bulk-driven miler OTA, Bulk-driven stage improved indirect-feedback OTA (BSIF OTA), Gate-driven stage added bulk-driven OTA (GSIF OTA), and proposed bulk-driven OTA topologies are designed and simulated using cadence spectre tool at 25 mV supply voltage in the 65nm CMOS process. These OTA circuits are analyzed and compared in terms of parameters like DC gain, unity-gain frequency, phase margin, CMRR, power dissipated, slew rate, and input referred noise.
{"title":"A 0.25-V Three-stage State Feedback Bulk-driven OTA for Wide Range Load Applications","authors":"Sreeteja Reddy Kotha, Karuppanan P, A. K. Gautam, Manmath Suryavanshi","doi":"10.29292/jics.v16i3.498","DOIUrl":"https://doi.org/10.29292/jics.v16i3.498","url":null,"abstract":"This article employs a nested state feedback compensation technique to a three-stage bulk-driven operational transconductance amplifier (OTA). The projected OTA circuit consists of a bulk-driven PMOS amplifier, gate-driven NMOS amplifier, and common source (CS) amplifier. The entire transistors in the amplifier core are configuredwith self-cascode transistor topology to increase its output impedance. All transistors are designed to operate in a weak inversion in order to dissipate less power. Cross-coupled transistor pair topology in the bulk-driven stage allows to improve the effective transconductance of OTA. The CS amplifier can drive a large load capacitor. The polarities and transconductance gains of feedback blocks are controlled appropriately to obtain the desired DC gain and bandwidth. The capacitor-less compensation strategy allows the fabrication of the OTA using the minimum area. Conventional bulk-driven miler OTA, Bulk-driven stage improved indirect-feedback OTA (BSIF OTA), Gate-driven stage added bulk-driven OTA (GSIF OTA), and proposed bulk-driven OTA topologies are designed and simulated using cadence spectre tool at 25 mV supply voltage in the 65nm CMOS process. These OTA circuits are analyzed and compared in terms of parameters like DC gain, unity-gain frequency, phase margin, CMRR, power dissipated, slew rate, and input referred noise.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46606760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Matheus Ferreira Pontes, Clayton R. Farias, R. Schvittz, P. Butzen, Leomar Da Rosa Jr.
The aggressive technology scaling has significantly affected the circuit reliability. The interaction of environmental radiation with the devices in the integrated circuits (ICs) may be the dominant reliability aspect of advanced ICs. Several techniques have been explored to mitigate the radiation effects and guarantee a satisfactory reliability levels. In this context, estimating circuit radiation reliability is crucial and a challenge that has not yet been overcome. For decades, several different methods have been proposed to provide circuit reliability. Recently, the radiation effects have been more faithfully incorporated in these strategies to provide the circuit susceptibility more accurately. This paper overviews the current trend for estimating the radiation reliability of digital circuits. The survey divides the approaches into two abstraction levels: (i) gate-level that incorporate the layout information and (ii) circuit-level that traditionally explore the logic circuit characteristic to provide the radiation susceptibility of combinational circuits. We also present an open-source tool that incorporates several previously explored methods. Finally, the actual research aspects are discussed, providing the newly emerging topic, such as selective hardening and critical vector identification.
{"title":"Survey on Reliability Estimation in Digital Circuits","authors":"Matheus Ferreira Pontes, Clayton R. Farias, R. Schvittz, P. Butzen, Leomar Da Rosa Jr.","doi":"10.29292/jics.v16i3.568","DOIUrl":"https://doi.org/10.29292/jics.v16i3.568","url":null,"abstract":"The aggressive technology scaling has significantly affected the circuit reliability. The interaction of environmental radiation with the devices in the integrated circuits (ICs) may be the dominant reliability aspect of advanced ICs. Several techniques have been explored to mitigate the radiation effects and guarantee a satisfactory reliability levels. In this context, estimating circuit radiation reliability is crucial and a challenge that has not yet been overcome. For decades, several different methods have been proposed to provide circuit reliability. Recently, the radiation effects have been more faithfully incorporated in these strategies to provide the circuit susceptibility more accurately. This paper overviews the current trend for estimating the radiation reliability of digital circuits. The survey divides the approaches into two abstraction levels: (i) gate-level that incorporate the layout information and (ii) circuit-level that traditionally explore the logic circuit characteristic to provide the radiation susceptibility of combinational circuits. We also present an open-source tool that incorporates several previously explored methods. Finally, the actual research aspects are discussed, providing the newly emerging topic, such as selective hardening and critical vector identification.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42914166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Hernández, I. Garduño, A. Cerdeira, B. Iñíguez, M. Estrada
In this paper, we report the effects of thermal annealing on Poly(methyl methacrylate) (PMMA) passivated, bottom gate thin film transistors, with amorphous hafnium oxide (HfO2) as gate dielectric and amorphous hafnium-indium-zinc oxide (a-HIZO) as semiconductor, fabricated at temperatures below 200 oC. It is shown that TFTs, with VTH =0.55 V, mFE>250 cm2/Vs, SS=200 mV/dec corresponding to Dit= 1x1012 cm-2eV-1 and Ion/Ioff>107, can be obtained, using a thermal annealing at 200 oC in N2, after the semiconductor layer is deposited. The dielectric constant of the HfO2 layer deposited by RF sputtering was 19.5, allowing devices to work within the operating voltage range of 2 V. An important increase of the field effect mobility is obtained, combining a high-k gate dielectric and a high carrier concentration a-HIZO layer, with a lower density of localized states.
{"title":"Effects of Thermal Annealing on the Density of States in Low Voltage Operating Range, High Mobility, Hf-In-ZnO/HfO2 TFTs Fabricated at Temperatures below 200 oC","authors":"I. Hernández, I. Garduño, A. Cerdeira, B. Iñíguez, M. Estrada","doi":"10.29292/jics.v16i3.561","DOIUrl":"https://doi.org/10.29292/jics.v16i3.561","url":null,"abstract":"In this paper, we report the effects of thermal annealing on Poly(methyl methacrylate) (PMMA) passivated, bottom gate thin film transistors, with amorphous hafnium oxide (HfO2) as gate dielectric and amorphous hafnium-indium-zinc oxide (a-HIZO) as semiconductor, fabricated at temperatures below 200 oC. It is shown that TFTs, with VTH =0.55 V, mFE>250 cm2/Vs, SS=200 mV/dec corresponding to Dit= 1x1012 cm-2eV-1 and Ion/Ioff>107, can be obtained, using a thermal annealing at 200 oC in N2, after the semiconductor layer is deposited. The dielectric constant of the HfO2 layer deposited by RF sputtering was 19.5, allowing devices to work within the operating voltage range of 2 V. An important increase of the field effect mobility is obtained, combining a high-k gate dielectric and a high carrier concentration a-HIZO layer, with a lower density of localized states.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46986108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：