In the current research work, we focused on the design and analysis of a semiconductor device called High-Elec-tron-Mobility Transistor (HEMT) based on the AlGaN/GaN material system. An Aluminum Nitride spacer,Layer of Nucle-ation along with cap as a AlGaN and barrier of GaN with the channel of AlGaN are incorporated to enhance HEMT device performance.The electrical characteristics of the proposed HEMT are an-alyzed. The Drain Current is found to be 0.18A/mm, indicating the device's ability to handle high current levels. The Electron Concentration is observed to have a maximum value of -96.12electrons/cm3 and varying based on the position in the channel for GaN Barrier thickness is 0.15mm. In the analysis of AC such as Gain of the Maximum Unilateral Power is deter-mined to be 83.41dB, indicating the ability of the device to am-plify signals. The Y-parameters, which characterize the de-vice's behavior at various frequencies of operation, are also de-termined. The capacitance between the electrode region Gate-Source (CGSMIN) is found to be 1.70×10^-11 F/mm, and alike The Capacitance between the electrode region the Gate-Drain Ca-pacitance (CGDMIN) is determined to be 4.7×10^-12 F/mm. Fur-thermore, an Electric Field of 96.51×10^3 V/mm is observed, in-dicating the strength of the electric field across the device. For HEMT device the simulation,The TCAD Silvaco software is be-ing practiced.
{"title":"Improvement of AlGaN/ GaN based HEMT with high performance rate for integrated circuit design for wide range of applications","authors":"Swati Dhondiram Jadhav, Aboo Bakar Khan","doi":"10.29292/jics.v19i1.747","DOIUrl":"https://doi.org/10.29292/jics.v19i1.747","url":null,"abstract":"In the current research work, we focused on the design and analysis of a semiconductor device called High-Elec-tron-Mobility Transistor (HEMT) based on the AlGaN/GaN material system. An Aluminum Nitride spacer,Layer of Nucle-ation along with cap as a AlGaN and barrier of GaN with the channel of AlGaN are incorporated to enhance HEMT device performance.The electrical characteristics of the proposed HEMT are an-alyzed. The Drain Current is found to be 0.18A/mm, indicating the device's ability to handle high current levels. The Electron Concentration is observed to have a maximum value of -96.12electrons/cm3 and varying based on the position in the channel for GaN Barrier thickness is 0.15mm. In the analysis of AC such as Gain of the Maximum Unilateral Power is deter-mined to be 83.41dB, indicating the ability of the device to am-plify signals. The Y-parameters, which characterize the de-vice's behavior at various frequencies of operation, are also de-termined. The capacitance between the electrode region Gate-Source (CGSMIN) is found to be 1.70×10^-11 F/mm, and alike The Capacitance between the electrode region the Gate-Drain Ca-pacitance (CGDMIN) is determined to be 4.7×10^-12 F/mm. Fur-thermore, an Electric Field of 96.51×10^3 V/mm is observed, in-dicating the strength of the electric field across the device. For HEMT device the simulation,The TCAD Silvaco software is be-ing practiced.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" 23","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140392256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Ortiz-Conde, V. C. P. Silva, Anabela Veloso, P. Agopian, Simoen Eddy, Joao A. Martino, F. García-Sánchez
We present a critical assessment and discussion of the presence of parasitic source-and-drain series resistance and normal electric field-dependent mobility degradation in undoped Si nanosheet MOSFETs. A simple explicit Lambert W function-based closed-form model, continuously valid from sub-threshold to strong conduction, was used to clearly describe the transfer characteristics. The model was applied to experimental vertically stacked GAA undoped Si nanosheet MOSFETs using phenomenon-related model parameter values extracted from measured data through suitable numerical optimization procedures. The conducted analysis reveals and explains how these two effects produce analogous deleterious consequences on these devices’ transfer characteristics.
{"title":"Parameter extraction using the transfer characteristics of vertically stacked Si nanosheet MOSFETs","authors":"A. Ortiz-Conde, V. C. P. Silva, Anabela Veloso, P. Agopian, Simoen Eddy, Joao A. Martino, F. García-Sánchez","doi":"10.29292/jics.v19i1.801","DOIUrl":"https://doi.org/10.29292/jics.v19i1.801","url":null,"abstract":"We present a critical assessment and discussion of the presence of parasitic source-and-drain series resistance and normal electric field-dependent mobility degradation in undoped Si nanosheet MOSFETs. A simple explicit Lambert W function-based closed-form model, continuously valid from sub-threshold to strong conduction, was used to clearly describe the transfer characteristics. The model was applied to experimental vertically stacked GAA undoped Si nanosheet MOSFETs using phenomenon-related model parameter values extracted from measured data through suitable numerical optimization procedures. The conducted analysis reveals and explains how these two effects produce analogous deleterious consequences on these devices’ transfer characteristics.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" 54","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140391751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mainak Mukherjee, Niloy Ghosh, Papiya Debnath, A. Sarkar, M. Chanda
In this research work, Hetero-structure Junction-less MOSFET having a Silicon-Germanium source and high-k inner corner spacer is proposed and investigated. In this article, we have shown that the introduction of a high-k dielectric material in the inner corner spacer and a low-k dielectric material in the rest of the spacer in the optimally designed device leads to a substantial reduction in parasitic capacitances, resulting in higher operating speed. It was also shown that proper doping in the drain-source underlaps regime, can improve the short channel performance (SCP) of the device by increasing the effective gate length. The optimally designed proposed device produces on current (ION) ~0.33 mA and off current (IOFF) ~ 5.55 fA along with ION/IOFF=6.08x1010, Subthreshold slope (SS)=59.6 mV/decade and drain induced barrier lowering (DIBL)=82.2 mV/V. This paper also highlights the performance improvement of the proposed device in terms of both speed and energy consumption, as compared to that of Junctionless Double Gate MOSFET when implemented as logic gates.
在这项研究工作中，我们提出并研究了具有硅锗源和高 K 内角间隔物的异质结构无结 MOSFET。在这篇文章中，我们证明了在优化设计的器件中，在内角隔板中引入高 k 电介质材料，而在隔板的其余部分中引入低 k 电介质材料，可大幅降低寄生电容，从而提高工作速度。研究还表明，在漏极-源极欠压状态下适当掺杂，可以通过增加有效栅极长度来改善器件的短沟道性能（SCP）。经过优化设计的器件可产生约 0.33 mA 的导通电流（ION）和约 5.55 fA 的关断电流（IOFF），ION/IOFF=6.08x1010，次阈值斜率（SS）=59.6 mV/decade，漏极诱导势垒降低（DIBL）=82.2 mV/V。本文还着重介绍了与作为逻辑门实现的无结双栅 MOSFET 相比，所提器件在速度和能耗方面的性能改进。
{"title":"Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications","authors":"Mainak Mukherjee, Niloy Ghosh, Papiya Debnath, A. Sarkar, M. Chanda","doi":"10.29292/jics.v19i1.796","DOIUrl":"https://doi.org/10.29292/jics.v19i1.796","url":null,"abstract":"In this research work, Hetero-structure Junction-less MOSFET having a Silicon-Germanium source and high-k inner corner spacer is proposed and investigated. In this article, we have shown that the introduction of a high-k dielectric material in the inner corner spacer and a low-k dielectric material in the rest of the spacer in the optimally designed device leads to a substantial reduction in parasitic capacitances, resulting in higher operating speed. It was also shown that proper doping in the drain-source underlaps regime, can improve the short channel performance (SCP) of the device by increasing the effective gate length. The optimally designed proposed device produces on current (ION) ~0.33 mA and off current (IOFF) ~ 5.55 fA along with ION/IOFF=6.08x1010, Subthreshold slope (SS)=59.6 mV/decade and drain induced barrier lowering (DIBL)=82.2 mV/V. This paper also highlights the performance improvement of the proposed device in terms of both speed and energy consumption, as compared to that of Junctionless Double Gate MOSFET when implemented as logic gates.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" 30","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140391493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Aloke Saha, Sudeshna Dutta, Snigdha Dutta, Osman Hossain Siddique, Rimpa Dey, Anup Kumar Das
Carrying more information makes the ternary-computation effective in order to reduce the interconnect complexity and hence, ternary computer can be the future alternative to conventional (binary) counterpart. As a consequence the ternary arithmetic has become the centre of choice among circuit/system researcher in recent time. Ternary adder/subtractor is the integral part of Ternary Arithmetic Logic Unit (TALU) and the 3’s complement is used to represent negative ternary number in TALU. This work proposes a new two-step low hardware-cost strategy to converts ternary input into its 3’s complement output. Novel hardware optimization using normal process Enhancement-type Metal Oxide Semiconductor (E-MOS)-transistor is explored and exploited to design proposed 4-trit 3’s complement generator on 32nm standard CMOS technology with 0.9V supply-rail at 27°C temperature using typical MOS-transistor. Unbalanced ternary digit “0”, “1” and “2” are denoted with ground, supply/2 and supply respectively. The T-Spice transient simulations with all possible test patterns validate the working of proposed circuit and the corresponding speed-power characteristic is compared with most recent counterpart. The circuit performance is also evaluated with different load condition. The 4-trit 3’s complement circuit is extended next to propose 16-trit 3’s complement generator and the impact of Process and Environmental variation on the proposed circuit is studied.
{"title":"Efficient 3’s Complement Circuit for Ternary-ALU","authors":"Aloke Saha, Sudeshna Dutta, Snigdha Dutta, Osman Hossain Siddique, Rimpa Dey, Anup Kumar Das","doi":"10.29292/jics.v19i1.750","DOIUrl":"https://doi.org/10.29292/jics.v19i1.750","url":null,"abstract":"Carrying more information makes the ternary-computation effective in order to reduce the interconnect complexity and hence, ternary computer can be the future alternative to conventional (binary) counterpart. As a consequence the ternary arithmetic has become the centre of choice among circuit/system researcher in recent time. Ternary adder/subtractor is the integral part of Ternary Arithmetic Logic Unit (TALU) and the 3’s complement is used to represent negative ternary number in TALU. This work proposes a new two-step low hardware-cost strategy to converts ternary input into its 3’s complement output. Novel hardware optimization using normal process Enhancement-type Metal Oxide Semiconductor (E-MOS)-transistor is explored and exploited to design proposed 4-trit 3’s complement generator on 32nm standard CMOS technology with 0.9V supply-rail at 27°C temperature using typical MOS-transistor. Unbalanced ternary digit “0”, “1” and “2” are denoted with ground, supply/2 and supply respectively. The T-Spice transient simulations with all possible test patterns validate the working of proposed circuit and the corresponding speed-power characteristic is compared with most recent counterpart. The circuit performance is also evaluated with different load condition. The 4-trit 3’s complement circuit is extended next to propose 16-trit 3’s complement generator and the impact of Process and Environmental variation on the proposed circuit is studied.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" 2","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140391914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Diego Mattos, Vitoria Monteiro, P. D. de Aguirre, Lucas Severo, Alessandro Girardi
Photovoltaic (PV) cells are being adopted as a viable and cost-effective option for implementing receivers within Visible Light Communication (VLC) systems, primarily in indoor environments. Accurately estimating the generated current and voltage of the PV cell based on incident light is crucial when designing VLC systems.For this assessment, the 1D2R electrical equivalent model, which incorporates a diode and two resistors, is employed.In AC small signal analysis, the diode is substituted by its dynamic counterpart, which comprises a dynamic resistance in parallel with an equivalent capacitance. This study introduces an approach to measure and characterize the small-signal parameters of a PV cell operating at the maximum power point (MPP), open circuit (OC), and short circuit (SC) bias points. This is achieved through a closed-loop frequency response system, calibrated to encompass illuminance levels ranging from 50 to 500 lux.The procedure for estimating the AC response of the PV cell is outlined, and the outcomes are subsequently employed in an analytical parameter extraction methodology. Experimental results from a 20 x 40 mm PV cell reveal that MPP represents the least favorable bias point in terms of bandwidth, whereas the SC bias point exhibits the most favorable performance. This observation validates the hypothesis that the optimal bias point for energy harvesting in PV cells is the worst bias point for communication purposes.
{"title":"Small-Signal Modeling and Parameter Extraction Method for Photovoltaic Cell Integration in Indoor Visible Light Communication Systems","authors":"Diego Mattos, Vitoria Monteiro, P. D. de Aguirre, Lucas Severo, Alessandro Girardi","doi":"10.29292/jics.v19i1.763","DOIUrl":"https://doi.org/10.29292/jics.v19i1.763","url":null,"abstract":"Photovoltaic (PV) cells are being adopted as a viable and cost-effective option for implementing receivers within Visible Light Communication (VLC) systems, primarily in indoor environments. Accurately estimating the generated current and voltage of the PV cell based on incident light is crucial when designing VLC systems.For this assessment, the 1D2R electrical equivalent model, which incorporates a diode and two resistors, is employed.In AC small signal analysis, the diode is substituted by its dynamic counterpart, which comprises a dynamic resistance in parallel with an equivalent capacitance. This study introduces an approach to measure and characterize the small-signal parameters of a PV cell operating at the maximum power point (MPP), open circuit (OC), and short circuit (SC) bias points. This is achieved through a closed-loop frequency response system, calibrated to encompass illuminance levels ranging from 50 to 500 lux.The procedure for estimating the AC response of the PV cell is outlined, and the outcomes are subsequently employed in an analytical parameter extraction methodology. Experimental results from a 20 x 40 mm PV cell reveal that MPP represents the least favorable bias point in terms of bandwidth, whereas the SC bias point exhibits the most favorable performance. This observation validates the hypothesis that the optimal bias point for energy harvesting in PV cells is the worst bias point for communication purposes.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" 15","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140391935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
HADJEM Dalila, Zakarya KOURDI, Imane FOUR, KERAI Salim, KHAOUANI Mohammed
The objectives of this research are to improve and optimize a vertically structure HEMT device based on AlGaN/GaN heterojunctions. This novel proposed structure with double gate command would allow for a better dispersion of the electric field, with peaks lower and farther from the surface than a lateral structure. The research focuses on estimating the performance of a GaN-based vertical structure called a "Current Aperture Vertical Electron Transistor (CAVET)" that combines a two-dimensional electron gas (2DEG) and a vertical structure with technology, operation, settings, and performance that can be seen in power applications. Performance operating at high frequencies and low power loss consumer, a device that will, therefore, lead function to best in electrical power and higher system efficiency with IDss equal 0.95 A, -6 V for pinch-off, fT/fMax are 110/250 GHz and 14 % for Drain-lag.
{"title":"Improved GaN-based Current Aperture Vertical Electron Transistor (CAVET)","authors":"HADJEM Dalila, Zakarya KOURDI, Imane FOUR, KERAI Salim, KHAOUANI Mohammed","doi":"10.29292/jics.v18i2.680","DOIUrl":"https://doi.org/10.29292/jics.v18i2.680","url":null,"abstract":"The objectives of this research are to improve and optimize a vertically structure HEMT device based on AlGaN/GaN heterojunctions. This novel proposed structure with double gate command would allow for a better dispersion of the electric field, with peaks lower and farther from the surface than a lateral structure. The research focuses on estimating the performance of a GaN-based vertical structure called a \"Current Aperture Vertical Electron Transistor (CAVET)\" that combines a two-dimensional electron gas (2DEG) and a vertical structure with technology, operation, settings, and performance that can be seen in power applications. Performance operating at high frequencies and low power loss consumer, a device that will, therefore, lead function to best in electrical power and higher system efficiency with IDss equal 0.95 A, -6 V for pinch-off, fT/fMax are 110/250 GHz and 14 % for Drain-lag.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135586826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Henrique Silva, Raimundo Carlos Silvério Freire, Jalberth Fernandes de Araújo, Sávio Correia Bezerra, Maria Nathália Freitas Nunes, Maxence Rube, Ollivier Tamarin
Surface acoustic wave sensors can be implemented within the feedback loop of sinusoidal oscillators for detecting pollutants. This detection process involves analyzing the variation of oscillator output voltage parameters, such as amplitude and oscillation frequency. However, each oscillator topology has a distinct operating range concerning frequency and component values. Therefore, a comparative analysis is necessary to determine the oscillator with optimal performance to use with the sensor. To obtain results, a surface acoustic wave sensor model was chosen based on a piezoelectric crystal with a resonant frequency of 117.6 MHz, and three sinusoidal oscillator topologies were used: Pierce, Colpitts, and Clapp. The oscillators were simulated with the sensor model in the feedback loop using the Montecarlo method. The simulation occurred in two steps: individually varying each component by +/- 20% with 250 iterations, and simultaneously varying all components by +/- 20% with 1000 iterations. The variables analyzed in the simulations were amplitude, oscillation frequency, and a new parameter indicating the percentage of time there is an oscillation, termed "robustness." As a result, it was determined that all three oscillators generated oscillations in the output voltage, making them viable for use with the sensor. Furthermore, it was discovered that the Clapp oscillator had a robustness of 84.5%, while the Colpitts and Pierce oscillators had a robustness of 56.3% and 49.9%, respectively. Therefore, based on the results presented in this study, the Clapp oscillator is the optimal choice for use with the surface acoustic wave sensor.
{"title":"Comparative Analysis of Sinusoidal Oscillators with Surface Acoustic Wave Sensor in the Feedback Loop","authors":"Henrique Silva, Raimundo Carlos Silvério Freire, Jalberth Fernandes de Araújo, Sávio Correia Bezerra, Maria Nathália Freitas Nunes, Maxence Rube, Ollivier Tamarin","doi":"10.29292/jics.v18i2.690","DOIUrl":"https://doi.org/10.29292/jics.v18i2.690","url":null,"abstract":"Surface acoustic wave sensors can be implemented within the feedback loop of sinusoidal oscillators for detecting pollutants. This detection process involves analyzing the variation of oscillator output voltage parameters, such as amplitude and oscillation frequency. However, each oscillator topology has a distinct operating range concerning frequency and component values. Therefore, a comparative analysis is necessary to determine the oscillator with optimal performance to use with the sensor. To obtain results, a surface acoustic wave sensor model was chosen based on a piezoelectric crystal with a resonant frequency of 117.6 MHz, and three sinusoidal oscillator topologies were used: Pierce, Colpitts, and Clapp. The oscillators were simulated with the sensor model in the feedback loop using the Montecarlo method. The simulation occurred in two steps: individually varying each component by +/- 20% with 250 iterations, and simultaneously varying all components by +/- 20% with 1000 iterations. The variables analyzed in the simulations were amplitude, oscillation frequency, and a new parameter indicating the percentage of time there is an oscillation, termed \"robustness.\" As a result, it was determined that all three oscillators generated oscillations in the output voltage, making them viable for use with the sensor. Furthermore, it was discovered that the Clapp oscillator had a robustness of 84.5%, while the Colpitts and Pierce oscillators had a robustness of 56.3% and 49.9%, respectively. Therefore, based on the results presented in this study, the Clapp oscillator is the optimal choice for use with the surface acoustic wave sensor.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135586112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A voltage-mode universal biquadratic filter using one second-generation current conveyor (CCII), one third-generation current conveyor (CCIII), two capacitors and two resistors is presented. The proposed voltage-mode biquadratic circuit has three input terminals and one output terminal and can realize all the standard filter functions that are highpass, bandpass, lowpass, notch and allpass filters without changing the circuit topology. Both its active and passive sensitivities are small. The proposed circuit does not need one more active component for the unity-gain inverting of the input signal in each filter realization.
{"title":"Three inputs and one output voltage-mode universal biquadratic filter using one CCII and one CCIII","authors":"Jiun-Wei Horng","doi":"10.29292/jics.v18i2.633","DOIUrl":"https://doi.org/10.29292/jics.v18i2.633","url":null,"abstract":"A voltage-mode universal biquadratic filter using one second-generation current conveyor (CCII), one third-generation current conveyor (CCIII), two capacitors and two resistors is presented. The proposed voltage-mode biquadratic circuit has three input terminals and one output terminal and can realize all the standard filter functions that are highpass, bandpass, lowpass, notch and allpass filters without changing the circuit topology. Both its active and passive sensitivities are small. The proposed circuit does not need one more active component for the unity-gain inverting of the input signal in each filter realization.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135586824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
None Rashmi Seethur, None Deeksha Sudarshan, None Vaibhavi Naik, None Tushar Masur, None Shreedhar H K
In copious mixed media applications, humans cannot necessarily discern error free or erroneous outputs, owing to the small range of perception abilities. Crucial information can still be obtained from marginally inexact outputs. Leveraging this, many algorithms such as Digital Signal Processing (DSP), Discrete Cosine Transform (DCT), Motion Compensation (MC) use approximate calculations while still maintaining appreciable computation accuracy. When data processing algorithms are taken into consideration, adders play an important role in the arithmetic module by managing the power and area utilization of the system. A fixed-width adder tree design for approximate calculations is proposed, that uses the trade-off between area and accuracy as the base for analysis. Our design uses 12.42%, 18.17% and 5.05% lesser area compared to the full width adder tree, FX-AT-PT and FX-AT-DT respectively. Additionally, when compared to FX-AT-DT, TFX-AT and ITFX-AT, the proposed design has an improved Maximum Error Distance (MED) of (33.33%, 29.03%), (63.64%, 65.63%) and (38.46%, 35.29%) for N = 8, 16 respectively. To cope with the inaccuracy caused by truncation, the proposed design employs mux-based radix-4 addition coupled with bias estimation. Further, to examine the error performance we have incorporated the proposed design and a few other existing designs into the Walsh-Hadamard Transform (WHT), to process images with different metrics and compare the Peak Signal to Noise Ratio (PSNR) of the images. It was observed that the proposed design showed significant improvement in the PSNR score when compared to ITFX-AT and maintains a score similar to that of FX-AT-PT.
{"title":"Multiplexer Based Error Efficient Fixed-Width Adder Tree Design for Signal Processing Applications","authors":"None Rashmi Seethur, None Deeksha Sudarshan, None Vaibhavi Naik, None Tushar Masur, None Shreedhar H K","doi":"10.29292/jics.v18i2.691","DOIUrl":"https://doi.org/10.29292/jics.v18i2.691","url":null,"abstract":"In copious mixed media applications, humans cannot necessarily discern error free or erroneous outputs, owing to the small range of perception abilities. Crucial information can still be obtained from marginally inexact outputs. Leveraging this, many algorithms such as Digital Signal Processing (DSP), Discrete Cosine Transform (DCT), Motion Compensation (MC) use approximate calculations while still maintaining appreciable computation accuracy. When data processing algorithms are taken into consideration, adders play an important role in the arithmetic module by managing the power and area utilization of the system. A fixed-width adder tree design for approximate calculations is proposed, that uses the trade-off between area and accuracy as the base for analysis. Our design uses 12.42%, 18.17% and 5.05% lesser area compared to the full width adder tree, FX-AT-PT and FX-AT-DT respectively. Additionally, when compared to FX-AT-DT, TFX-AT and ITFX-AT, the proposed design has an improved Maximum Error Distance (MED) of (33.33%, 29.03%), (63.64%, 65.63%) and (38.46%, 35.29%) for N = 8, 16 respectively. To cope with the inaccuracy caused by truncation, the proposed design employs mux-based radix-4 addition coupled with bias estimation. Further, to examine the error performance we have incorporated the proposed design and a few other existing designs into the Walsh-Hadamard Transform (WHT), to process images with different metrics and compare the Peak Signal to Noise Ratio (PSNR) of the images. It was observed that the proposed design showed significant improvement in the PSNR score when compared to ITFX-AT and maintains a score similar to that of FX-AT-PT.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135586113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a new approach was adopted in order to remove the artifacts present in the raw ECG signal. To realizing this process a multiple types of filters for a variety of types of noises have been applied to obtain the lowest possible noise. Initially, the ECG signal was filtered from the electromyography signal, and then the filtered signal was passed again on another filter for the purpose of removing its drift from the baseline. The effectiveness of the suggested approach has been assessed in comparison to the conventional ECG signal. Results of this study showed significantly less signaling noise than was present in the conventional signal. Overall, the signal to noise ratio and the mean square error of the filtered ECG reached 15.72 and 0.006, respectively, in the filtered signal of one of the ECG recordings.
{"title":"Pre-processing of ECG signal based on multistage filters","authors":"Mohammed Waheed","doi":"10.29292/jics.v18i2.698","DOIUrl":"https://doi.org/10.29292/jics.v18i2.698","url":null,"abstract":"In this paper, a new approach was adopted in order to remove the artifacts present in the raw ECG signal. To realizing this process a multiple types of filters for a variety of types of noises have been applied to obtain the lowest possible noise. Initially, the ECG signal was filtered from the electromyography signal, and then the filtered signal was passed again on another filter for the purpose of removing its drift from the baseline. The effectiveness of the suggested approach has been assessed in comparison to the conventional ECG signal. Results of this study showed significantly less signaling noise than was present in the conventional signal. Overall, the signal to noise ratio and the mean square error of the filtered ECG reached 15.72 and 0.006, respectively, in the filtered signal of one of the ECG recordings.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135586293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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