The Si3N4/ AlGaN/ AlN/ GaN Metal-Insulator-Semiconductor High Electron Mobility Transistor (MISHEMT) analog performance was ascertained considering the device’s multiple channels. MISHEMTs with different gate lengths, source/drain electrodes depths, source/drain distances to the gate electrode and AlGaN aluminum molar fractions were analyzed. The total drain current has 3 different components, where one of them is related to MOS conduction and the other two are related to HEMT conduction. Due to their different transport mechanism and distance to the gate electrode, each channel conduction exhibits different threshold voltages, causing unusual transfer and output characteristics, such as transconductance multiple slopes and a steady output resistance. As a result, the MISHEMTs presents an unexpected increase in intrinsic voltage gain (Av) for high gate bias (strong conduction). The HEMT conduction and the conduction through all the AlGaN volume are responsible for sustaining drain current levels so high that it affects the Early voltage more strongly than the degradation of output conductance, ensuring a high Av values.
{"title":"MISHEMT’s multiple conduction channels influence on its DC parameters","authors":"B. Canales, P. Agopian","doi":"10.29292/jics.v18i1.662","DOIUrl":"https://doi.org/10.29292/jics.v18i1.662","url":null,"abstract":"The Si3N4/ AlGaN/ AlN/ GaN Metal-Insulator-Semiconductor High Electron Mobility Transistor (MISHEMT) analog performance was ascertained considering the device’s multiple channels. MISHEMTs with different gate lengths, source/drain electrodes depths, source/drain distances to the gate electrode and AlGaN aluminum molar fractions were analyzed. The total drain current has 3 different components, where one of them is related to MOS conduction and the other two are related to HEMT conduction. Due to their different transport mechanism and distance to the gate electrode, each channel conduction exhibits different threshold voltages, causing unusual transfer and output characteristics, such as transconductance multiple slopes and a steady output resistance. As a result, the MISHEMTs presents an unexpected increase in intrinsic voltage gain (Av) for high gate bias (strong conduction). The HEMT conduction and the conduction through all the AlGaN volume are responsible for sustaining drain current levels so high that it affects the Early voltage more strongly than the degradation of output conductance, ensuring a high Av values.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43646206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Thomas Soupizet, Zalfa Jouni, Siqi Wang, A. Benlarbi-Delai, Pietro M. Ferreira
Different from classical artificial neural network which processes digital data, the spiking neural network (SNN) processes spike trains. Indeed, its event-driven property helps to capture the rich dynamics the neurons have within the brain, and the sparsity of collected spikes helps reducing computational power. Novel synthesis framework is proposed and an algorithm is detailed to guide designers into deep learning and energy-efficient analog SNN using MNIST. An analog SNN composed of 86 electronic neurons (eNeuron) and 1238 synapses interacting through two hidden layers is illustrated. Three different models of eNeurons implementations are tested, being (Leaky) Integrate-and-Fire (LIF), Morris Lecar (ML) simplified (simp.) and biomimetic (bio.). The proposed SNN, coupling deep learning and ultra-low power, is trained using a common machine learning system (Tensor- Flow) for the MNIST. LIF eNeurons implementations present some limitations and weakness in terms of dynamic range. Both ML eNeurons achieve robust accuracy which is approximately of 0.82.
与处理数字数据的经典人工神经网络不同，尖峰神经网络处理尖峰序列。事实上，它的事件驱动特性有助于捕捉神经元在大脑中的丰富动态，而收集到的尖峰的稀疏性有助于降低计算能力。提出了一种新的综合框架，并详细介绍了一种算法，以指导设计者使用MNIST进行深度学习和节能模拟SNN。图示了由86个电子神经元（eNeuron）和1238个突触通过两个隐藏层相互作用组成的模拟SNN。测试了三种不同的eNeurons实现模型，即（Leaky）Integration and Fire（LIF）、Morris Lecar（ML）simp.和仿生（bio.）。所提出的SNN耦合深度学习和超低功率，使用MNIST的通用机器学习系统（Tensor-Flow）进行训练。LIF eNeurons的实现在动态范围方面存在一些局限性和弱点。两个ML eNeuron都实现了大约为0.82的鲁棒精度。
{"title":"Analog Spiking Neural Network Synthesis for the MNIST","authors":"Thomas Soupizet, Zalfa Jouni, Siqi Wang, A. Benlarbi-Delai, Pietro M. Ferreira","doi":"10.29292/jics.v18i1.663","DOIUrl":"https://doi.org/10.29292/jics.v18i1.663","url":null,"abstract":"Different from classical artificial neural network which processes digital data, the spiking neural network (SNN) processes spike trains. Indeed, its event-driven property helps to capture the rich dynamics the neurons have within the brain, and the sparsity of collected spikes helps reducing computational power. Novel synthesis framework is proposed and an algorithm is detailed to guide designers into deep learning and energy-efficient analog SNN using MNIST. An analog SNN composed of 86 electronic neurons (eNeuron) and 1238 synapses interacting through two hidden layers is illustrated. Three different models of eNeurons implementations are tested, being (Leaky) Integrate-and-Fire (LIF), Morris Lecar (ML) simplified (simp.) and biomimetic (bio.). The proposed SNN, coupling deep learning and ultra-low power, is trained using a common machine learning system (Tensor- Flow) for the MNIST. LIF eNeurons implementations present some limitations and weakness in terms of dynamic range. Both ML eNeurons achieve robust accuracy which is approximately of 0.82.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43105139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The Impact of Aluminium nitride (AlN) Spacer, Gallium Nitride (GaN) Cap Layer, Front Pi Gate (FG) and Back Pi Gate(BG), High K dielectric material such as Hafnium dioxide(HfO2), Aluminium Oxide (Al2O3), Silicon nitride (Si3N4) on Aluminium Galium Nitride/ Gallium Nitride (AlGaN/GaN), Heterojunction High Electron Mobility Transistor (HEMT) of 6nm(nanometer) technology is simulated and extracted the results using the Silvaco Atlas TCAD tool. The importance of High K dielectric materials like Al2O3 and Si3N4 are studied for the proposal of GaN HEMT. AlN, GaN Cap Layers, and High K Dielectric material are layered one on another to overcome the conventional transistor draw backs like surface defects, scattering of the electron, and less mobility of electron. Hot electron effect is overcome by Pi type gate. Therefore, by optimizing the HEMT structure the abilities for certain devices are converted to abilities. The dependency on DC characteristics and RF characteristics due to GaN Cap Layers, Multi gate (FG &BG), and High K Dielectric material is established. Further Compared Single Gate (SG) Passivated HEMT, Double Gate (DG) Passivated HEMT, Double Gate Triple(DGT) Tooth Passivated HEMT, High K Dielectric Front Pi Gate (FG) and Back Pi Gate (BG) Nanowire HEMT. It is observed that there is an increased Drain Current (Ion) of 5.92(A/mm), low Leakage current(Ioff) 5.54E-13 (A) of Transconductance (Gm) of 3.71(S/mm), Drain Conductance (Gd) of 1.769(S/mm), Cutoff frequency(fT) of 743 GHz Maximum Oscillation frequency (Fmax) 765 GHz, Minimum Threshold Voltage (Vth) of -4.5V, On Resistance (Ron)of 0.40(Ohms) at Vgs =0V. These outstanding characteristics and transistor structure of proposed HEMT and materials involved to apply for upcoming generation High-speed GHz frequency applications.
{"title":"Qualitative Analysis & Advancement of Asymmetric Recessed Gates with Dual Floating Material GaN HEMT for Quantum Electronics","authors":"Y. Gowthami, B.Balaji, K. Srinivasa Rao","doi":"10.29292/jics.v18i1.657","DOIUrl":"https://doi.org/10.29292/jics.v18i1.657","url":null,"abstract":"The Impact of Aluminium nitride (AlN) Spacer, Gallium Nitride (GaN) Cap Layer, Front Pi Gate (FG) and Back Pi Gate(BG), High K dielectric material such as Hafnium dioxide(HfO2), Aluminium Oxide (Al2O3), Silicon nitride (Si3N4) on Aluminium Galium Nitride/ Gallium Nitride (AlGaN/GaN), Heterojunction High Electron Mobility Transistor (HEMT) of 6nm(nanometer) technology is simulated and extracted the results using the Silvaco Atlas TCAD tool. The importance of High K dielectric materials like Al2O3 and Si3N4 are studied for the proposal of GaN HEMT. AlN, GaN Cap Layers, and High K Dielectric material are layered one on another to overcome the conventional transistor draw backs like surface defects, scattering of the electron, and less mobility of electron. Hot electron effect is overcome by Pi type gate. Therefore, by optimizing the HEMT structure the abilities for certain devices are converted to abilities. The dependency on DC characteristics and RF characteristics due to GaN Cap Layers, Multi gate (FG &BG), and High K Dielectric material is established. Further Compared Single Gate (SG) Passivated HEMT, Double Gate (DG) Passivated HEMT, Double Gate Triple(DGT) Tooth Passivated HEMT, High K Dielectric Front Pi Gate (FG) and Back Pi Gate (BG) Nanowire HEMT. It is observed that there is an increased Drain Current (Ion) of 5.92(A/mm), low Leakage current(Ioff) 5.54E-13 (A) of Transconductance (Gm) of 3.71(S/mm), Drain Conductance (Gd) of 1.769(S/mm), Cutoff frequency(fT) of 743 GHz Maximum Oscillation frequency (Fmax) 765 GHz, Minimum Threshold Voltage (Vth) of -4.5V, On Resistance (Ron)of 0.40(Ohms) at Vgs =0V. These outstanding characteristics and transistor structure of proposed HEMT and materials involved to apply for upcoming generation High-speed GHz frequency applications.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48011993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Huziel Souto, Fernando Cesar Rufino, Renato Massaroto Beraldo, Sergio Henrique Fernandes, José Alexandre Diniz
This work presents the development of an Electrolyte-Insulator-Semiconductor (EIS) device with a built-in reference electrode to detect phosphate in wastewater. The idea of developing this device comes from the need to improve the use of water processed by the effluent treatment plant. After treatment process, a fraction of the water can be used as wastewater, this water cannot be consumed, however it can be used for other purposes including cleaning public spaces, such as streets and squares. In the fabrication process of the EIS device, titanium oxide (TiO2) deposited on a silicon substrate was used as a sensor element, and titanium nitride (TiN) was used for the reference electrode. Both materials were deposited by the reactive sputtering process. Aluminum (Al) was used for the electrode on the back of the slide deposited by evaporation. Preliminary results of structural and electrical characterizations indicate that the manufactured device has good sensitivity to phosphate ions (66 mV/ppm). This sensitivity is due to the good quality of the film, which is shown using Raman spectroscopy, atomic force microscopy (AFM) and X-ray diffraction (XRD) techniques, in addition to electrical measurements.
{"title":"EIS capacitor sensor, with TiO2 dielectric, applied in the evaluation of phosphate in wastewater","authors":"Huziel Souto, Fernando Cesar Rufino, Renato Massaroto Beraldo, Sergio Henrique Fernandes, José Alexandre Diniz","doi":"10.29292/jics.v18i1.670","DOIUrl":"https://doi.org/10.29292/jics.v18i1.670","url":null,"abstract":"This work presents the development of an Electrolyte-Insulator-Semiconductor (EIS) device with a built-in reference electrode to detect phosphate in wastewater. The idea of developing this device comes from the need to improve the use of water processed by the effluent treatment plant. After treatment process, a fraction of the water can be used as wastewater, this water cannot be consumed, however it can be used for other purposes including cleaning public spaces, such as streets and squares. In the fabrication process of the EIS device, titanium oxide (TiO2) deposited on a silicon substrate was used as a sensor element, and titanium nitride (TiN) was used for the reference electrode. Both materials were deposited by the reactive sputtering process. Aluminum (Al) was used for the electrode on the back of the slide deposited by evaporation. Preliminary results of structural and electrical characterizations indicate that the manufactured device has good sensitivity to phosphate ions (66 mV/ppm). This sensitivity is due to the good quality of the film, which is shown using Raman spectroscopy, atomic force microscopy (AFM) and X-ray diffraction (XRD) techniques, in addition to electrical measurements.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135429369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Matheus Cortez, A. Girardi, L. Severo, P. D. de Aguirre
Most mobile and wearable devices present digital audio signal processing capabilities. Since the nature of audio signals is analog, there is a need to use analog-to-digital converters (ADCs) with high-resolution for a high signal-to-noise ratio audio acquisition. This paper presents the high-level modeling and design of a continuous-time third-order sigma-delta modulator (CT-SDM) with an FIR DAC for audio devices, using a supply voltage of 0.5 V. The design is divided in three steps and is carried out using the Delta-sigma toolbox and a discrete-time to continuous-time (DT-CT) transformation. First, the schematic implementation with verilogA models is done to estimate the first-integrator amplifier specifications for the modulator to provide 14 bits of ENOB. Following, a two-stage inverter-based amplifier is designed and used to verify the design strategy. Finally, a transistor-level implementation of OTAs and comparator is done to evaluate the CT-SDM performance. An in-depth analysis and discussion are presented to explain the achieved results with those transistor-level circuits.
{"title":"Behavioral and Electrical Modeling of a 0.5-V Third-Order Continuous-Time Sigma-Delta Modulator with FIR DAC for Audio Applications","authors":"Matheus Cortez, A. Girardi, L. Severo, P. D. de Aguirre","doi":"10.29292/jics.v18i1.664","DOIUrl":"https://doi.org/10.29292/jics.v18i1.664","url":null,"abstract":"Most mobile and wearable devices present digital audio signal processing capabilities. Since the nature of audio signals is analog, there is a need to use analog-to-digital converters (ADCs) with high-resolution for a high signal-to-noise ratio audio acquisition. This paper presents the high-level modeling and design of a continuous-time third-order sigma-delta modulator (CT-SDM) with an FIR DAC for audio devices, using a supply voltage of 0.5 V. The design is divided in three steps and is carried out using the Delta-sigma toolbox and a discrete-time to continuous-time (DT-CT) transformation. First, the schematic implementation with verilogA models is done to estimate the first-integrator amplifier specifications for the modulator to provide 14 bits of ENOB. Following, a two-stage inverter-based amplifier is designed and used to verify the design strategy. Finally, a transistor-level implementation of OTAs and comparator is done to evaluate the CT-SDM performance. An in-depth analysis and discussion are presented to explain the achieved results with those transistor-level circuits.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47432908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the design of low-dropout volt-age regulators (LDO) using nanowire tunnel field-effect tran-sistors (TFETs) and nanowire MOSFET. The devices are mod-eled using lookup tables implemented with experimental measures of TFETs with different source compositions (Si, SiGe and Ge) and MOSFET. In order to compare the designs, the transistors of the differential amplifier in all LDOs is biased with gm/ID = 8 V-1 with a load of 1 μA and 10-pF. It is shown that all TFET based LDOs are stables without the need of a compensator capacitor (CC) even for higher load capacitance. For the MOSFET LDO, a CC of 5-pF capacitor was used. The study shows that the TFET based LDOs deliver higher effi-ciency due to the possibility to operate with low bias current. In the transient analysis it is shown that the TFET LDOs have lower overshoot but higher delay. The Ge-TFET LDO pre-sented settling times for load and line transient close to the MOSFET LDO with 15 μs and 30 μs. The SiGe-TFET LDO shows the best loop gain (60 dB), while the Si-TFET LDO deliv-ers lowest quiescent current (300 pA) and the Ge-TFET have the best GBW (70 KHz) and PSR (-52 dB). It is concluded that the TFET based LDOs can deliver specifications similar or bet-ter than the MOSFET LDO even without the need of CC and with less power consumption.
{"title":"Low-Dropout Voltage Regulator Designed with Nanowire TFET with Different Source Composition Experimental Data","authors":"R. Tolêdo, J. Martino, Paula Ghedini Der Agopian","doi":"10.29292/jics.v18i1.653","DOIUrl":"https://doi.org/10.29292/jics.v18i1.653","url":null,"abstract":"This paper presents the design of low-dropout volt-age regulators (LDO) using nanowire tunnel field-effect tran-sistors (TFETs) and nanowire MOSFET. The devices are mod-eled using lookup tables implemented with experimental measures of TFETs with different source compositions (Si, SiGe and Ge) and MOSFET. In order to compare the designs, the transistors of the differential amplifier in all LDOs is biased with gm/ID = 8 V-1 with a load of 1 μA and 10-pF. It is shown that all TFET based LDOs are stables without the need of a compensator capacitor (CC) even for higher load capacitance. For the MOSFET LDO, a CC of 5-pF capacitor was used. The study shows that the TFET based LDOs deliver higher effi-ciency due to the possibility to operate with low bias current. In the transient analysis it is shown that the TFET LDOs have lower overshoot but higher delay. The Ge-TFET LDO pre-sented settling times for load and line transient close to the MOSFET LDO with 15 μs and 30 μs. The SiGe-TFET LDO shows the best loop gain (60 dB), while the Si-TFET LDO deliv-ers lowest quiescent current (300 pA) and the Ge-TFET have the best GBW (70 KHz) and PSR (-52 dB). It is concluded that the TFET based LDOs can deliver specifications similar or bet-ter than the MOSFET LDO even without the need of CC and with less power consumption.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43999234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article describes the design of a low power, low phase noise, multi-Path ring VCO (MPRVCO) in 90nm CMOS process. The proposed oscillator achieves a tuning range of 1.2GHz operating at 1.65 GHz center frequency, with reduced phase noise of -87.3dBc/Hz at 1MHz offset. The proposed MPRVCO achieves a FoM of 153.4dBc/Hz, consuming 0.657mW power at 1.65GHz frequency. The proposed VCO utilizes Current starving technique for frequency variation. Sub-threshold transistor is used to obtain monotonic and linear frequency tuning characteristics. The proposed VCO is one of the very few Current Starved ring VCOs capable of producing such low phase noise in 90nm CMOS process while operating in GHz frequency range
{"title":"A 1.2GHz Frequency Range, 153.4 dBc/Hz FoM, low Phase Noise, Current Starved Multi-Path Ring VCO","authors":"Mohd Ziauddin Jahangir, C. Paidimarry","doi":"10.29292/jics.v18i1.676","DOIUrl":"https://doi.org/10.29292/jics.v18i1.676","url":null,"abstract":"This article describes the design of a low power, low phase noise, multi-Path ring VCO (MPRVCO) in 90nm CMOS process. The proposed oscillator achieves a tuning range of 1.2GHz operating at 1.65 GHz center frequency, with reduced phase noise of -87.3dBc/Hz at 1MHz offset. The proposed MPRVCO achieves a FoM of 153.4dBc/Hz, consuming 0.657mW power at 1.65GHz frequency. The proposed VCO utilizes Current starving technique for frequency variation. Sub-threshold transistor is used to obtain monotonic and linear frequency tuning characteristics. The proposed VCO is one of the very few Current Starved ring VCOs capable of producing such low phase noise in 90nm CMOS process while operating in GHz frequency range","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41633828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a dedicated hardware architecture for the Low-Frequency Non-Separable Transform (LFNST) of the Versatile Video Coding (H.266/VVC) standard. The VVC defines two stages of transformation, where the first stage uses traditional transform types (e.g. DCT-II, DCT-VII and DST-VII), while the secondary transform stage applies the LFNST. The LFNST is used to transform the coefficients that were transformed by the DCT-II in the primary transform, but only those from the residues that came from the intra prediction. The developed LFNST system design exploits the Clock Crossing Domain technique to extract the best relation between performance and area/power. Consequently, the design operates with two clock domains, where the core operates at a four times higher frequency than the primary transform. The ASIC synthesis results for a TSMC 40nm standard-cells library indicate that our design can process UHD 4K videos at 120 frames per second while using an area of 69.68 Kgates, and with a power dissipation of 40.46 mW. When compared with related works, our design presented the lowest power dissipation and energy consumption per sample.
{"title":"Efficient Dedicated Hardware Design System for the VVC Low-Frequency Non-Separable Transform","authors":"J. Goebel, B. Zatt, L. Agostini, M. Porto","doi":"10.29292/jics.v18i1.668","DOIUrl":"https://doi.org/10.29292/jics.v18i1.668","url":null,"abstract":"This paper proposes a dedicated hardware architecture for the Low-Frequency Non-Separable Transform (LFNST) of the Versatile Video Coding (H.266/VVC) standard. The VVC defines two stages of transformation, where the first stage uses traditional transform types (e.g. DCT-II, DCT-VII and DST-VII), while the secondary transform stage applies the LFNST. The LFNST is used to transform the coefficients that were transformed by the DCT-II in the primary transform, but only those from the residues that came from the intra prediction. The developed LFNST system design exploits the Clock Crossing Domain technique to extract the best relation between performance and area/power. Consequently, the design operates with two clock domains, where the core operates at a four times higher frequency than the primary transform. The ASIC synthesis results for a TSMC 40nm standard-cells library indicate that our design can process UHD 4K videos at 120 frames per second while using an area of 69.68 Kgates, and with a power dissipation of 40.46 mW. When compared with related works, our design presented the lowest power dissipation and energy consumption per sample.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41821601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Defining the timing characteristics behavior, such as the gate delay and the oscillation period, is an essential task in integrated circuits (ICs), especially for low-power CMOS-based technologies. The nanometric-sized devices designed to achieve low-power consumption have higher threshold voltages. Hence, these devices are operated at the near-threshold regime, or slightly above the threshold. In these regions, shifts in electrical parameters (expressed in terms of drain current or threshold voltage) may severely impact the circuit behavior. Consequently, the time-dependent sources of variability (e.g., the bias temperature instability) impose a crucial reliability problem that affects time delay variability and induces slope propagation effects along the signal path. In this context, an improved analytical model to properly account for both the gate delay and its variability is presented, taking into account the properties of low-power devices. Additionally, the applicability of the model is presented in a case study of a ring oscillator. The derived equations allows a suitable estimative for the parameters’ degradation. Supported by Monte Carlo simulations, the extracted results indicate that the proposed method provides a better estimate for the ring oscillator jitter when compared to the simplified propagation of uncertainty method.
{"title":"An Analytical Gate Delay Variability Model for Low-Power Applications under the Process Variations Effects","authors":"Caroline Pinheiro Garcia, Thiago Hanna Both","doi":"10.29292/jics.v18i1.654","DOIUrl":"https://doi.org/10.29292/jics.v18i1.654","url":null,"abstract":"Defining the timing characteristics behavior, such as the gate delay and the oscillation period, is an essential task in integrated circuits (ICs), especially for low-power CMOS-based technologies. The nanometric-sized devices designed to achieve low-power consumption have higher threshold voltages. Hence, these devices are operated at the near-threshold regime, or slightly above the threshold. In these regions, shifts in electrical parameters (expressed in terms of drain current or threshold voltage) may severely impact the circuit behavior. Consequently, the time-dependent sources of variability (e.g., the bias temperature instability) impose a crucial reliability problem that affects time delay variability and induces slope propagation effects along the signal path. In this context, an improved analytical model to properly account for both the gate delay and its variability is presented, taking into account the properties of low-power devices. Additionally, the applicability of the model is presented in a case study of a ring oscillator. The derived equations allows a suitable estimative for the parameters’ degradation. Supported by Monte Carlo simulations, the extracted results indicate that the proposed method provides a better estimate for the ring oscillator jitter when compared to the simplified propagation of uncertainty method.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48027852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The design of digital circuits on recent technologies brings several challenges, among which robustness to variations stands out. Variation sources are multiple, and the evolution of integrated circuit fabrication techniques increases the number and relevance of such sources, and the complexity of ensuring circuit robustness against them. Some design paradigms naturally counter variations of one or more types. Asynchronous self-timed design is one such paradigm that can provide robustness to process, voltage, temperature, ageing and IR drop variations, to cite some of the main types. This paper proposes an enhancement to the Pulsar environment, a recently proposed open source automated flow for the design of self-timed clockless circuits.The six components proposed here enable describing choices and decisions on the flow of data tokens inside asynchronous circuits.Design capture in Pulsar can then employ these. To implement the abstract (synthesis-enabled) components, the paper also bringsthe proposal of the handshaking mutex, a versatile complex gate that eases the design of probe and arbiter, the two most complex among the new components. Results demonstrate the new version of Pulsar is more powerful than the previous, baseline, version, enabling the design capture and the automated synthesis steps of more complex asynchronous self-timed circuits. They also indicate the handshaking mutex operates correctly, and with a good level of attested fairness.
{"title":"Components to Support Choice in Self-Timed Asynchronous Design Flows","authors":"Marcos Luiggi Lemos Sartori, Willian Analdo Nunes, Ney Laert Vilar Calazans","doi":"10.29292/jics.v18i1.671","DOIUrl":"https://doi.org/10.29292/jics.v18i1.671","url":null,"abstract":"The design of digital circuits on recent technologies brings several challenges, among which robustness to variations stands out. Variation sources are multiple, and the evolution of integrated circuit fabrication techniques increases the number and relevance of such sources, and the complexity of ensuring circuit robustness against them. Some design paradigms naturally counter variations of one or more types. Asynchronous self-timed design is one such paradigm that can provide robustness to process, voltage, temperature, ageing and IR drop variations, to cite some of the main types. This paper proposes an enhancement to the Pulsar environment, a recently proposed open source automated flow for the design of self-timed clockless circuits.The six components proposed here enable describing choices and decisions on the flow of data tokens inside asynchronous circuits.Design capture in Pulsar can then employ these. To implement the abstract (synthesis-enabled) components, the paper also bringsthe proposal of the handshaking mutex, a versatile complex gate that eases the design of probe and arbiter, the two most complex among the new components. Results demonstrate the new version of Pulsar is more powerful than the previous, baseline, version, enabling the design capture and the automated synthesis steps of more complex asynchronous self-timed circuits. They also indicate the handshaking mutex operates correctly, and with a good level of attested fairness.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45597261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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