A simple and efficient parameter extraction method for Silicon Carbide (SiC) power MOSFET model is described. This method uses nonlinear optimization algorithm to find the optimal set of parameters to model. The optimizer algorithm starts with initial guess parameters, extracted from measurement, to provide a set of parameters minimizing errors between model and measurements data in entire operating regions of the device. The starting initial guess parameter values give to the algorithm a closed solution to obtain the optimal set of model parameters with reduced iteratives. The Levenberg-Marquardt (LM) algorithm will be used in this work. The efficiency of the proposed extraction method is proved with the good agreements obtained between the model and the measurements.
{"title":"An Optimal Parameter Extraction Procedure for SiC Power MOSFET Model","authors":"Hicham Er-rafii, Abdelghafour Galadi","doi":"10.29292/jics.v18i2.756","DOIUrl":"https://doi.org/10.29292/jics.v18i2.756","url":null,"abstract":"A simple and efficient parameter extraction method for Silicon Carbide (SiC) power MOSFET model is described. This method uses nonlinear optimization algorithm to find the optimal set of parameters to model. The optimizer algorithm starts with initial guess parameters, extracted from measurement, to provide a set of parameters minimizing errors between model and measurements data in entire operating regions of the device. The starting initial guess parameter values give to the algorithm a closed solution to obtain the optimal set of model parameters with reduced iteratives. The Levenberg-Marquardt (LM) algorithm will be used in this work. The efficiency of the proposed extraction method is proved with the good agreements obtained between the model and the measurements.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135586294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Vinicius Zanandrea, Douglas Borges, Vagner Rosa, Cristina Meinhardt
With the rising importance of power consumption in battery-powered devices, approximate computing techniques have emerged as a promising approach to strike a balance between exact computation and power savings, leading to improved delays. This paper investigates the combination of near-threshold operation and approximate adders to design power-efficient multipliers. We analyzed four multiplier architectures using 16 nm low-power and high-performance models. At the transistor level, three strategies for approximate full adders are explored, focusing on both partial product reduction and the final addition stage of the multipliers. Eleven test cases are thoroughly evaluated to identify the most suitable approximate circuit, considering the trade-offs among power, performance, and accuracy. The obtained results demonstrate a substantial reduction in power consumption at near-threshold operation. The replacement of exact full adders with the approximate copy strategy in the least significant bits of the multipliers leads to a reduction of up to 34.4% in power consumption and 19.2% in delay. The design-space exploration carried out in this study provides valuable insights for designers to choose the best approximate multiplier based on specific design requirements.
{"title":"On the Use of Low-power Devices, Approximate Adders and Near-threshold Operation for Energy-efficient Multipliers","authors":"Vinicius Zanandrea, Douglas Borges, Vagner Rosa, Cristina Meinhardt","doi":"10.29292/jics.v18i2.754","DOIUrl":"https://doi.org/10.29292/jics.v18i2.754","url":null,"abstract":"With the rising importance of power consumption in battery-powered devices, approximate computing techniques have emerged as a promising approach to strike a balance between exact computation and power savings, leading to improved delays. This paper investigates the combination of near-threshold operation and approximate adders to design power-efficient multipliers. We analyzed four multiplier architectures using 16 nm low-power and high-performance models. At the transistor level, three strategies for approximate full adders are explored, focusing on both partial product reduction and the final addition stage of the multipliers. Eleven test cases are thoroughly evaluated to identify the most suitable approximate circuit, considering the trade-offs among power, performance, and accuracy. The obtained results demonstrate a substantial reduction in power consumption at near-threshold operation. The replacement of exact full adders with the approximate copy strategy in the least significant bits of the multipliers leads to a reduction of up to 34.4% in power consumption and 19.2% in delay. The design-space exploration carried out in this study provides valuable insights for designers to choose the best approximate multiplier based on specific design requirements.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135586290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cryptographic solutions based on traditional authentication methods are susceptible to several attacks on secret keys. Dynamic random access memory (DRAM)-based physical unclonable functions (PUF) are described as promising security building blocks to enable cryptography and authentication services. PUFs frequently suffer reliability concerns since they are sensitive to both internal and exterior noises. The need for enhanced resistance and dependability results in significant additional overheads. In this work, we proposed a DRAM-PUF based on the inclusion of selective hardware features in the computation. The proposed solution offers a higher number of challenge-response pairs (CRP) without additional circuitry. An innovative structure of PUF is presented in the paper which offers a reliable challenge-response pair module for authentication and authorization based on the ubiquitous nature of memory without the need for an additional circuit. DRAM PUF utilized the random startup value initialized by a capacitor followed by a random number generator. Our proposed PUF shows a reliability of 99.46% with temperature variation, a reliability of 99.5% with supply voltage variation, a uniqueness of 49.46%, a bit aliasing of 46.875%, and a uniformity of 47.65%.
{"title":"An Innovative Architecture of DRAM PUF","authors":"Abhishek Kumar, None Manoj Sindhwani, Shippu Sachdeva","doi":"10.29292/jics.v18i2.675","DOIUrl":"https://doi.org/10.29292/jics.v18i2.675","url":null,"abstract":"Cryptographic solutions based on traditional authentication methods are susceptible to several attacks on secret keys. Dynamic random access memory (DRAM)-based physical unclonable functions (PUF) are described as promising security building blocks to enable cryptography and authentication services. PUFs frequently suffer reliability concerns since they are sensitive to both internal and exterior noises. The need for enhanced resistance and dependability results in significant additional overheads. In this work, we proposed a DRAM-PUF based on the inclusion of selective hardware features in the computation. The proposed solution offers a higher number of challenge-response pairs (CRP) without additional circuitry. An innovative structure of PUF is presented in the paper which offers a reliable challenge-response pair module for authentication and authorization based on the ubiquitous nature of memory without the need for an additional circuit. DRAM PUF utilized the random startup value initialized by a capacitor followed by a random number generator. Our proposed PUF shows a reliability of 99.46% with temperature variation, a reliability of 99.5% with supply voltage variation, a uniqueness of 49.46%, a bit aliasing of 46.875%, and a uniformity of 47.65%.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135586291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fernando Pizzo Ribeiro, Egon Galembeck, Rodrigo A. de Lima Moreto, Salvador Pinillos Gimenez
According to a study by the International Energy Agency (IEA), solar energy could reach 30% in 2023 in countries with the most excellent installed generation capacity, such as China, Germany, Japan, and the United States of America. In other countries, like Brazil (mainly in Paraiba state), for instance, the volume of investments in the solar energy sector is equal to 4.17 billion Reais of private investments in 2022 to implement a photovoltaic module factory to reach an installed capacity of 1.6GW. In this context, several efforts have been made to boost the electrical performance of solar cells in terms of using new materials, fabrication processes, and constructive essential elements to produce electric energy with more efficiency. Thus, this paper performs, by three-dimensional numerical simulations, a comparative study between solar cells implemented with constructive elements based on Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), N channel, depletion type, with two types of gate geometries, in which one is layouted with the typical rectangular (Rectangular MOSFET, RM) and other is implemented with the FISH layout style (FISH MOSFET, FM). The main results have shown that the solar cell implemented with the FISH MOSFET has an efficiency of approximately 57% higher than that presented in the solar cell implemented with the Conventional MOSFET. Therefore, the solar cells implemented with FISH MOSFETs can be considered an alternative constructive essential element to improve the electrical performance of solar cells.
{"title":"Study of Solar Cells Using FISH MOSFETs as a Constructive Element to Generate Photocurrent in the Longitudinal Direction","authors":"Fernando Pizzo Ribeiro, Egon Galembeck, Rodrigo A. de Lima Moreto, Salvador Pinillos Gimenez","doi":"10.29292/jics.v18i2.616","DOIUrl":"https://doi.org/10.29292/jics.v18i2.616","url":null,"abstract":"According to a study by the International Energy Agency (IEA), solar energy could reach 30% in 2023 in countries with the most excellent installed generation capacity, such as China, Germany, Japan, and the United States of America. In other countries, like Brazil (mainly in Paraiba state), for instance, the volume of investments in the solar energy sector is equal to 4.17 billion Reais of private investments in 2022 to implement a photovoltaic module factory to reach an installed capacity of 1.6GW. In this context, several efforts have been made to boost the electrical performance of solar cells in terms of using new materials, fabrication processes, and constructive essential elements to produce electric energy with more efficiency. Thus, this paper performs, by three-dimensional numerical simulations, a comparative study between solar cells implemented with constructive elements based on Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), N channel, depletion type, with two types of gate geometries, in which one is layouted with the typical rectangular (Rectangular MOSFET, RM) and other is implemented with the FISH layout style (FISH MOSFET, FM). The main results have shown that the solar cell implemented with the FISH MOSFET has an efficiency of approximately 57% higher than that presented in the solar cell implemented with the Conventional MOSFET. Therefore, the solar cells implemented with FISH MOSFETs can be considered an alternative constructive essential element to improve the electrical performance of solar cells.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135586821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For precise digital control applications, high-resolution feedback is essential to achieve the required performance. Precise control systems with analog input-output and digital processing are generally limited by the resolution of digital to analog converter (DAC). DACs available for space use are limited in terms of resolution and performance. This paper presents a novel approach of combining two DACs to achieve higher resolution in closed-loop control systems. DACs can be combined with an overlapping range such that nonlinearity of higher significant DAC does not cause oscillations and instability when lower significant DAC rolls over. Flowchart of the algorithm for combining two DACs is presented, along with a detailed analysis. Simulation results are also shown elaborating the behaviour of DACs in non-overlapping and overlapping combination methods. The non-overlapping combination may result in oscillations, while the overlapping combination can settle the loop after a small settling time. An implementation example of a digital lock-in amplifier for the Rubidium atomic clock, showing the realization of a coarse-fine DAC combination to achieve 20-bits resolution with two 12-bits DACs, is also presented. This approach will result in achieving better performance in small-bandwidth digital control systems.
{"title":"A Novel Method of Digital-to-Analog Converter Combination for Precise Digital Control in Closed Loop Systems","authors":"Pratik Jain, Priyanka Priya","doi":"10.29292/jics.v18i2.735","DOIUrl":"https://doi.org/10.29292/jics.v18i2.735","url":null,"abstract":"For precise digital control applications, high-resolution feedback is essential to achieve the required performance. Precise control systems with analog input-output and digital processing are generally limited by the resolution of digital to analog converter (DAC). DACs available for space use are limited in terms of resolution and performance. This paper presents a novel approach of combining two DACs to achieve higher resolution in closed-loop control systems. DACs can be combined with an overlapping range such that nonlinearity of higher significant DAC does not cause oscillations and instability when lower significant DAC rolls over. Flowchart of the algorithm for combining two DACs is presented, along with a detailed analysis. Simulation results are also shown elaborating the behaviour of DACs in non-overlapping and overlapping combination methods. The non-overlapping combination may result in oscillations, while the overlapping combination can settle the loop after a small settling time. An implementation example of a digital lock-in amplifier for the Rubidium atomic clock, showing the realization of a coarse-fine DAC combination to achieve 20-bits resolution with two 12-bits DACs, is also presented. This approach will result in achieving better performance in small-bandwidth digital control systems.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135586823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Marcio Monteiro, Ismael Seidel, José Luis Güntzel, Mateus Grellert, Leonardo Soares, Cristina Meinhardt
Gaussian filtering is an important step in many image-processing applications because it reduces image noise.However, this step is also compute-intensive, so power-optimized hardware architectures are necessary to allow its adoption in embedded devices. This work presents a design space exploration of power-efficient Gaussian filter architectures.Differently from related work, this work shows the impacts of the design decisions on two target applications: the Canny Algorithm and an Automatic License Plate Recognition system.To explore the design space, the 3x3, 5x5, and 7x7kernels were logically refactored using Multiplierless Constant Multiplication and Common Sub-expression Exploration. The adders were approximated using the copy strategy to further reduce power consumption. Systematic experiments show the effects of the adopted strategies on power savings and quality of results compared to exact baselines using the two applications.The approximate strategy reached up to 51 dB of Peak Signal-to-Noise Ratio with power reductions of up to 48% in the best-case scenario of the standalone Gaussian filters. Also, the total power of the Gaussian filter in the Canny Algorithm can be reduced down to 34% while maintaining the precision of results between 57% and 90%. Finally, the proposed strategies reduce up to 64% of the Gaussian filter power consumption when adopted in the plate detection solution with a similar detection rate compared to the exact filter architecture.
{"title":"A Design Space Exploration of Power-efficient Gaussian Filter Architectures using Logical Optimization and Approximated Adders","authors":"Marcio Monteiro, Ismael Seidel, José Luis Güntzel, Mateus Grellert, Leonardo Soares, Cristina Meinhardt","doi":"10.29292/jics.v18i2.702","DOIUrl":"https://doi.org/10.29292/jics.v18i2.702","url":null,"abstract":"Gaussian filtering is an important step in many image-processing applications because it reduces image noise.However, this step is also compute-intensive, so power-optimized hardware architectures are necessary to allow its adoption in embedded devices. This work presents a design space exploration of power-efficient Gaussian filter architectures.Differently from related work, this work shows the impacts of the design decisions on two target applications: the Canny Algorithm and an Automatic License Plate Recognition system.To explore the design space, the 3x3, 5x5, and 7x7kernels were logically refactored using Multiplierless Constant Multiplication and Common Sub-expression Exploration. The adders were approximated using the copy strategy to further reduce power consumption. Systematic experiments show the effects of the adopted strategies on power savings and quality of results compared to exact baselines using the two applications.The approximate strategy reached up to 51 dB of Peak Signal-to-Noise Ratio with power reductions of up to 48% in the best-case scenario of the standalone Gaussian filters. Also, the total power of the Gaussian filter in the Canny Algorithm can be reduced down to 34% while maintaining the precision of results between 57% and 90%. Finally, the proposed strategies reduce up to 64% of the Gaussian filter power consumption when adopted in the plate detection solution with a similar detection rate compared to the exact filter architecture.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135586292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
NBTI is a key reliability challenge in nanoscale digital design, and it is vital to address it throughout the exploration of design space at high levels of abstraction in order to improve reliability. A prediction model of aging that is adequate for these levels ought to be faster. In addition to this, the model should be able to forecast the recently discovered stochastic consequences of growing older. The purpose of this study is to offer a model that is based on machine learning (ML) and can predict aging effects. After obtaining a training set of sufficient size using Synopsis HSPICE (MOSFET Reliability, MOSRA) in the beginning, the machine-learning-based model is then trained and built in order to forecast the aging statistical features. Evaluation is done on a number of machine learning techniques, including Adaptive Neuro-Fuzzy Inference System (ANFIS), K-Nearest Neighbor (KNN), Support Vector Machine (SVM) and Random Forest (RF). The findings indicate that ANFIS algorithms are very effective in the process of age prediction. The proposed technique shows that the aging prediction runtime is reduced by more than 99% when compared to the MOSRA-based approach, and accurate predictions of the statistical properties of aging are obtained with an accuracy of more than 99% on complementary metal oxide semiconductor (CMOS) and metal gate/high-K (MGK) circuits at the 22nm technology node.
NBTI是纳米数字设计中一个关键的可靠性挑战，为了提高可靠性，在高抽象层次的设计空间探索中解决它是至关重要的。一个适合这些水平的衰老预测模型应该更快。除此之外，该模型应该能够预测最近发现的随年龄增长的随机结果。本研究的目的是提供一个基于机器学习(ML)的模型，可以预测衰老的影响。在开始使用synopsyshspice (MOSFET Reliability, MOSRA)获得足够规模的训练集后，然后训练和构建基于机器学习的模型，以预测老化统计特征。对许多机器学习技术进行了评估，包括自适应神经模糊推理系统(ANFIS)， k -最近邻(KNN)，支持向量机(SVM)和随机森林(RF)。结果表明，ANFIS算法在年龄预测过程中是非常有效的。与基于mosra的方法相比，该方法的老化预测运行时间缩短了99%以上，并且在22nm技术节点上对互补金属氧化物半导体(CMOS)和金属栅/高k (MGK)电路的老化统计特性进行了准确预测，精度超过99%。
{"title":"A Machine Learning Based Reliability Analysis of Negative Bias Temperature Instability (NBTI) Compliant Design for Ultra Large Scale Digital Integrated Circuit","authors":"Karan Singh, Shruti Kalra","doi":"10.29292/jics.v18i2.686","DOIUrl":"https://doi.org/10.29292/jics.v18i2.686","url":null,"abstract":"NBTI is a key reliability challenge in nanoscale digital design, and it is vital to address it throughout the exploration of design space at high levels of abstraction in order to improve reliability. A prediction model of aging that is adequate for these levels ought to be faster. In addition to this, the model should be able to forecast the recently discovered stochastic consequences of growing older. The purpose of this study is to offer a model that is based on machine learning (ML) and can predict aging effects. After obtaining a training set of sufficient size using Synopsis HSPICE (MOSFET Reliability, MOSRA) in the beginning, the machine-learning-based model is then trained and built in order to forecast the aging statistical features. Evaluation is done on a number of machine learning techniques, including Adaptive Neuro-Fuzzy Inference System (ANFIS), K-Nearest Neighbor (KNN), Support Vector Machine (SVM) and Random Forest (RF). The findings indicate that ANFIS algorithms are very effective in the process of age prediction. The proposed technique shows that the aging prediction runtime is reduced by more than 99% when compared to the MOSRA-based approach, and accurate predictions of the statistical properties of aging are obtained with an accuracy of more than 99% on complementary metal oxide semiconductor (CMOS) and metal gate/high-K (MGK) circuits at the 22nm technology node.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135586825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fabio Silva, Rodrigo Trevisoli Dória, Eddy Simoen, Maria G. C. Andrade
It has been verified through numerical simulations calibrated to experimental data the changes that the insertion of a germanium layer can bring to the electrical power generation of a silicon solar cell. The insertion of a germanium layer on top or below a silicon PIN diode designed in SOI technology has been considered. Results showed that different semiconductor characteristics (bandgap, mobility, and absorption coefficients) result in a general improvement in the solar cell performance, being able to reach a power 136% greater than the device without the heterogeneous layer. In the evaluated device the average power was improved from 9.43 nW to 14.92 nW with the Ge layer insertion. Besides that, the analysis has allowed for a better understanding of the phenomena that occur in the photogeneration of a cell with a heterojunction between germanium and silicon.
{"title":"Lateral PIN Photodiode with Germanium and Silicon Layer on SOI Wafers","authors":"Fabio Silva, Rodrigo Trevisoli Dória, Eddy Simoen, Maria G. C. Andrade","doi":"10.29292/jics.v18i2.746","DOIUrl":"https://doi.org/10.29292/jics.v18i2.746","url":null,"abstract":"It has been verified through numerical simulations calibrated to experimental data the changes that the insertion of a germanium layer can bring to the electrical power generation of a silicon solar cell. The insertion of a germanium layer on top or below a silicon PIN diode designed in SOI technology has been considered. Results showed that different semiconductor characteristics (bandgap, mobility, and absorption coefficients) result in a general improvement in the solar cell performance, being able to reach a power 136% greater than the device without the heterogeneous layer. In the evaluated device the average power was improved from 9.43 nW to 14.92 nW with the Ge layer insertion. Besides that, the analysis has allowed for a better understanding of the phenomena that occur in the photogeneration of a cell with a heterojunction between germanium and silicon.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135586827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. H. Duarte, Ricardo Cardoso Rangel, D. A. Ramos, Leonardo Shimizu Yojo, Carlos Augusto Bergfeld Mori, K. Sasaki, Paula Ghedini Der Agopian, J. Martino
This work presents the Ion-Sensitive Field Effect Transistor (ISFET) fabrication and electrical characterization for hydrogen peroxide sensing. Two configurations were set up to evaluate the devices sensitivity to the concentration of the solution. First, measurements with one electrode in the sample solution (contained over the gate area) were performed, but the results may not be directly related to the characteristics of the solution, due to the prevalence of secondary effects. The second method, using two electrodes in the sample solution, shows a higher sensitivity at increasing hydrogen peroxide concentrations, in smallest intervals when compared to measurements with one electrode.
{"title":"ISFET Fabrication and Characterization for Hydrogen Peroxide sensing","authors":"P. H. Duarte, Ricardo Cardoso Rangel, D. A. Ramos, Leonardo Shimizu Yojo, Carlos Augusto Bergfeld Mori, K. Sasaki, Paula Ghedini Der Agopian, J. Martino","doi":"10.29292/jics.v18i1.646","DOIUrl":"https://doi.org/10.29292/jics.v18i1.646","url":null,"abstract":"This work presents the Ion-Sensitive Field Effect Transistor (ISFET) fabrication and electrical characterization for hydrogen peroxide sensing. Two configurations were set up to evaluate the devices sensitivity to the concentration of the solution. First, measurements with one electrode in the sample solution (contained over the gate area) were performed, but the results may not be directly related to the characteristics of the solution, due to the prevalence of secondary effects. The second method, using two electrodes in the sample solution, shows a higher sensitivity at increasing hydrogen peroxide concentrations, in smallest intervals when compared to measurements with one electrode.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49384125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Lucas Almir dos Santos Fernandes, Marco Isaías Alayo Chávez, J. Martino
In this work, an experimental implementation of a Fractional-order MOS capacitor using a fractal tree structure in discrete circuits was carried out in order to validate the theoretical results obtained of the simulations. In addition, a Monte Carlo analysis was performed to determine the sensitivity of the electrical circuit to the variation of some parameters.In these analyzes were observed that for a tolerance of 20% in the device values and for 2σ above and below the median values(for both, width, and initial frequency value of fractal zone) it is noticed a deviation of 18% and -14%, respectively, which is areasonable deviation for a group that contains more than 90% of the samples.
{"title":"Fractional-Order MOS Capacitor: Experimental Results and Monte Carlo Analysis","authors":"Lucas Almir dos Santos Fernandes, Marco Isaías Alayo Chávez, J. Martino","doi":"10.29292/jics.v18i1.660","DOIUrl":"https://doi.org/10.29292/jics.v18i1.660","url":null,"abstract":"In this work, an experimental implementation of a Fractional-order MOS capacitor using a fractal tree structure in discrete circuits was carried out in order to validate the theoretical results obtained of the simulations. In addition, a Monte Carlo analysis was performed to determine the sensitivity of the electrical circuit to the variation of some parameters.In these analyzes were observed that for a tolerance of 20% in the device values and for 2σ above and below the median values(for both, width, and initial frequency value of fractal zone) it is noticed a deviation of 18% and -14%, respectively, which is areasonable deviation for a group that contains more than 90% of the samples.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43227168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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