Pub Date : 2019-08-01DOI: 10.1109/SBMicro.2019.8919304
L. d'Oliveira, V. Kilchytska, D. Flandre, M. Souza
This paper presents an analysis of the harmonic distortion extracted from simulated results of symmetric and asymmetric self-cascode devices (S-SC and A-SC, respectively) composed by ultra-thin body and BOX fully depleted silicon-on-insulator planar MOSFETs 28 nm technological node. The results show that the A-SC effectively increases the operating drain current range for lower distortion. Comparisons with the literature show that the A-SC structures are a promising option for enhancing the circuit design flexibility for advanced MOSFETs.
{"title":"Harmonic Distortion in Symmetric and Asymmetric Self-Cascodes of UTBB FD SOI Planar MOSFETs","authors":"L. d'Oliveira, V. Kilchytska, D. Flandre, M. Souza","doi":"10.1109/SBMicro.2019.8919304","DOIUrl":"https://doi.org/10.1109/SBMicro.2019.8919304","url":null,"abstract":"This paper presents an analysis of the harmonic distortion extracted from simulated results of symmetric and asymmetric self-cascode devices (S-SC and A-SC, respectively) composed by ultra-thin body and BOX fully depleted silicon-on-insulator planar MOSFETs 28 nm technological node. The results show that the A-SC effectively increases the operating drain current range for lower distortion. Comparisons with the literature show that the A-SC structures are a promising option for enhancing the circuit design flexibility for advanced MOSFETs.","PeriodicalId":403446,"journal":{"name":"2019 34th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122728550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/SBMicro.2019.8919485
P. Pereira, G. M. Penello, M. Pires, M. Helm, H. Schneider, P. L. Souza
We have investigated the influence of the position of the dopants and the number of Bragg mirrors in the confinement of localized states in the continuum of a InGaAs/InAlAs superlattice with a structural defect. The potential profile of the conduction band of the superlattice was determined by self-consistently solving the Schrödinger-Poisson equations. The influence of these parameters was analyzed by the oscillator strength of the optical transition between the ground state and the first localized state in the continuum. The best location for the dopants is in the structural defect quantum well, for which an oscillator strength of 0.25 was obtained. It is found that two Bragg mirrors are enough to confine the first localized state in the continuum without decreasing the oscillator strength of the optical transition from the ground state.
{"title":"Effect of the dopant location and the number of Bragg mirrors on the performance of superlattice infrared photodetectors","authors":"P. Pereira, G. M. Penello, M. Pires, M. Helm, H. Schneider, P. L. Souza","doi":"10.1109/SBMicro.2019.8919485","DOIUrl":"https://doi.org/10.1109/SBMicro.2019.8919485","url":null,"abstract":"We have investigated the influence of the position of the dopants and the number of Bragg mirrors in the confinement of localized states in the continuum of a InGaAs/InAlAs superlattice with a structural defect. The potential profile of the conduction band of the superlattice was determined by self-consistently solving the Schrödinger-Poisson equations. The influence of these parameters was analyzed by the oscillator strength of the optical transition between the ground state and the first localized state in the continuum. The best location for the dopants is in the structural defect quantum well, for which an oscillator strength of 0.25 was obtained. It is found that two Bragg mirrors are enough to confine the first localized state in the continuum without decreasing the oscillator strength of the optical transition from the ground state.","PeriodicalId":403446,"journal":{"name":"2019 34th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131198657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/SBMicro.2019.8919464
E. T. Fonte, R. Trevisoli, R. Doria
A study of Junctionless Nanowire Transistors (JNTs) is presented in this work, with emphasis on verifying the applicability of the charge pumping method for the analysis of interface traps. To the best of our knowledge, this is the first work to use this method in JNTs. The first step is the analysis of the performance using numerical simulations. It is stated that a transient current is observed in the devices with the charge pumping method application and increases with the trap density. Simulated and experimental data of Junctionless Nanowire Transistors show how this method can be useful and its applicability to verify the JNTs interface quality.
{"title":"Applicability of Charge Pumping Technique for Evaluating the Effect of Interface Traps in Junctionless Nanowire Transistors","authors":"E. T. Fonte, R. Trevisoli, R. Doria","doi":"10.1109/SBMicro.2019.8919464","DOIUrl":"https://doi.org/10.1109/SBMicro.2019.8919464","url":null,"abstract":"A study of Junctionless Nanowire Transistors (JNTs) is presented in this work, with emphasis on verifying the applicability of the charge pumping method for the analysis of interface traps. To the best of our knowledge, this is the first work to use this method in JNTs. The first step is the analysis of the performance using numerical simulations. It is stated that a transient current is observed in the devices with the charge pumping method application and increases with the trap density. Simulated and experimental data of Junctionless Nanowire Transistors show how this method can be useful and its applicability to verify the JNTs interface quality.","PeriodicalId":403446,"journal":{"name":"2019 34th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129313561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/SBMicro.2019.8919320
E. Galembeck, J. Swart, Gabriel Augusto da Silva, S. Gimenez
This paper performs an experimental comparative study of a huge variation of temperature influence (from 300K to 573K) in planar Metal-Oxide-Semiconductor (MOS) Field-Effect-Transistors (MOSFETs), which are implemented with the octagonal (Octo MOSFETs, OM) and rectangular (Rectangular MOSFETs, RM) layout styles, regarding the same bias conditions. The devices were manufactured regarding a Complementary MOS (CMOS) Integrated Circuits (ICs) manufacturing process of 180 nm. The main results have shown that the OM is capable of keeping active the Longitudinal Corner Effect (LCE) and PArallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), which are intrinsic present in its structure, resulting a higher electrical performing in the relation to their RM counterparts, such as the OM saturation drain current (IDS_SAT) and transconductance (gm) are approximately three and two times, respectively, better as compared to those found in its RM counterpart. Therefore, the octagonal layout style for MOSFETs can be considered an alternative layout strategy to boost the electrical performance of the MOSFETs, without causing any additional burden to the CMOS ICs manufacturing process.
{"title":"Boosting the Performance of MOSFET Operating Under a Huge Range of High Temperature by Using the Octagonal Layout Style","authors":"E. Galembeck, J. Swart, Gabriel Augusto da Silva, S. Gimenez","doi":"10.1109/SBMicro.2019.8919320","DOIUrl":"https://doi.org/10.1109/SBMicro.2019.8919320","url":null,"abstract":"This paper performs an experimental comparative study of a huge variation of temperature influence (from 300K to 573K) in planar Metal-Oxide-Semiconductor (MOS) Field-Effect-Transistors (MOSFETs), which are implemented with the octagonal (Octo MOSFETs, OM) and rectangular (Rectangular MOSFETs, RM) layout styles, regarding the same bias conditions. The devices were manufactured regarding a Complementary MOS (CMOS) Integrated Circuits (ICs) manufacturing process of 180 nm. The main results have shown that the OM is capable of keeping active the Longitudinal Corner Effect (LCE) and PArallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), which are intrinsic present in its structure, resulting a higher electrical performing in the relation to their RM counterparts, such as the OM saturation drain current (IDS_SAT) and transconductance (gm) are approximately three and two times, respectively, better as compared to those found in its RM counterpart. Therefore, the octagonal layout style for MOSFETs can be considered an alternative layout strategy to boost the electrical performance of the MOSFETs, without causing any additional burden to the CMOS ICs manufacturing process.","PeriodicalId":403446,"journal":{"name":"2019 34th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128648367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/SBMicro.2019.8919372
Taiza A. Neves, Taiane C. Neves, H. Boudinov
Al/PVA/Ni and Al/PVA/P3HT/Ni capacitors were fabricated in this work. PVA capacitors were prepared by spin coating of water solution on top of Ni layer deposited by sputtering on glass plates. For the PVA/P3HT capacitors region-regular P3HT was dissolved in chlorobenzene and deposited by spin coating on similar Ni/glass substrates. After annealing the PVA solution was deposited. Aluminum circular contacts were evaporated through a mechanical mask. I-V and C-V measurements at different temperatures were performed. Difference in the electric field distribution from accumulation to depletion state in Al/PVA/P3HT/Ni structure was used to explain the data. The methodology used for this study proved to be successful in the sense of comparing the dielectric properties of PVA and P3HT considering the differences between Al/PVA/Ni and Al/PVA/P3HT/Ni capacitors.
{"title":"Electrical Characterization of Al/PVA/Ni and Al/PVA/P3HT/Ni Capacitors for Organic Electronics Applications","authors":"Taiza A. Neves, Taiane C. Neves, H. Boudinov","doi":"10.1109/SBMicro.2019.8919372","DOIUrl":"https://doi.org/10.1109/SBMicro.2019.8919372","url":null,"abstract":"Al/PVA/Ni and Al/PVA/P3HT/Ni capacitors were fabricated in this work. PVA capacitors were prepared by spin coating of water solution on top of Ni layer deposited by sputtering on glass plates. For the PVA/P3HT capacitors region-regular P3HT was dissolved in chlorobenzene and deposited by spin coating on similar Ni/glass substrates. After annealing the PVA solution was deposited. Aluminum circular contacts were evaporated through a mechanical mask. I-V and C-V measurements at different temperatures were performed. Difference in the electric field distribution from accumulation to depletion state in Al/PVA/P3HT/Ni structure was used to explain the data. The methodology used for this study proved to be successful in the sense of comparing the dielectric properties of PVA and P3HT considering the differences between Al/PVA/Ni and Al/PVA/P3HT/Ni capacitors.","PeriodicalId":403446,"journal":{"name":"2019 34th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114653390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/SBMicro.2019.8919346
Rogério C. B. L. Póvoa, P. Pereira, G. Torelly, D. Dias, G. M. Penello, M. Pires, B. Horta, P. L. Souza
We present a study of the use of evolutionary computation in the design of a new superlattice infrared photodetector (SLIP). Four optimization algorithms were used to find the parameters of the superlattice, specifically the thickness of the quantum wells and quantum barriers, which give the desired detection energy with the highest possible oscillator strength. The initial parameters for optimization are of a reference SLIP with detection energy and corresponding oscillator strength equal to 300 meV and 0.22, respectively. All optimization algorithms converged to a new superlattice with an oscillator strength around 0.35 for the same detection, a value 59% greater than the reference SLIP.
{"title":"Structural optimization of a superlattice infrared photodetector by evolutionary computation algorithms","authors":"Rogério C. B. L. Póvoa, P. Pereira, G. Torelly, D. Dias, G. M. Penello, M. Pires, B. Horta, P. L. Souza","doi":"10.1109/SBMicro.2019.8919346","DOIUrl":"https://doi.org/10.1109/SBMicro.2019.8919346","url":null,"abstract":"We present a study of the use of evolutionary computation in the design of a new superlattice infrared photodetector (SLIP). Four optimization algorithms were used to find the parameters of the superlattice, specifically the thickness of the quantum wells and quantum barriers, which give the desired detection energy with the highest possible oscillator strength. The initial parameters for optimization are of a reference SLIP with detection energy and corresponding oscillator strength equal to 300 meV and 0.22, respectively. All optimization algorithms converged to a new superlattice with an oscillator strength around 0.35 for the same detection, a value 59% greater than the reference SLIP.","PeriodicalId":403446,"journal":{"name":"2019 34th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127844967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/SBMicro.2019.8919309
W. G. Filho, J. Martino, P. Agopian
This work presents the behavior of Line Tunneling Field Effect Transistors (Line-TFET) at the saturation like region with different device's dimensions. In spite of the drain current and transconductance (gm) of the Line-TFET being proportional to the gate área (LgxW, with Lg: length and W:width), the output conductance (gd) is shown to be independent on the gate length at deep saturation. This unique behavior was observed experimentally and explained by numerical simulations. The conduction mechanisms are discussed and parasitic source to drain tunneling is found to be the main responsible for the output conductance value at the deep saturation like region, which doesn't depend upon Lg. Its impact on analog circuit design is also addressed, revealing fundamental differences of analog design using Line-TFET devices and MOSFET. It is revealed that if the designer wishes to increase the circuit voltage gain, this can be done by increasing the transconductance or the output resistance with Line-TFETs, as for MOSFETs only the latter option is available.
{"title":"Output conductance at saturation like region on Line-TFET for different dimensions","authors":"W. G. Filho, J. Martino, P. Agopian","doi":"10.1109/SBMicro.2019.8919309","DOIUrl":"https://doi.org/10.1109/SBMicro.2019.8919309","url":null,"abstract":"This work presents the behavior of Line Tunneling Field Effect Transistors (Line-TFET) at the saturation like region with different device's dimensions. In spite of the drain current and transconductance (gm) of the Line-TFET being proportional to the gate área (LgxW, with Lg: length and W:width), the output conductance (gd) is shown to be independent on the gate length at deep saturation. This unique behavior was observed experimentally and explained by numerical simulations. The conduction mechanisms are discussed and parasitic source to drain tunneling is found to be the main responsible for the output conductance value at the deep saturation like region, which doesn't depend upon Lg. Its impact on analog circuit design is also addressed, revealing fundamental differences of analog design using Line-TFET devices and MOSFET. It is revealed that if the designer wishes to increase the circuit voltage gain, this can be done by increasing the transconductance or the output resistance with Line-TFETs, as for MOSFETs only the latter option is available.","PeriodicalId":403446,"journal":{"name":"2019 34th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128029988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/SBMicro.2019.8919384
V. B. Sousa, P. Pereira, D. Sivco, C. Gmachl, G. M. Penello, M. Pires, P. L. Souza
We have developed a new dual color infrared photodetector based on an asymmetric multiple quantum well superlattice. Theoretical simulations on the asymmetric superlattices show that two different absorption energies will contribute to the current in opposite directions. Absorption measurements on grown structures are compared with theoretical absorption spectra and a good agreement is obtained.
{"title":"Dual Color Asymmetric Superlattice Infrared Photodetector","authors":"V. B. Sousa, P. Pereira, D. Sivco, C. Gmachl, G. M. Penello, M. Pires, P. L. Souza","doi":"10.1109/SBMicro.2019.8919384","DOIUrl":"https://doi.org/10.1109/SBMicro.2019.8919384","url":null,"abstract":"We have developed a new dual color infrared photodetector based on an asymmetric multiple quantum well superlattice. Theoretical simulations on the asymmetric superlattices show that two different absorption energies will contribute to the current in opposite directions. Absorption measurements on grown structures are compared with theoretical absorption spectra and a good agreement is obtained.","PeriodicalId":403446,"journal":{"name":"2019 34th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125204975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/SBMicro.2019.8919343
V. N. Hamanaka, Remco J. van Dasselaar, M. Hamanaka, N. L. Dias, V. L. Pimentel, M. C. Q. Bazetto, H. Aziz, F. Fonseca
In this work we show the project and fabrication of a home-made blade coating system for deposition of solutions of organic semiconductor materials. The system was used for deposition of PEDOT:PSS, a common hole injection material in solution based organic light emitting diodes (OLEDs). Phosphorescent OLEDs were assembled with PEDOT:PSS deposited by blade coating and also by spin coating for comparison. Both devices presented similar performance with low leakage current and driving voltages around 6 V (at 20 mA/cm2). The efficiency for both devices was very similar (EQE $sim$ 17%, at 20 mA/cm2) showing that the PEDOT:PSS film obtained by blade coating has similar hole injection properties and performance as the film deposited by spin coating.
{"title":"Blade Coating System for Organic Electronics","authors":"V. N. Hamanaka, Remco J. van Dasselaar, M. Hamanaka, N. L. Dias, V. L. Pimentel, M. C. Q. Bazetto, H. Aziz, F. Fonseca","doi":"10.1109/SBMicro.2019.8919343","DOIUrl":"https://doi.org/10.1109/SBMicro.2019.8919343","url":null,"abstract":"In this work we show the project and fabrication of a home-made blade coating system for deposition of solutions of organic semiconductor materials. The system was used for deposition of PEDOT:PSS, a common hole injection material in solution based organic light emitting diodes (OLEDs). Phosphorescent OLEDs were assembled with PEDOT:PSS deposited by blade coating and also by spin coating for comparison. Both devices presented similar performance with low leakage current and driving voltages around 6 V (at 20 mA/cm2). The efficiency for both devices was very similar (EQE $sim$ 17%, at 20 mA/cm2) showing that the PEDOT:PSS film obtained by blade coating has similar hole injection properties and performance as the film deposited by spin coating.","PeriodicalId":403446,"journal":{"name":"2019 34th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128741745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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