Pub Date : 2018-09-22DOI: 10.1109/ESTC.2006.280114
J. Morris
Nanotechnologies are being applied to microelectronics packaging, primarily in the applications of nanoparticle nanocomposites, or in the exploitation of the superior mechanical, electrical, or thermal properties of carbon nanotubes. Composite materials are studied for high-k dielectrics, electrically conductive adhesives, conductive "inks," underfill fillers, and solder enhancement. These trends are demonstrated by paper presentations over the past few years at ECTC and other conferences, which show research to be concentrated in relatively few laboratories, with little work being done on the packaging requirements of the new nanoelectronics technologies. Future needs (predictably) include education and software development
{"title":"Nanopackaging: nanotechnologies and electronics packaging","authors":"J. Morris","doi":"10.1109/ESTC.2006.280114","DOIUrl":"https://doi.org/10.1109/ESTC.2006.280114","url":null,"abstract":"Nanotechnologies are being applied to microelectronics packaging, primarily in the applications of nanoparticle nanocomposites, or in the exploitation of the superior mechanical, electrical, or thermal properties of carbon nanotubes. Composite materials are studied for high-k dielectrics, electrically conductive adhesives, conductive \"inks,\" underfill fillers, and solder enhancement. These trends are demonstrated by paper presentations over the past few years at ECTC and other conferences, which show research to be concentrated in relatively few laboratories, with little work being done on the packaging requirements of the new nanoelectronics technologies. Future needs (predictably) include education and software development","PeriodicalId":406794,"journal":{"name":"Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, 2006. HDP'06.","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132032486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-09DOI: 10.1109/HDP.2006.1707613
Xia Jun, Sang Wen-bin, Qian Yong-biao, Min Jiahua, T. Jianyong, L. Xiaoyan
CdZnTe (CZT) capacitive Frisch grid detector has increasingly captured the recent research interests in room temperature gamma-ray detection applications. The geometrical parameters of the detector have an important role in improving the detector performance. In this paper, the design parameters were optimized through finite element simulation, based on a 3-dimensional weighting potential analysis. The optimized parameters with a ratio of L/H of about 80% and d/8r <0.1mm were obtained. In addition, for the same ratio of L/H and d/er, model B with 5times5times10 mm3 could get better performance than model A with 8times8times10mm3
{"title":"Simulation design of capacitive Frisch grid CdZnTe detectors","authors":"Xia Jun, Sang Wen-bin, Qian Yong-biao, Min Jiahua, T. Jianyong, L. Xiaoyan","doi":"10.1109/HDP.2006.1707613","DOIUrl":"https://doi.org/10.1109/HDP.2006.1707613","url":null,"abstract":"CdZnTe (CZT) capacitive Frisch grid detector has increasingly captured the recent research interests in room temperature gamma-ray detection applications. The geometrical parameters of the detector have an important role in improving the detector performance. In this paper, the design parameters were optimized through finite element simulation, based on a 3-dimensional weighting potential analysis. The optimized parameters with a ratio of L/H of about 80% and d/8r <0.1mm were obtained. In addition, for the same ratio of L/H and d/er, model B with 5times5times10 mm3 could get better performance than model A with 8times8times10mm3","PeriodicalId":406794,"journal":{"name":"Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, 2006. HDP'06.","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122152121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-27DOI: 10.1109/HDP.2006.1707565
D. Zhou, T. Y. Hin, K. Tan, B. H. Oh
This paper describes the thermal-mechanical solutions for a community personal computer (PC), which is developed for rural Indian communities where the harsh living environment always poses the reliability challenge to maintain a conventional personal computer. The thermal-mechanical solution for micro-flip chip ball grid array (FCBGA) packaged CPU is presented and followed by the system level thermal, acoustic, dust-sand-insect protected solutions at 45 degC external ambient and dusty-sandy environment. To achieve better system acoustic performance, the system fan speed control (FSC) scheme is developed. Additionally, a dust-sand-insect filter is developed for the system which can protect dust, sand or insect no smaller than 1 mm from the inside chassis. The thermal simulation and structural analysis results agree well with the corresponding validation data. Also, the acoustic measurement data indicates the system acoustic targets can be met with the FSC scheme
{"title":"Design and development of thermal-mechanical solutions for a community personal computer","authors":"D. Zhou, T. Y. Hin, K. Tan, B. H. Oh","doi":"10.1109/HDP.2006.1707565","DOIUrl":"https://doi.org/10.1109/HDP.2006.1707565","url":null,"abstract":"This paper describes the thermal-mechanical solutions for a community personal computer (PC), which is developed for rural Indian communities where the harsh living environment always poses the reliability challenge to maintain a conventional personal computer. The thermal-mechanical solution for micro-flip chip ball grid array (FCBGA) packaged CPU is presented and followed by the system level thermal, acoustic, dust-sand-insect protected solutions at 45 degC external ambient and dusty-sandy environment. To achieve better system acoustic performance, the system fan speed control (FSC) scheme is developed. Additionally, a dust-sand-insect filter is developed for the system which can protect dust, sand or insect no smaller than 1 mm from the inside chassis. The thermal simulation and structural analysis results agree well with the corresponding validation data. Also, the acoustic measurement data indicates the system acoustic targets can be met with the FSC scheme","PeriodicalId":406794,"journal":{"name":"Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, 2006. HDP'06.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127181470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-27DOI: 10.1109/HDP.2006.1707612
T. Jianyong, Sang Wen-bin, Qin Kaifeng, Min Jiahua, Xia Jun
The characteristics of the Au contacts deposited by three different processes before and after accelerating aging tests have been investigated in this paper. The experimental results indicate that the aging tests can cause the degradation of the contact interfacial properties, such as continuities, adhesion strength and ohmic characteristics, especially for the contact interface deposited by the thermal vacuum processing, which would influence the performance of CdZnTe detectors
{"title":"Failure analysis of the CdZnTe detector electrode contacts","authors":"T. Jianyong, Sang Wen-bin, Qin Kaifeng, Min Jiahua, Xia Jun","doi":"10.1109/HDP.2006.1707612","DOIUrl":"https://doi.org/10.1109/HDP.2006.1707612","url":null,"abstract":"The characteristics of the Au contacts deposited by three different processes before and after accelerating aging tests have been investigated in this paper. The experimental results indicate that the aging tests can cause the degradation of the contact interfacial properties, such as continuities, adhesion strength and ohmic characteristics, especially for the contact interface deposited by the thermal vacuum processing, which would influence the performance of CdZnTe detectors","PeriodicalId":406794,"journal":{"name":"Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, 2006. HDP'06.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125512352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-27DOI: 10.1109/HDP.2006.1707603
Guh-Yaw Jang, Jenq-Gong Dun, S. Tsai, Chi-Rung Lee
Cu/electroless Ni/immersion Au metallization is usually used as bonding pad on the substrate side of flip chip solder joints. Sn-Ag-Cu solder is one of the promising candidates to replace the conventional Sn-Pb solder. Isothermal interfacial reaction in Sn-3.0Ag-(0.5 or 1.5)Cu solder joints with electroless Ni/immersion Au surface finish after aging at 150degC was investigated in this study. Intermetallic compounds (IMC) of (Cu1-y,Niy)6Sn5 , (Ni1-x,Cux)3Sn4 and P-rich layer formed between the solder and the EN layer in both Sn-Ag-Cu joints during aging. For the Sn-3.0Ag-0.5Cu joints after more than 2000 h aging, (Ni1-x,Cux)3Sn4 IMC gradually grew. Through the investigation of cross-sectional microstructural observation and quantitative analysis, the interfacial microstructure and the elemental distribution between the solder and bonding pad could be clearly revealed. It was demonstrated that Cu content in the solders near the solder/IMC interface played an important role in the growth of (Ni1-x,Cux)3Sn 4 and (Cu1-y,Nix)6Sn5
{"title":"Role of Cu contents in the isothermal metallurgical reaction for the flip chip Sn-3.0Ag-[0.5 or 1.5]Cu joints with Cu/electroless Ni-P/immersion Au bonding pad during aging","authors":"Guh-Yaw Jang, Jenq-Gong Dun, S. Tsai, Chi-Rung Lee","doi":"10.1109/HDP.2006.1707603","DOIUrl":"https://doi.org/10.1109/HDP.2006.1707603","url":null,"abstract":"Cu/electroless Ni/immersion Au metallization is usually used as bonding pad on the substrate side of flip chip solder joints. Sn-Ag-Cu solder is one of the promising candidates to replace the conventional Sn-Pb solder. Isothermal interfacial reaction in Sn-3.0Ag-(0.5 or 1.5)Cu solder joints with electroless Ni/immersion Au surface finish after aging at 150degC was investigated in this study. Intermetallic compounds (IMC) of (Cu<sub>1-y</sub>,Ni<sub>y</sub>)<sub>6</sub>Sn<sub>5 </sub>, (Ni<sub>1-x</sub>,Cu<sub>x</sub>)<sub>3</sub>Sn<sub>4</sub> and P-rich layer formed between the solder and the EN layer in both Sn-Ag-Cu joints during aging. For the Sn-3.0Ag-0.5Cu joints after more than 2000 h aging, (Ni<sub>1-x</sub>,Cu<sub>x</sub>)<sub>3</sub>Sn<sub>4</sub> IMC gradually grew. Through the investigation of cross-sectional microstructural observation and quantitative analysis, the interfacial microstructure and the elemental distribution between the solder and bonding pad could be clearly revealed. It was demonstrated that Cu content in the solders near the solder/IMC interface played an important role in the growth of (Ni<sub>1-x</sub>,Cu<sub>x</sub>)<sub>3</sub>Sn <sub>4</sub> and (Cu<sub>1-y</sub>,Ni<sub>x</sub>)<sub>6</sub>Sn<sub>5 </sub>","PeriodicalId":406794,"journal":{"name":"Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, 2006. HDP'06.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122651731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-27DOI: 10.1109/HDP.2006.1707573
Chen Dong-fan, Zhou Lincan
With the background of SMT products manufacturing enterprises, we have probed into the manufacturing and managing mode of the SMT enterprises on the basis of the manufacturing execution system (MES) theory. According to the research on the manufacturing facilities and technological process of typical SMT manufacturing enterprises, some potential major problems are discovered in the application of MES to the SMT enterprises. Thus, a relatively consummate resolution to the systematic function is proposed. Furthermore, a brief introduction is made on the main module of this kind of MES system
{"title":"Research on manufacturing execution system for the SMT industry","authors":"Chen Dong-fan, Zhou Lincan","doi":"10.1109/HDP.2006.1707573","DOIUrl":"https://doi.org/10.1109/HDP.2006.1707573","url":null,"abstract":"With the background of SMT products manufacturing enterprises, we have probed into the manufacturing and managing mode of the SMT enterprises on the basis of the manufacturing execution system (MES) theory. According to the research on the manufacturing facilities and technological process of typical SMT manufacturing enterprises, some potential major problems are discovered in the application of MES to the SMT enterprises. Thus, a relatively consummate resolution to the systematic function is proposed. Furthermore, a brief introduction is made on the main module of this kind of MES system","PeriodicalId":406794,"journal":{"name":"Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, 2006. HDP'06.","volume":"214 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114371662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-27DOI: 10.1109/HDP.2006.1707585
A. Huynh, P. Håkansson, Shaofang Gong, Leif Odselius
This paper presents a board-to-board interconnect technique utilizing elastomeric connectors and parallel microstrip lines on a flexible foil cable with low dielectric loss (tandelta = 0.002). It is shown that a pad structure combined with an elastomeric connector can be co-designed such that a good signal integrity and thus a high data transmission rate is achieved. It is also shown that 2 Gbps data transmission rate can be achieved with a 490-mm-long microstrip on the flexible cable, where crosstalk is taken into account. Utilizing the elastomeric connector together with the flat and flexible cable, dense parallel microstrips can easily be designed and processed since standard printed circuit board processing techniques can be utilized
{"title":"High-speed board-to-board interconnects utilizing flexible foils and elastomeric connectors","authors":"A. Huynh, P. Håkansson, Shaofang Gong, Leif Odselius","doi":"10.1109/HDP.2006.1707585","DOIUrl":"https://doi.org/10.1109/HDP.2006.1707585","url":null,"abstract":"This paper presents a board-to-board interconnect technique utilizing elastomeric connectors and parallel microstrip lines on a flexible foil cable with low dielectric loss (tandelta = 0.002). It is shown that a pad structure combined with an elastomeric connector can be co-designed such that a good signal integrity and thus a high data transmission rate is achieved. It is also shown that 2 Gbps data transmission rate can be achieved with a 490-mm-long microstrip on the flexible cable, where crosstalk is taken into account. Utilizing the elastomeric connector together with the flat and flexible cable, dense parallel microstrips can easily be designed and processed since standard printed circuit board processing techniques can be utilized","PeriodicalId":406794,"journal":{"name":"Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, 2006. HDP'06.","volume":"25 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114100268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-27DOI: 10.1109/HDP.2006.1707576
Yan Zhang, R. Larsson, Jing-yu Fan, Z. Cheng, Johan Liu
The increase in microsystem packaging density sets the requirement for component sizes in the system to become smaller and smaller. The scale decrease makes the analysis more complicated as the corresponding resolution should be improved to a great extent. Interconnection in the system is a typical interface structure that widely appear in the packaging system, in which periodic microstructures may be included inside. A homogenization model is developed in this paper, which focuses on the interface behavior. The interface model based on micropolar theory provides a natural way to include the characteristic scale that can reflect the size effect of the considered structure. Computations are carried out as the numerical example of the model, and comparisons of this model with those of the conventional method show its validity and efficiency
{"title":"Homogenization model based on micropolar theory for the interconnection layer in microsystem packaging","authors":"Yan Zhang, R. Larsson, Jing-yu Fan, Z. Cheng, Johan Liu","doi":"10.1109/HDP.2006.1707576","DOIUrl":"https://doi.org/10.1109/HDP.2006.1707576","url":null,"abstract":"The increase in microsystem packaging density sets the requirement for component sizes in the system to become smaller and smaller. The scale decrease makes the analysis more complicated as the corresponding resolution should be improved to a great extent. Interconnection in the system is a typical interface structure that widely appear in the packaging system, in which periodic microstructures may be included inside. A homogenization model is developed in this paper, which focuses on the interface behavior. The interface model based on micropolar theory provides a natural way to include the characteristic scale that can reflect the size effect of the considered structure. Computations are carried out as the numerical example of the model, and comparisons of this model with those of the conventional method show its validity and efficiency","PeriodicalId":406794,"journal":{"name":"Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, 2006. HDP'06.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132100279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-27DOI: 10.1109/HDP.2006.1707595
Xu Wang, Z. Cheng, Johan Liu
Anisotropic conductive adhesives (ACAs) have been proved to own good performance in high frequency applications. However, the effect of distribution of conductive particles in ACAs on RF (radio frequency) characterization is not fully understood. Finite difference in time domain (FDTD) method based electromagnetic software QuickWave is used to establish the structure and investigate RF characterization of ACA. The effect of distribution of conductive particles both in random and uniform distribution is simulated. Furthermore, the influence of conductor overlap is also investigated. An equivalent lumped circuit is also set up. The results show in a certain particles number, that there is minor influence in different distribution of conductive particles, and that as expected, the conductor overlap should be minimized to improve high frequency performance
{"title":"RF characterization of flip-chip anisotropic conductive adhesives joints","authors":"Xu Wang, Z. Cheng, Johan Liu","doi":"10.1109/HDP.2006.1707595","DOIUrl":"https://doi.org/10.1109/HDP.2006.1707595","url":null,"abstract":"Anisotropic conductive adhesives (ACAs) have been proved to own good performance in high frequency applications. However, the effect of distribution of conductive particles in ACAs on RF (radio frequency) characterization is not fully understood. Finite difference in time domain (FDTD) method based electromagnetic software QuickWave is used to establish the structure and investigate RF characterization of ACA. The effect of distribution of conductive particles both in random and uniform distribution is simulated. Furthermore, the influence of conductor overlap is also investigated. An equivalent lumped circuit is also set up. The results show in a certain particles number, that there is minor influence in different distribution of conductive particles, and that as expected, the conductor overlap should be minimized to improve high frequency performance","PeriodicalId":406794,"journal":{"name":"Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, 2006. HDP'06.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133236278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-27DOI: 10.1109/HDP.2006.1707563
Kar Mun Ng, K. R. Shah
A standard modeling method to represent conduction in motherboard (MB) for predicting a ball-grid array package temperature is developed. It is shown that discrete representation of individual copper and FR4 layers within MB rather than an effective block is needed for accurate thermal prediction. The MB signal layers consists of set of parallel copper traces and are represented by orthotropic layer to capture direction-sensitive thermal conduction along the traces. The role of through-hole vias in MB is captured by augmenting the through-plane conductivity of FR4 layers. The methodology uses a set of prismatic and/or polygon blocks with orthotropic thermal conductivities and can be implemented in existing computational fluid dynamic (CFD) and heat transfer tools. A MB-level test set-up is developed to validate the proposed modeling methodology under a range of airflow conditions and it is shown that the model results match the test data with maximum error of 14%
{"title":"Motherboard heat transfer modeling methodology","authors":"Kar Mun Ng, K. R. Shah","doi":"10.1109/HDP.2006.1707563","DOIUrl":"https://doi.org/10.1109/HDP.2006.1707563","url":null,"abstract":"A standard modeling method to represent conduction in motherboard (MB) for predicting a ball-grid array package temperature is developed. It is shown that discrete representation of individual copper and FR4 layers within MB rather than an effective block is needed for accurate thermal prediction. The MB signal layers consists of set of parallel copper traces and are represented by orthotropic layer to capture direction-sensitive thermal conduction along the traces. The role of through-hole vias in MB is captured by augmenting the through-plane conductivity of FR4 layers. The methodology uses a set of prismatic and/or polygon blocks with orthotropic thermal conductivities and can be implemented in existing computational fluid dynamic (CFD) and heat transfer tools. A MB-level test set-up is developed to validate the proposed modeling methodology under a range of airflow conditions and it is shown that the model results match the test data with maximum error of 14%","PeriodicalId":406794,"journal":{"name":"Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, 2006. HDP'06.","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133811137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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