Pub Date : 2006-06-27DOI: 10.1109/ICIIS.2006.365759
C. Chen, M. G. Nejad, L. Zheng
This paper is an investigation of off-chip solution of power converters for passive UHF RFID transponders. The power converter, consisting of a chain of Schottky diodes and capacitors, is designed and then implemented on Rogers4350 PCB substrate. The ISM unlicensed frequency bands 915 MHz is used for RF signal. The de-embedded measurement results show that with minimum input power of -4.7dBm, the power converter achieves 1.8V/5muA output driving capability, which is sufficient for the transponder operation. It corresponds to a 3.6m operating distance when 4-W EIRP radiation is allowed
{"title":"Design and implementation of a high efficient power converter for self-powered UHF RFID applications","authors":"C. Chen, M. G. Nejad, L. Zheng","doi":"10.1109/ICIIS.2006.365759","DOIUrl":"https://doi.org/10.1109/ICIIS.2006.365759","url":null,"abstract":"This paper is an investigation of off-chip solution of power converters for passive UHF RFID transponders. The power converter, consisting of a chain of Schottky diodes and capacitors, is designed and then implemented on Rogers4350 PCB substrate. The ISM unlicensed frequency bands 915 MHz is used for RF signal. The de-embedded measurement results show that with minimum input power of -4.7dBm, the power converter achieves 1.8V/5muA output driving capability, which is sufficient for the transponder operation. It corresponds to a 3.6m operating distance when 4-W EIRP radiation is allowed","PeriodicalId":406794,"journal":{"name":"Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, 2006. HDP'06.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129937840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-27DOI: 10.1109/HDP.2006.1707590
Y. Abe, K. Yamada, N. Abe, F. Tanaka, T. Fujiki
The miniaturization of flip-chip package is examined in many manufacturers. A thermal conductivity of underfill material has been regarded as important. Silica is contained in conventional under-fill as filler. Thermal conductivity of under-fill which contains silica filler is around 0.4W/mK. More than 1 W/mK of thermal conductivity is required for high thermally conductive under-fill. However, it is difficult to confirm if thermal conductivities are more than 1W/mK when silica is chosen as filler, since thermal conductivity of silica is about 1.3 W/mK. The various kinds of aluminum nitride were examined. High thermally conductive under-fill has been developed. It is filled with fine particle size aluminum nitride which will provide high thermal conductivity and good fluidity. And this under-fill realized over 2W/mK of thermal conductivity by control of loading level of the aluminum nitride filler. Also, this product satisfies the basic requirements for the under-fill, such as the JEDEC level 3 preconditioning test and temperature cycle test
{"title":"High thermally conductive and high reliability under-fill","authors":"Y. Abe, K. Yamada, N. Abe, F. Tanaka, T. Fujiki","doi":"10.1109/HDP.2006.1707590","DOIUrl":"https://doi.org/10.1109/HDP.2006.1707590","url":null,"abstract":"The miniaturization of flip-chip package is examined in many manufacturers. A thermal conductivity of underfill material has been regarded as important. Silica is contained in conventional under-fill as filler. Thermal conductivity of under-fill which contains silica filler is around 0.4W/mK. More than 1 W/mK of thermal conductivity is required for high thermally conductive under-fill. However, it is difficult to confirm if thermal conductivities are more than 1W/mK when silica is chosen as filler, since thermal conductivity of silica is about 1.3 W/mK. The various kinds of aluminum nitride were examined. High thermally conductive under-fill has been developed. It is filled with fine particle size aluminum nitride which will provide high thermal conductivity and good fluidity. And this under-fill realized over 2W/mK of thermal conductivity by control of loading level of the aluminum nitride filler. Also, this product satisfies the basic requirements for the under-fill, such as the JEDEC level 3 preconditioning test and temperature cycle test","PeriodicalId":406794,"journal":{"name":"Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, 2006. HDP'06.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130769873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-27DOI: 10.1109/HDP.2006.1707562
Hua Lu, D. Flynn, C. Bailey, M. Desmulliez
The results of a finite element computer modelling analysis of a micro-manufactured one-turn magnetic inductor using the software package ANSYS 10.0 are presented. The inductor is designed for a DC-DC converter used in microelectronic devices. It consists of a copper conductor with a rectangular cross-section plated with an insulation layer and a layer of magnetic core. The analysis has focused on the effects of the frequency and the air gaps on the on the inductance values and the Joule losses in the core and conductor. It has been found that an inductor with small multiple air gaps has lower losses than an inductor with a single larger gap
{"title":"Computer modeling of a micro-manufactured one-turn inductor","authors":"Hua Lu, D. Flynn, C. Bailey, M. Desmulliez","doi":"10.1109/HDP.2006.1707562","DOIUrl":"https://doi.org/10.1109/HDP.2006.1707562","url":null,"abstract":"The results of a finite element computer modelling analysis of a micro-manufactured one-turn magnetic inductor using the software package ANSYS 10.0 are presented. The inductor is designed for a DC-DC converter used in microelectronic devices. It consists of a copper conductor with a rectangular cross-section plated with an insulation layer and a layer of magnetic core. The analysis has focused on the effects of the frequency and the air gaps on the on the inductance values and the Joule losses in the core and conductor. It has been found that an inductor with small multiple air gaps has lower losses than an inductor with a single larger gap","PeriodicalId":406794,"journal":{"name":"Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, 2006. HDP'06.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128545896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-27DOI: 10.1109/HDP.2006.1707591
G. Izuta, T. Tanabe, J. Murai, M. Murakami, K. Suganuma
Solder joint separation of IC leads is caused by partial melting and displacement of a lead-free solder joint having Pb contamination in process of wave soldering after reflow soldering. An evaluation method of solder joint separation was developed by focusing on the vertical displacement of the joint, which is defined by IC package size and curvature of a printed circuit board (PCB). It has been clarified that the critical displacement causing the solder joint separation is 15 micrometers or less by the model experiment of wave soldering process. Based on the above data, a new in-process measurement tool of PCBs curvature in wave soldering has been developed. The results of practical wave soldering agree well with the model experiment values
{"title":"IC fillet-lifting mechanism on wave soldering after reflow soldering","authors":"G. Izuta, T. Tanabe, J. Murai, M. Murakami, K. Suganuma","doi":"10.1109/HDP.2006.1707591","DOIUrl":"https://doi.org/10.1109/HDP.2006.1707591","url":null,"abstract":"Solder joint separation of IC leads is caused by partial melting and displacement of a lead-free solder joint having Pb contamination in process of wave soldering after reflow soldering. An evaluation method of solder joint separation was developed by focusing on the vertical displacement of the joint, which is defined by IC package size and curvature of a printed circuit board (PCB). It has been clarified that the critical displacement causing the solder joint separation is 15 micrometers or less by the model experiment of wave soldering process. Based on the above data, a new in-process measurement tool of PCBs curvature in wave soldering has been developed. The results of practical wave soldering agree well with the model experiment values","PeriodicalId":406794,"journal":{"name":"Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, 2006. HDP'06.","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124324726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-27DOI: 10.1109/HDP.2006.1707586
Yin-Jung Chang, D. Guidotti, L. Wan, G. Chang
An opto/digital interconnect prototype for board-level 1times4 optical-to-digital signal broadcasting operating at 10 Gb/s per channel over an interconnect distance of 10 cm is demonstrated. An improved 1 times4 multimode interference (MMI) splitter at 1550 nm with linearly-tapered output facet is heterogeneously integrated with 4 p-i-n photodetectors (PDs) on a silicon (Si) bench. The Si bench itself is hybrid integrated onto an FR-4 printed-circuit board (PCB) with 4 receiver channels. A novel fabrication/integration approach demonstrates the capability of simultaneously aligning multiple polymer waveguides with multiple optoelectronic (OE) devices during the waveguide fabrication process. The combined excess loss of the MMI splitter and the mirror loss per channel is less than 3.5 dB and the entire system is fully functional at 10 Gb/s
{"title":"Hybrid interconnects using silicon/FR-4 substrates for board-level 10 Gb/s signal broadcasting","authors":"Yin-Jung Chang, D. Guidotti, L. Wan, G. Chang","doi":"10.1109/HDP.2006.1707586","DOIUrl":"https://doi.org/10.1109/HDP.2006.1707586","url":null,"abstract":"An opto/digital interconnect prototype for board-level 1times4 optical-to-digital signal broadcasting operating at 10 Gb/s per channel over an interconnect distance of 10 cm is demonstrated. An improved 1 times4 multimode interference (MMI) splitter at 1550 nm with linearly-tapered output facet is heterogeneously integrated with 4 p-i-n photodetectors (PDs) on a silicon (Si) bench. The Si bench itself is hybrid integrated onto an FR-4 printed-circuit board (PCB) with 4 receiver channels. A novel fabrication/integration approach demonstrates the capability of simultaneously aligning multiple polymer waveguides with multiple optoelectronic (OE) devices during the waveguide fabrication process. The combined excess loss of the MMI splitter and the mirror loss per channel is less than 3.5 dB and the entire system is fully functional at 10 Gb/s","PeriodicalId":406794,"journal":{"name":"Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, 2006. HDP'06.","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131639316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-27DOI: 10.1109/HDP.2006.1707588
Yulin Wang, Z. Xiong, X. Zou, H. Ding
It has been shown that diode laser soldering is suitable for electronic packaging especially for the rework of ball grid array (BGA) chips, because laser soldering technique for BGA packaging has several distinct advantages over conventional methods. In this study, we build an experimental prototype laser soldering workstation and have some researches on the laser bumping process. We first summarize researches and applications of laser soldering in electronics assembly in recent years. Then our diode laser soldering system is introduced. In order to study the influence of different parameters for obtaining a good solder joint, some experiments are carried out with a continuous-wave (CW) diode laser rating up to 2.4 watts on the soldering process. We study some key parameters including laser power, irradiation time, reflow height, the amount of flux and misalignment. Experimental results are compared and analyzed. In the end, optimized process parameters are given as a conclusion
{"title":"Experimental optimization of process parameters for diode laser soldering of BGA","authors":"Yulin Wang, Z. Xiong, X. Zou, H. Ding","doi":"10.1109/HDP.2006.1707588","DOIUrl":"https://doi.org/10.1109/HDP.2006.1707588","url":null,"abstract":"It has been shown that diode laser soldering is suitable for electronic packaging especially for the rework of ball grid array (BGA) chips, because laser soldering technique for BGA packaging has several distinct advantages over conventional methods. In this study, we build an experimental prototype laser soldering workstation and have some researches on the laser bumping process. We first summarize researches and applications of laser soldering in electronics assembly in recent years. Then our diode laser soldering system is introduced. In order to study the influence of different parameters for obtaining a good solder joint, some experiments are carried out with a continuous-wave (CW) diode laser rating up to 2.4 watts on the soldering process. We study some key parameters including laser power, irradiation time, reflow height, the amount of flux and misalignment. Experimental results are compared and analyzed. In the end, optimized process parameters are given as a conclusion","PeriodicalId":406794,"journal":{"name":"Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, 2006. HDP'06.","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122119254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-27DOI: 10.1109/HDP.2006.1707616
N. Gorman, R. Kay, I. Roney, M. Desmulliez
Summary form only given. The advances of chip scale packaging technologies have induced an increase of the density of solder joints in microelectronics products. Pitch sizes are consequently due to further decrease, leading to joint structures at sub 100mum dimensions. Stencil printing for wafer bumping with fine particle solder pastes is potentially a low-cost assembly solution for fine pitch solder joint interconnects. For ultra fine pitch applications stencil printing has been perceived to have reached its practical limits, in consequence a requirement to understand all the processes that impact on the performance of stencil printing at ultra fine pitch is needed. Paste roll, aperture filling & release, post print behaviour and paste open time need to be examined as experimental inputs, alongside the following parameters: fine particle Pb-free solder pastes and solder paste rheology, particle size distribution, metal content, flux type and stencil aperture attributes. The complexity in using stencil technology at such fine pitch geometries has indicated that the quality, consistency and yield are determined by a combination of variables that are involved in the stencil manufacture, paste formulation, and the print process performance of the paste from the stencil. With the WEEE and RoHS Directives being introduced to the electronics manufacturing industry we also have the change to Sn-Pb solders with Pb free alloys to consider. These changes in composition required for Pb free solder alloys and the behavioural changes caused by them during manufacturing processes mean that more process variables need to be understood. Along with the continual miniaturization in microelectronics, the number of variables and parameters that can be involved in stencil printing technology make tight process controls and consistent high yielding interconnects even more difficult to achieve. This paper will report on the advancements of stencil technology using novel micro-engineering techniques to achieve the quality required for printing at ultra fine pitches in terms of aperture tolerances, repeatability and side-wall smoothness. This study, coupled with the improvements in Pb free solder paste, shows that deposits can be produced at ultra fine pitch with types 6, 7 & 8 pastes. Tests also show that subtle differences in the performance of type-6 and type-7 and most recently type 8 mean that there should be careful selection of pastes made that are specific to application geometries. Investigations into the effects of different shaped aperture openings in the stencil also reveal that solder paste deposit volume can be controlled. Sufficient volumes of the fine particle solder paste are required during reflowing to obtain an adequate stand off between the flip chip device and substrate pad. Print consistency and uniformity of the bumps generated are also governed by the volume of solder paste for each deposit all of which will be shown to be more controllable with
{"title":"Design, manufacture and testing of microengineered stencils used for sub 100 micron wafer level bumping","authors":"N. Gorman, R. Kay, I. Roney, M. Desmulliez","doi":"10.1109/HDP.2006.1707616","DOIUrl":"https://doi.org/10.1109/HDP.2006.1707616","url":null,"abstract":"Summary form only given. The advances of chip scale packaging technologies have induced an increase of the density of solder joints in microelectronics products. Pitch sizes are consequently due to further decrease, leading to joint structures at sub 100mum dimensions. Stencil printing for wafer bumping with fine particle solder pastes is potentially a low-cost assembly solution for fine pitch solder joint interconnects. For ultra fine pitch applications stencil printing has been perceived to have reached its practical limits, in consequence a requirement to understand all the processes that impact on the performance of stencil printing at ultra fine pitch is needed. Paste roll, aperture filling & release, post print behaviour and paste open time need to be examined as experimental inputs, alongside the following parameters: fine particle Pb-free solder pastes and solder paste rheology, particle size distribution, metal content, flux type and stencil aperture attributes. The complexity in using stencil technology at such fine pitch geometries has indicated that the quality, consistency and yield are determined by a combination of variables that are involved in the stencil manufacture, paste formulation, and the print process performance of the paste from the stencil. With the WEEE and RoHS Directives being introduced to the electronics manufacturing industry we also have the change to Sn-Pb solders with Pb free alloys to consider. These changes in composition required for Pb free solder alloys and the behavioural changes caused by them during manufacturing processes mean that more process variables need to be understood. Along with the continual miniaturization in microelectronics, the number of variables and parameters that can be involved in stencil printing technology make tight process controls and consistent high yielding interconnects even more difficult to achieve. This paper will report on the advancements of stencil technology using novel micro-engineering techniques to achieve the quality required for printing at ultra fine pitches in terms of aperture tolerances, repeatability and side-wall smoothness. This study, coupled with the improvements in Pb free solder paste, shows that deposits can be produced at ultra fine pitch with types 6, 7 & 8 pastes. Tests also show that subtle differences in the performance of type-6 and type-7 and most recently type 8 mean that there should be careful selection of pastes made that are specific to application geometries. Investigations into the effects of different shaped aperture openings in the stencil also reveal that solder paste deposit volume can be controlled. Sufficient volumes of the fine particle solder paste are required during reflowing to obtain an adequate stand off between the flip chip device and substrate pad. Print consistency and uniformity of the bumps generated are also governed by the volume of solder paste for each deposit all of which will be shown to be more controllable with ","PeriodicalId":406794,"journal":{"name":"Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, 2006. HDP'06.","volume":"242 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122529474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-27DOI: 10.1109/HDP.2006.1707604
Cong‐qian Cheng, Peng Yang, Jie Zhao, Feng Zhu, Qing-Yang Song
The growth behaviors of Sn-3Ag/Cu and Sn/Cu IMC layers during soldering and aging have been investigated. In the soldering experiments, both the Sn-3Ag/Cu and Sn/Cu were soldered at 270 degC for different time. In the aging experiments, the Sn-3Ag/Cu and Sn/Cu joints were firstly soldered at 270 degC for 60s, and aged at 120 degC, 170 degC, 190 degC for various time. Then all the samples were observed under scanning electron microscopy (SEM). The average thickness of IMC layers was measured by using Q500IW image analysis meter. The results indicated that in the soldering the growth rate of Sn-3Ag/Cu IMC layers was faster than that of Sn/Cu. However, in the aging the growth rate of Sn-3Ag/Cu IMC layers was lower than that of Sn/Cu. The activation energies of Sn-3Ag/Cu and Sn/Cu IMC layers in the aging were about 90KJ/mol and 52KJ/mol respectively
{"title":"The growth behavior of intermetallic compound layers of Sn-3Ag / Cu and Sn/Cu joints during soldering and aging","authors":"Cong‐qian Cheng, Peng Yang, Jie Zhao, Feng Zhu, Qing-Yang Song","doi":"10.1109/HDP.2006.1707604","DOIUrl":"https://doi.org/10.1109/HDP.2006.1707604","url":null,"abstract":"The growth behaviors of Sn-3Ag/Cu and Sn/Cu IMC layers during soldering and aging have been investigated. In the soldering experiments, both the Sn-3Ag/Cu and Sn/Cu were soldered at 270 degC for different time. In the aging experiments, the Sn-3Ag/Cu and Sn/Cu joints were firstly soldered at 270 degC for 60s, and aged at 120 degC, 170 degC, 190 degC for various time. Then all the samples were observed under scanning electron microscopy (SEM). The average thickness of IMC layers was measured by using Q500IW image analysis meter. The results indicated that in the soldering the growth rate of Sn-3Ag/Cu IMC layers was faster than that of Sn/Cu. However, in the aging the growth rate of Sn-3Ag/Cu IMC layers was lower than that of Sn/Cu. The activation energies of Sn-3Ag/Cu and Sn/Cu IMC layers in the aging were about 90KJ/mol and 52KJ/mol respectively","PeriodicalId":406794,"journal":{"name":"Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, 2006. HDP'06.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115069363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-27DOI: 10.1109/HDP.2006.1707594
Yi Li, C. Wong
Although conductive adhesives have been studied for many years as a lead-free alternative in electronic industry, applications of electrically conductive adhesives (ECAs) for electronic interconnect are limited to low voltage display driver devices. This is due to the serious concerns associated with the long-term reliability and high voltage application issues caused by the silver migration. In this study, a novel approach to reduce silver migration and enhance the long-term reliability of conductive adhesives is discovered by using self-assembled monolayer molecular wires. The approach enhances the long-term reliability and durability of conductive adhesives and enables the ECA for high voltage applications. In addition, the self-assembled molecular wires help the dispersion of conductive fillers (in particular, nano-sized (<100 nm) conductive fillers) in the polymer matrix and enhance the electrical conductivity of conductive adhesives. Due to the high current density of those functional molecular monolayers, the current carrying capability of conductive adhesives can also be improved significantly
{"title":"Silver migration control in electrically conductive adhesives","authors":"Yi Li, C. Wong","doi":"10.1109/HDP.2006.1707594","DOIUrl":"https://doi.org/10.1109/HDP.2006.1707594","url":null,"abstract":"Although conductive adhesives have been studied for many years as a lead-free alternative in electronic industry, applications of electrically conductive adhesives (ECAs) for electronic interconnect are limited to low voltage display driver devices. This is due to the serious concerns associated with the long-term reliability and high voltage application issues caused by the silver migration. In this study, a novel approach to reduce silver migration and enhance the long-term reliability of conductive adhesives is discovered by using self-assembled monolayer molecular wires. The approach enhances the long-term reliability and durability of conductive adhesives and enables the ECA for high voltage applications. In addition, the self-assembled molecular wires help the dispersion of conductive fillers (in particular, nano-sized (<100 nm) conductive fillers) in the polymer matrix and enhance the electrical conductivity of conductive adhesives. Due to the high current density of those functional molecular monolayers, the current carrying capability of conductive adhesives can also be improved significantly","PeriodicalId":406794,"journal":{"name":"Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, 2006. HDP'06.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122144582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-27DOI: 10.1109/HDP.2006.1707598
Jie Zhao, Linge Qi, Lai Wang
Three lead-free solder alloys, Sn-3Ag-0.5Cu, Sn-3Ag-0.5Cu-1Bi and Sn-3Ag-0.5Cu-3Bi, were used in the current experiments to investigated the microstructural evolution as well as the kinetics of intermetallic compound (IMC) layer growth. The experimental results indicated that the thickness of Cu6Sn5 intermetallic layer at the solder/Cu interface increases with aging temperature, while the growth rate of IMC in Sn-3Ag-0.5Cu-3Bi/Cu joints is slower than that in Sn-3Ag-0.5Cu-1Bi/Cu joints and Sn-Ag-Cu solder joints. The effect of Bi element is attributed to the accumulation of Bi near the joint and the enhancement of the activation energy by the addition of Bi
{"title":"Effect of Bi on the kinetics of intermetallics growth in Sn-3Ag-0.5Cu/Cu solder joint","authors":"Jie Zhao, Linge Qi, Lai Wang","doi":"10.1109/HDP.2006.1707598","DOIUrl":"https://doi.org/10.1109/HDP.2006.1707598","url":null,"abstract":"Three lead-free solder alloys, Sn-3Ag-0.5Cu, Sn-3Ag-0.5Cu-1Bi and Sn-3Ag-0.5Cu-3Bi, were used in the current experiments to investigated the microstructural evolution as well as the kinetics of intermetallic compound (IMC) layer growth. The experimental results indicated that the thickness of Cu6Sn5 intermetallic layer at the solder/Cu interface increases with aging temperature, while the growth rate of IMC in Sn-3Ag-0.5Cu-3Bi/Cu joints is slower than that in Sn-3Ag-0.5Cu-1Bi/Cu joints and Sn-Ag-Cu solder joints. The effect of Bi element is attributed to the accumulation of Bi near the joint and the enhancement of the activation energy by the addition of Bi","PeriodicalId":406794,"journal":{"name":"Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, 2006. HDP'06.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114093438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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