Approximate computing is an emerging design technique for error-tolerant applications. As adders are the key building blocks in many applications, approximate adders have been widely studied recently. However, existing approximate adders may introduce sign bit error when doing two's complement signed addition, which is not tolerable for some applications. In this work, we propose a scheme that can correct sign bit error with low area and delay overhead. It is a general design applicable to many block-based approximate adders. This design not only can correct the sign bit error when it occurs, but also can fix some errors in the most significant bits even if there is no sign bit error. Experimental results on a real application, namely edge detection, showed that the approximate adders with our sign bit error correction module were up to 5.5 times better in peak signal-to-noise ratio than the original approximate adders, while the area and delay overhead is small.
{"title":"A general sign bit error correction scheme for approximate adders","authors":"Rui Zhou, Weikang Qian","doi":"10.1145/2902961.2903012","DOIUrl":"https://doi.org/10.1145/2902961.2903012","url":null,"abstract":"Approximate computing is an emerging design technique for error-tolerant applications. As adders are the key building blocks in many applications, approximate adders have been widely studied recently. However, existing approximate adders may introduce sign bit error when doing two's complement signed addition, which is not tolerable for some applications. In this work, we propose a scheme that can correct sign bit error with low area and delay overhead. It is a general design applicable to many block-based approximate adders. This design not only can correct the sign bit error when it occurs, but also can fix some errors in the most significant bits even if there is no sign bit error. Experimental results on a real application, namely edge detection, showed that the approximate adders with our sign bit error correction module were up to 5.5 times better in peak signal-to-noise ratio than the original approximate adders, while the area and delay overhead is small.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133322861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Anastasios Psarras, Junghee Lee, Pavlos M. Mattheakis, C. Nicopoulos, G. Dimitrakopoulos
Technology scaling of tiled-based CMPs reduces the physical size of each tile and increases the number of tiles per die. This trend directly impacts the on-chip interconnect; even though the tile population increases, the inter-tile link distances scale down proportionally to the tile dimensions. The decreasing inter-tile wire lengths can be exploited to enable swift link traversal between neighboring tiles, after appropriate wire engineering. Building on this premise, we propose a technique to rapidly transfer flits between adjacent routers in half a clock cycle, by utilizing both edges of the clock during the sending and receiving operations. Half-cycle link traversal enables, for the first time, substantial reductions in (a) link power, irrespective of the data switching profile, and (b) buffer power (through buffer-size reduction), without incurring any latency/throughput loss. In fact, the proposed architecture also yields some latency improvements over a baseline NoC. Detailed hardware analysis using placed-and-routed designs, and cycle-accurate full-system simulations corroborate the significant power and latency improvements.
{"title":"A low-power network-on-chip architecture for tile-based chip multi-processors","authors":"Anastasios Psarras, Junghee Lee, Pavlos M. Mattheakis, C. Nicopoulos, G. Dimitrakopoulos","doi":"10.1145/2902961.2903010","DOIUrl":"https://doi.org/10.1145/2902961.2903010","url":null,"abstract":"Technology scaling of tiled-based CMPs reduces the physical size of each tile and increases the number of tiles per die. This trend directly impacts the on-chip interconnect; even though the tile population increases, the inter-tile link distances scale down proportionally to the tile dimensions. The decreasing inter-tile wire lengths can be exploited to enable swift link traversal between neighboring tiles, after appropriate wire engineering. Building on this premise, we propose a technique to rapidly transfer flits between adjacent routers in half a clock cycle, by utilizing both edges of the clock during the sending and receiving operations. Half-cycle link traversal enables, for the first time, substantial reductions in (a) link power, irrespective of the data switching profile, and (b) buffer power (through buffer-size reduction), without incurring any latency/throughput loss. In fact, the proposed architecture also yields some latency improvements over a baseline NoC. Detailed hardware analysis using placed-and-routed designs, and cycle-accurate full-system simulations corroborate the significant power and latency improvements.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134068155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Gu, Shuangchen Li, Dylan C. Stow, Russell Barnes, L. Liu, Yuan Xie, E. Kursun
3D die stacking and 2.5D interposer design are promising technologies to improve integration density, performance and cost. Current approaches face serious issues in dealing with emerging security challenges such as side channel attacks, hardware trojans, secure IC manufacturing and IP piracy. By utilizing intrinsic characteristics of 2.5D and 3D technologies, we propose novel opportunities in designing secure systems. We present: (i) a 3D architecture for shielding side-channel information; (ii) split fabrication using active interposers; (iii) circuit camouflage on monolithic 3D IC, and (iv) 3D IC-based security processing-in-memory (PIM). Advantages and challenges of these designs are discussed, showing that the new designs can improve existing counter-measures against security threats and further provide new security features.
{"title":"Leveraging 3D technologies for hardware security: Opportunities and challenges","authors":"P. Gu, Shuangchen Li, Dylan C. Stow, Russell Barnes, L. Liu, Yuan Xie, E. Kursun","doi":"10.1145/2902961.2903512","DOIUrl":"https://doi.org/10.1145/2902961.2903512","url":null,"abstract":"3D die stacking and 2.5D interposer design are promising technologies to improve integration density, performance and cost. Current approaches face serious issues in dealing with emerging security challenges such as side channel attacks, hardware trojans, secure IC manufacturing and IP piracy. By utilizing intrinsic characteristics of 2.5D and 3D technologies, we propose novel opportunities in designing secure systems. We present: (i) a 3D architecture for shielding side-channel information; (ii) split fabrication using active interposers; (iii) circuit camouflage on monolithic 3D IC, and (iv) 3D IC-based security processing-in-memory (PIM). Advantages and challenges of these designs are discussed, showing that the new designs can improve existing counter-measures against security threats and further provide new security features.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115683456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we demonstrate an energy-reduction strategy that exploits the stochastic switching characteristics of STT-RAM write operation and propose a multiple-attempt write technique needed for it. In contrast to the traditional approach which uses the pulse that guarantees writes for all cells, the proposed technique uses multiple short pulses. Individually, these pulses result in high probability of write error therefore multiple attempts are made until a successful write for all bits. Average write energy is significantly reduced because the average write duration is far shorter than the worst-case duration. We developed a self-validation write circuit that allows bit-wise validation and current de-activation without adding energy and area overhead. We evaluated the proposed circuit using a compact STT-RAM model targeting an implementation in a 10nm technology node. Results indicate that the proposed architecture reduces write energy by 94.6% compared to the conventional design. Compared to the best previously known architectures that rely on write-read-verify strategy we reduce write energy by 2.1x without area overhead.
{"title":"Multiple attempt write strategy for low energy STT-RAM","authors":"Jaeyoung Park, M. Orshansky","doi":"10.1145/2902961.2903015","DOIUrl":"https://doi.org/10.1145/2902961.2903015","url":null,"abstract":"In this paper, we demonstrate an energy-reduction strategy that exploits the stochastic switching characteristics of STT-RAM write operation and propose a multiple-attempt write technique needed for it. In contrast to the traditional approach which uses the pulse that guarantees writes for all cells, the proposed technique uses multiple short pulses. Individually, these pulses result in high probability of write error therefore multiple attempts are made until a successful write for all bits. Average write energy is significantly reduced because the average write duration is far shorter than the worst-case duration. We developed a self-validation write circuit that allows bit-wise validation and current de-activation without adding energy and area overhead. We evaluated the proposed circuit using a compact STT-RAM model targeting an implementation in a 10nm technology node. Results indicate that the proposed architecture reduces write energy by 94.6% compared to the conventional design. Compared to the best previously known architectures that rely on write-read-verify strategy we reduce write energy by 2.1x without area overhead.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114286235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Implementation of high performance multi-camera / multi-sensor imaging systems that are required to produce real-time video output pose a large number of unique challenges to conventional digital design based on general-purpose processors or GPUs. In potential application areas ranging from machine vision, automotive, and virtual reality, the need for real-time operation with very limited latency dictates customized architectures that are not readily implementable using conventional approaches. In this talk, we will discuss the algorithms that are utilized in such multi-sensor platforms, the specialized architectures that allow streaming video processing, and system-level integration issues. Problems such as light-field reconstruction, multi-band blending, pixel-level interpolation, and rectification are presented, with detailed circuit and system level examples.
{"title":"Design and implementation of real-time multi-sensor vision systems","authors":"Y. Leblebici","doi":"10.1145/2902961.2902965","DOIUrl":"https://doi.org/10.1145/2902961.2902965","url":null,"abstract":"Implementation of high performance multi-camera / multi-sensor imaging systems that are required to produce real-time video output pose a large number of unique challenges to conventional digital design based on general-purpose processors or GPUs. In potential application areas ranging from machine vision, automotive, and virtual reality, the need for real-time operation with very limited latency dictates customized architectures that are not readily implementable using conventional approaches. In this talk, we will discuss the algorithms that are utilized in such multi-sensor platforms, the specialized architectures that allow streaming video processing, and system-level integration issues. Problems such as light-field reconstruction, multi-band blending, pixel-level interpolation, and rectification are presented, with detailed circuit and system level examples.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121414903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Bian, Michihiro Shintani, Shumpei Morita, H. Awano, Masayuki Hiromoto, Takashi Sato
As technology further scales semiconductor devices, aging-induced device degradation has become one of the major threats to device reliability. In addition, aging mechanisms like the negative bias temperature instability (NBTI) is known to be sensitive to workload (i.e., signal probability) that is hard to be assumed at design phase. In this work, we analyze the workload dependence of NBTI degradation using a processor, and propose a novel technique to estimate the worst-case paths. In our approach, with careful examination, we exploit the fact that the deterministic nature of circuit structure limits the amount of NBTI degradation on different paths, and proposes a two-stage path extraction algorithm to identify the invariable critical paths in the processor. Through numerical experiment on a MIPS32 processor, we performed a detailed signal probability analysis, and successfully extracted 85 invariable critical paths out of the 24,978 path candidates, achieving nearly 300× reduction in the sheer number of paths.
{"title":"Workload-aware worst path analysis of processor-scale NBTI degradation","authors":"S. Bian, Michihiro Shintani, Shumpei Morita, H. Awano, Masayuki Hiromoto, Takashi Sato","doi":"10.1145/2902961.2903013","DOIUrl":"https://doi.org/10.1145/2902961.2903013","url":null,"abstract":"As technology further scales semiconductor devices, aging-induced device degradation has become one of the major threats to device reliability. In addition, aging mechanisms like the negative bias temperature instability (NBTI) is known to be sensitive to workload (i.e., signal probability) that is hard to be assumed at design phase. In this work, we analyze the workload dependence of NBTI degradation using a processor, and propose a novel technique to estimate the worst-case paths. In our approach, with careful examination, we exploit the fact that the deterministic nature of circuit structure limits the amount of NBTI degradation on different paths, and proposes a two-stage path extraction algorithm to identify the invariable critical paths in the processor. Through numerical experiment on a MIPS32 processor, we performed a detailed signal probability analysis, and successfully extracted 85 invariable critical paths out of the 24,978 path candidates, achieving nearly 300× reduction in the sheer number of paths.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126900965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As chip multiprocessors (CMPs) are becoming more susceptible to process variation, crosstalk, and hard and soft errors, emerging threats from rogue employees in a compromised foundry are creating new vulnerabilities that could undermine the integrity of our chips with malicious alterations. As the Network-on-Chip (NoC) is a focal point of sensitive data transfer and critical device coordination, there is an urgent demand for secure and reliable communication. In this paper we propose Secure Model Checkers (SMCs), a real-time solution for control logic verification and functional correctness in the micro-architecture to detect Hardware Trojan (HT) induced denial-of-service attacks and improve reliability. In our evaluation, we show that SMCs provides significant security enhancements in real-time with only 1.5% power and 1.1% area overhead penalty in the micro-architecture.
{"title":"Secure model checkers for Network-on-Chip (NoC) architectures","authors":"T. Boraten, D. DiTomaso, Avinash Karanth Kodi","doi":"10.1145/2902961.2903032","DOIUrl":"https://doi.org/10.1145/2902961.2903032","url":null,"abstract":"As chip multiprocessors (CMPs) are becoming more susceptible to process variation, crosstalk, and hard and soft errors, emerging threats from rogue employees in a compromised foundry are creating new vulnerabilities that could undermine the integrity of our chips with malicious alterations. As the Network-on-Chip (NoC) is a focal point of sensitive data transfer and critical device coordination, there is an urgent demand for secure and reliable communication. In this paper we propose Secure Model Checkers (SMCs), a real-time solution for control logic verification and functional correctness in the micro-architecture to detect Hardware Trojan (HT) induced denial-of-service attacks and improve reliability. In our evaluation, we show that SMCs provides significant security enhancements in real-time with only 1.5% power and 1.1% area overhead penalty in the micro-architecture.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131415708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper introduces a novel design of reconfigurable Spintronic Threshold Logic Gate (STLG), which employs spintronic weight devices to perform current mode weighted summation of binary inputs, whereas, the low voltage spintronic threshold device carries out the thresholding operation in an energy efficient manner. The proposed STLG can operate at a small terminal voltage of ~50mV, resulting in ultra-low energy consumption. The device-circuit simulation results for common benchmarks show that the proposed STLG circuit can achieve 87.5% and 11.1% energy reduction compared with state-of-the-art CMOS look-up-table (LUT) and Memristive Threshold Logic Gate (MTLG) respectively. The ultra-low programming energy of spintronic weight device also leads to three orders lower reconfiguration energy of STLG compared with MTLG design.
{"title":"Ultra-low energy reconfigurable spintronic threshold logic gate","authors":"Deliang Fan","doi":"10.1145/2902961.2902994","DOIUrl":"https://doi.org/10.1145/2902961.2902994","url":null,"abstract":"This paper introduces a novel design of reconfigurable Spintronic Threshold Logic Gate (STLG), which employs spintronic weight devices to perform current mode weighted summation of binary inputs, whereas, the low voltage spintronic threshold device carries out the thresholding operation in an energy efficient manner. The proposed STLG can operate at a small terminal voltage of ~50mV, resulting in ultra-low energy consumption. The device-circuit simulation results for common benchmarks show that the proposed STLG circuit can achieve 87.5% and 11.1% energy reduction compared with state-of-the-art CMOS look-up-table (LUT) and Memristive Threshold Logic Gate (MTLG) respectively. The ultra-low programming energy of spintronic weight device also leads to three orders lower reconfiguration energy of STLG compared with MTLG design.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"220 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132450045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In modern VLSI design, manufacturing yield and chip performance are seriously affected by via failure. Redundant via insertion is an effective technique recommended by foundries to deal with the via failure. However, due to the extreme scaling of feature size, it is more and more difficult to resolve redundant via insertion (RVI) with limited routing resource while obeying complicated design rules. In this paper, we propose an RVI enhanced concurrent detailed router, M-CFRoute 2.0, which effectively avoids design rule violations through a compact integer linear programming (ILP) model. The proposed router can not only route all nets simultaneously but also search for redundant via positions for all via simultaneously during routing stage. In addition, it proposes an RVI aware pin access allocation to further improve the routing performance. Experimental results show that our detailed router outperforms an industry EDA tool that it improves the redundant via insertion rate by 21%, while reducing design rule checking violation count, total wire length and via count by 47%, 4% and 14%, respectively.
{"title":"MCFRoute 2.0: A redundant via insertion enhanced concurrent detailed router","authors":"Xiaotao Jia, Yici Cai, Qiang Zhou, Bei Yu","doi":"10.1145/2902961.2902966","DOIUrl":"https://doi.org/10.1145/2902961.2902966","url":null,"abstract":"In modern VLSI design, manufacturing yield and chip performance are seriously affected by via failure. Redundant via insertion is an effective technique recommended by foundries to deal with the via failure. However, due to the extreme scaling of feature size, it is more and more difficult to resolve redundant via insertion (RVI) with limited routing resource while obeying complicated design rules. In this paper, we propose an RVI enhanced concurrent detailed router, M-CFRoute 2.0, which effectively avoids design rule violations through a compact integer linear programming (ILP) model. The proposed router can not only route all nets simultaneously but also search for redundant via positions for all via simultaneously during routing stage. In addition, it proposes an RVI aware pin access allocation to further improve the routing performance. Experimental results show that our detailed router outperforms an industry EDA tool that it improves the redundant via insertion rate by 21%, while reducing design rule checking violation count, total wire length and via count by 47%, 4% and 14%, respectively.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132729612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We consider how the I-V characteristics of emerging transistors (particularly those sponsored by STARnet) might be employed to enhance hardware security. An emphasis of this work is to move beyond hardware implementations of physically unclonable functions (PUFs) and random number generators (RNGs). We highlight how new devices (i) may enable more sophisticated logic obfuscation for IP protection, (ii) could help to prevent fault injection attacks, (iii) prevent differential power analysis in lightweight cryptographic systems, etc.
{"title":"Enhancing hardware security with emerging transistor technologies","authors":"Yu Bi, X. Hu, Yier Jin, M. Niemier, Kaveh Shamsi, Xunzhao Yin","doi":"10.1145/2902961.2903041","DOIUrl":"https://doi.org/10.1145/2902961.2903041","url":null,"abstract":"We consider how the I-V characteristics of emerging transistors (particularly those sponsored by STARnet) might be employed to enhance hardware security. An emphasis of this work is to move beyond hardware implementations of physically unclonable functions (PUFs) and random number generators (RNGs). We highlight how new devices (i) may enable more sophisticated logic obfuscation for IP protection, (ii) could help to prevent fault injection attacks, (iii) prevent differential power analysis in lightweight cryptographic systems, etc.","PeriodicalId":407054,"journal":{"name":"2016 International Great Lakes Symposium on VLSI (GLSVLSI)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116684285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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