Pub Date : 2005-12-19DOI: 10.1109/SMICND.2005.1558792
K. Moselund, J.E. Freiermuth, P. Dainesi, A. Ionescu
This paper reports on the process dependence and electrical characterization of Schottky diodes and ohmic contacts fabricated on p- and n-type silicon wafers. Four metals are studied: Mo, Ti, W, and Cr due to their mid-gap barriers and compatibility with microelectronics processing. For these an original investigation of the variation in Schottky barrier height and contact resistance is carried out for the following process parameters: (i) pre-deposition wafer preparation, (ii) deposition method (sputtering and e-beam evaporation). (iii) deposition temperature for the sputtered samples, and (iv) annealing. It is found that RF-etching previous to metal deposition increases the contact resistance and the barrier height for diodes on p-type silicon. This is of great importance, since RF-etching is a very common in-situ cleaning process in microelectronic and MEMS technologies. Annealing can be used to restore the values of barrier height and contact resistance on wafers exposed to RF-etching
{"title":"Process dependence and characterization of Mo, Cr, Ti and W silicon Schottky diodes","authors":"K. Moselund, J.E. Freiermuth, P. Dainesi, A. Ionescu","doi":"10.1109/SMICND.2005.1558792","DOIUrl":"https://doi.org/10.1109/SMICND.2005.1558792","url":null,"abstract":"This paper reports on the process dependence and electrical characterization of Schottky diodes and ohmic contacts fabricated on p- and n-type silicon wafers. Four metals are studied: Mo, Ti, W, and Cr due to their mid-gap barriers and compatibility with microelectronics processing. For these an original investigation of the variation in Schottky barrier height and contact resistance is carried out for the following process parameters: (i) pre-deposition wafer preparation, (ii) deposition method (sputtering and e-beam evaporation). (iii) deposition temperature for the sputtered samples, and (iv) annealing. It is found that RF-etching previous to metal deposition increases the contact resistance and the barrier height for diodes on p-type silicon. This is of great importance, since RF-etching is a very common in-situ cleaning process in microelectronic and MEMS technologies. Annealing can be used to restore the values of barrier height and contact resistance on wafers exposed to RF-etching","PeriodicalId":40779,"journal":{"name":"Teatro e Storia","volume":null,"pages":null},"PeriodicalIF":0.1,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83295692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/SMICND.2005.1558808
C. Popa
An original improved linearization technique for a CMOS active resistor will be further presented. The main advantages of the original proposed implementation are the improved linearity, the small area consumption and the improved frequency response. The new method for linearizing the I(V) characteristic of the active resistor will be based on a parallel connection of two quasi-ideal circuits opposite excited and different biased, having the result of improving the circuit linearity with about an order of magnitude. Because of this original design technique, the circuit linearity is not affected by the second-order effects that alter the MOS transistor operation. The reduced complexity obtained by using a FGMOS transistor will he made maintaining the compatibility with classical technologies (the classical FGMOS device could be replaced by an original equivalent circuit using exclusively classical MOS devices). The frequency response of the circuit is very good as a result of operating all MOS transistors in the saturation region. The circuit is implemented in 0.35 mum CMOS technology, the SPICE simulation confirming the theoretical estimated results and showing a linearity error under a percent for an extended input range (plusmn 500mV) and for a small value of the supply voltage (plusmn 3V)
本文将进一步提出一种改进的CMOS有源电阻线性化技术。最初提出的实现的主要优点是改进的线性度，小面积消耗和改进的频率响应。线性化有源电阻器I(V)特性的新方法将基于两个激励相反、偏置不同的准理想电路并联，其结果是将电路的线性度提高约一个数量级。由于这种原始的设计技术，电路线性度不受改变MOS晶体管工作的二阶效应的影响。使用FGMOS晶体管所获得的复杂性降低将有助于保持与经典技术的兼容性(经典的FGMOS器件可以被完全使用经典MOS器件的原始等效电路所取代)。由于所有MOS晶体管都工作在饱和区，因此电路的频率响应非常好。该电路采用0.35 μ m CMOS技术实现，SPICE仿真证实了理论估计结果，并显示在扩展输入范围(plusmn 500mV)和小电源电压值(plusmn 3V)下线性误差小于1%。
{"title":"A new improved linearity active resistor using complementary functions","authors":"C. Popa","doi":"10.1109/SMICND.2005.1558808","DOIUrl":"https://doi.org/10.1109/SMICND.2005.1558808","url":null,"abstract":"An original improved linearization technique for a CMOS active resistor will be further presented. The main advantages of the original proposed implementation are the improved linearity, the small area consumption and the improved frequency response. The new method for linearizing the I(V) characteristic of the active resistor will be based on a parallel connection of two quasi-ideal circuits opposite excited and different biased, having the result of improving the circuit linearity with about an order of magnitude. Because of this original design technique, the circuit linearity is not affected by the second-order effects that alter the MOS transistor operation. The reduced complexity obtained by using a FGMOS transistor will he made maintaining the compatibility with classical technologies (the classical FGMOS device could be replaced by an original equivalent circuit using exclusively classical MOS devices). The frequency response of the circuit is very good as a result of operating all MOS transistors in the saturation region. The circuit is implemented in 0.35 mum CMOS technology, the SPICE simulation confirming the theoretical estimated results and showing a linearity error under a percent for an extended input range (plusmn 500mV) and for a small value of the supply voltage (plusmn 3V)","PeriodicalId":40779,"journal":{"name":"Teatro e Storia","volume":null,"pages":null},"PeriodicalIF":0.1,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86999161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/SMICND.2005.1558757
M. Miu, A. Angelescu, L. Kleps, F. Craciunoiu, A. Bragaru, T. Ignat, M. Simion
The development of implantable devices for controlled drug delivery is of great interest for medicine applications. Some drug delivery systems already exist and there are based on in vivo degradation of different biomaterials such as polymers or porous silicon; the drug release over a period of time is realised via out-diffusion and/or degradation of the impregnated material. In this paper a new integrated system on silicon substrate is presented: it consists of a microreservoir array filled with drugs which have metallic caps, and the release of drugs is electrically controlled.
{"title":"Integrated system on silicon for electrically controlled drug delivery","authors":"M. Miu, A. Angelescu, L. Kleps, F. Craciunoiu, A. Bragaru, T. Ignat, M. Simion","doi":"10.1109/SMICND.2005.1558757","DOIUrl":"https://doi.org/10.1109/SMICND.2005.1558757","url":null,"abstract":"The development of implantable devices for controlled drug delivery is of great interest for medicine applications. Some drug delivery systems already exist and there are based on in vivo degradation of different biomaterials such as polymers or porous silicon; the drug release over a period of time is realised via out-diffusion and/or degradation of the impregnated material. In this paper a new integrated system on silicon substrate is presented: it consists of a microreservoir array filled with drugs which have metallic caps, and the release of drugs is electrically controlled.","PeriodicalId":40779,"journal":{"name":"Teatro e Storia","volume":null,"pages":null},"PeriodicalIF":0.1,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90696121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/SMICND.2005.1558704
C. Iliescu, F. Tay
The purpose of this paper is to find ways to Improve the wet etching techniques used for glass etching. Essential elements of glass wet etching process such as: influence of glass composition, etching rate, influence of the residual stress in the masking layer, characterization of the main masking materials, the quality of surface generated using wet etching process are analyzed. As a result of this analysis an improved technique for deep wet etching of glass is proposed. A 500-/spl mu/m thick Pyrex glass wafer was etched through using a Cr/Au and photoresist mask, from our knowledge this is the best result reported. For an improved surface an optimal solution HF/HCl (10:1) was established for Pyrex and soda lime glasses. The developed techniques are currently used for fabrication of microfluidic devices on glass.
{"title":"Wet etching of glass","authors":"C. Iliescu, F. Tay","doi":"10.1109/SMICND.2005.1558704","DOIUrl":"https://doi.org/10.1109/SMICND.2005.1558704","url":null,"abstract":"The purpose of this paper is to find ways to Improve the wet etching techniques used for glass etching. Essential elements of glass wet etching process such as: influence of glass composition, etching rate, influence of the residual stress in the masking layer, characterization of the main masking materials, the quality of surface generated using wet etching process are analyzed. As a result of this analysis an improved technique for deep wet etching of glass is proposed. A 500-/spl mu/m thick Pyrex glass wafer was etched through using a Cr/Au and photoresist mask, from our knowledge this is the best result reported. For an improved surface an optimal solution HF/HCl (10:1) was established for Pyrex and soda lime glasses. The developed techniques are currently used for fabrication of microfluidic devices on glass.","PeriodicalId":40779,"journal":{"name":"Teatro e Storia","volume":null,"pages":null},"PeriodicalIF":0.1,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74303555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/SMICND.2005.1558800
M. Placidi, P. Godignon, N. Mestres, J. Esteve, G. Ferro, A. Leycuras, T. Chassagne
The development of high quality 3C-SiC layers on Si free of residual stress opens the possibility to use SiC for microsystems fabrication and to combine them with Si devices for sensor applications. A new front-side micromachining process technology for 3C-SiC layers on Si resonators has been developed. To show it feasibility several resonator cantilever or bridge test structures of various dimensions have been fabricated. The main advantage of SiC in comparison with Si lies on its higher Young's modulus (almost three times higher), which results in higher resonance frequencies and higher quality factors
{"title":"Fabrication of electrostatic resonators with monocrystalline 3C-SiC grown on silicon","authors":"M. Placidi, P. Godignon, N. Mestres, J. Esteve, G. Ferro, A. Leycuras, T. Chassagne","doi":"10.1109/SMICND.2005.1558800","DOIUrl":"https://doi.org/10.1109/SMICND.2005.1558800","url":null,"abstract":"The development of high quality 3C-SiC layers on Si free of residual stress opens the possibility to use SiC for microsystems fabrication and to combine them with Si devices for sensor applications. A new front-side micromachining process technology for 3C-SiC layers on Si resonators has been developed. To show it feasibility several resonator cantilever or bridge test structures of various dimensions have been fabricated. The main advantage of SiC in comparison with Si lies on its higher Young's modulus (almost three times higher), which results in higher resonance frequencies and higher quality factors","PeriodicalId":40779,"journal":{"name":"Teatro e Storia","volume":null,"pages":null},"PeriodicalIF":0.1,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74621145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/SMICND.2005.1558746
M. Szermer, A. Napieralski
In this paper the PTAT (point to absolute temperature) sensor design in CMOS technology is discussed and presented. Two different structures are described. The first one was implemented together with 12-bit ADC into a test chip. Although this sensor has a small linear region, only up to 60 C, it is fully functional and fulfills all requirements. Nevertheless, that was the reason why the new research was established, and a second structure with wide up to 180 /spl deg/C linear range was developed.
{"title":"The PTAT sensors in CMOS technology","authors":"M. Szermer, A. Napieralski","doi":"10.1109/SMICND.2005.1558746","DOIUrl":"https://doi.org/10.1109/SMICND.2005.1558746","url":null,"abstract":"In this paper the PTAT (point to absolute temperature) sensor design in CMOS technology is discussed and presented. Two different structures are described. The first one was implemented together with 12-bit ADC into a test chip. Although this sensor has a small linear region, only up to 60 C, it is fully functional and fulfills all requirements. Nevertheless, that was the reason why the new research was established, and a second structure with wide up to 180 /spl deg/C linear range was developed.","PeriodicalId":40779,"journal":{"name":"Teatro e Storia","volume":null,"pages":null},"PeriodicalIF":0.1,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74640739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/SMICND.2005.1558762
C. Codreanu, I. Stan, F. Craciunoiu, V. Obreja
This paper presents a temperature monitoring system used for the experimental investigation and characterization of materials and microstructures or devices under different temperature conditions. After a general description of the measurement system, the temperature control and measurement block is presented. The heating and the sensing elements are firstly presented, and then the temperature monitoring unit is described. Besides the constructive solutions, problems related to thermal contact, calibration, error and sensitivity are also discussed.
{"title":"In situ temperature monitoring system for experimental investigation of microstructures","authors":"C. Codreanu, I. Stan, F. Craciunoiu, V. Obreja","doi":"10.1109/SMICND.2005.1558762","DOIUrl":"https://doi.org/10.1109/SMICND.2005.1558762","url":null,"abstract":"This paper presents a temperature monitoring system used for the experimental investigation and characterization of materials and microstructures or devices under different temperature conditions. After a general description of the measurement system, the temperature control and measurement block is presented. The heating and the sensing elements are firstly presented, and then the temperature monitoring unit is described. Besides the constructive solutions, problems related to thermal contact, calibration, error and sensitivity are also discussed.","PeriodicalId":40779,"journal":{"name":"Teatro e Storia","volume":null,"pages":null},"PeriodicalIF":0.1,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84430895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/SMICND.2005.1558825
S. Spiridon, F. Op't Eynde
This paper presents the analyses and design of a very high speed 6 bit digital to analog converter intended for high-speed data streaming applications. The DAC is implemented using current switching technique. For eliminating non-monotonicity thermometric coding is used for the first five MSBs. The circuit has differential current outputs. The output voltage is generated externally by the current that the DAC injects into high precision resistors. The circuit operates at only 1.5 V, making it an ideal choice for low-power mobile applications. The circuit exhibits a third order intermodulation (IM3) of about 37 dBc with a full-scale two tone sinusoidal inputs at 150 MHz and 200 MHz. The DAC is fabricated in a 0.13mum in CMOS technology, it occupies 0.3 mm 2 and dissipates less then 7.5 mW
本文介绍了一种用于高速数据流应用的超高速6位数模转换器的分析和设计。该DAC采用电流开关技术实现。为了消除非单调性，对前五个msb使用温度编码。电路有差动电流输出。输出电压由DAC注入高精度电阻的电流在外部产生。该电路工作电压仅为1.5 V，使其成为低功耗移动应用的理想选择。该电路具有约37 dBc的三阶互调(IM3)，并具有150 MHz和200 MHz的满量程双音正弦输入。该DAC采用0.13 μ m CMOS技术制造，占地0.3 mm2，功耗小于7.5 mW
{"title":"A 6 bit resolution, 1 gsamples/sec digital to analog converter","authors":"S. Spiridon, F. Op't Eynde","doi":"10.1109/SMICND.2005.1558825","DOIUrl":"https://doi.org/10.1109/SMICND.2005.1558825","url":null,"abstract":"This paper presents the analyses and design of a very high speed 6 bit digital to analog converter intended for high-speed data streaming applications. The DAC is implemented using current switching technique. For eliminating non-monotonicity thermometric coding is used for the first five MSBs. The circuit has differential current outputs. The output voltage is generated externally by the current that the DAC injects into high precision resistors. The circuit operates at only 1.5 V, making it an ideal choice for low-power mobile applications. The circuit exhibits a third order intermodulation (IM3) of about 37 dBc with a full-scale two tone sinusoidal inputs at 150 MHz and 200 MHz. The DAC is fabricated in a 0.13mum in CMOS technology, it occupies 0.3 mm 2 and dissipates less then 7.5 mW","PeriodicalId":40779,"journal":{"name":"Teatro e Storia","volume":null,"pages":null},"PeriodicalIF":0.1,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84130819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/SMICND.2005.1558791
E. Bodegom, R. Widenhorn, D.A. lordache
The experimental results concerning the temperature dependence of the dark currents in some charge-coupled devices (CCDs) were analyzed. It was found that the used theoretical model allows: (i) the evaluation of the lowest limit of experimental errors (involving the systematic ones), (ii) the study of Meyer-Neldel relations, pointing out the high correlation of diffusion dark currents with the energy-gap Eg, unlike the corresponding weak correlation of depletion dark currents (iii) rather accurate assignments of the obtained values of deep-level traps energies to some specific impurities
{"title":"Interpreting fitting parameters of temperature dependence of dark currents in some CCDs","authors":"E. Bodegom, R. Widenhorn, D.A. lordache","doi":"10.1109/SMICND.2005.1558791","DOIUrl":"https://doi.org/10.1109/SMICND.2005.1558791","url":null,"abstract":"The experimental results concerning the temperature dependence of the dark currents in some charge-coupled devices (CCDs) were analyzed. It was found that the used theoretical model allows: (i) the evaluation of the lowest limit of experimental errors (involving the systematic ones), (ii) the study of Meyer-Neldel relations, pointing out the high correlation of diffusion dark currents with the energy-gap Eg, unlike the corresponding weak correlation of depletion dark currents (iii) rather accurate assignments of the obtained values of deep-level traps energies to some specific impurities","PeriodicalId":40779,"journal":{"name":"Teatro e Storia","volume":null,"pages":null},"PeriodicalIF":0.1,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89300711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/SMICND.2005.1558811
S. Eftimie, A. Rusu
A special characteristic of a MOS transistor is that its drain current has a point somewhere around the threshold voltage where it almost doesn't vary with the temperature. This is called the Zero-TC (ZTC) point. By considering two different types of MOSFET models, a strong inversion and an unified one, it can see that both of them indicated the position of the ZTC point close to the measured one (sec Table 1). As this paper indicates, it is normally to presume that the larger value obtained with the unified model is due to the sub threshold component of the drain current. This is because the strong inversion model does not take it into account. Unlike this model, the unified one considers the drain current as a sum of the diffusion current, preponderant in weak inversion, and the drift current, which governs the strong inversion region. Because the ZTC point is somewhere between these two regions, it is normally to presume that the diffusion current has an influence on it. The paper will answer to this problem and will try to explain the results
{"title":"The influence of diffusion current on the zero-tc point of a MOS transistor","authors":"S. Eftimie, A. Rusu","doi":"10.1109/SMICND.2005.1558811","DOIUrl":"https://doi.org/10.1109/SMICND.2005.1558811","url":null,"abstract":"A special characteristic of a MOS transistor is that its drain current has a point somewhere around the threshold voltage where it almost doesn't vary with the temperature. This is called the Zero-TC (ZTC) point. By considering two different types of MOSFET models, a strong inversion and an unified one, it can see that both of them indicated the position of the ZTC point close to the measured one (sec Table 1). As this paper indicates, it is normally to presume that the larger value obtained with the unified model is due to the sub threshold component of the drain current. This is because the strong inversion model does not take it into account. Unlike this model, the unified one considers the drain current as a sum of the diffusion current, preponderant in weak inversion, and the drift current, which governs the strong inversion region. Because the ZTC point is somewhere between these two regions, it is normally to presume that the diffusion current has an influence on it. The paper will answer to this problem and will try to explain the results","PeriodicalId":40779,"journal":{"name":"Teatro e Storia","volume":null,"pages":null},"PeriodicalIF":0.1,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87513736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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