Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569643
Qi Wang, S. Vrudhula
We present an efficient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations consist of adding redundant connections or gates so as to reduce the switching activity. Simple and efficient procedures, based on logic implication, for identifying the sources and targets of the redundant connections are presented. Additionally, procedures that permit the designer to trade-off power and delay after the transformations are described. Results of experiments on the MCNC benchmark circuits are given. The results indicate that significant reduction of the switching activities of a CMOS combinational circuit can be achieved with a very low area overhead and low computational cost.
{"title":"Multi-level logic optimization for low power using local logic transformations","authors":"Qi Wang, S. Vrudhula","doi":"10.1109/ICCAD.1996.569643","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569643","url":null,"abstract":"We present an efficient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations consist of adding redundant connections or gates so as to reduce the switching activity. Simple and efficient procedures, based on logic implication, for identifying the sources and targets of the redundant connections are presented. Additionally, procedures that permit the designer to trade-off power and delay after the transformations are described. Results of experiments on the MCNC benchmark circuits are given. The results indicate that significant reduction of the switching activities of a CMOS combinational circuit can be achieved with a very low area overhead and low computational cost.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123099883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569911
M. Çelik, A. Cangellaris
Although numerous methods have been proposed for interconnect simulation, no single model exists for all kind of transmission line problems. This paper presents a new, single, general dispersive coupled uniform/nonuniform transmission line model which can be used for interconnect simulation in SPICE. The mathematical model is based on the use of Chebyshev polynomials for the representation of the spatial variation of the transmission-line voltages and currents. A simple collocation procedure is used to obtain a matrix representation of the transmission line equations with matrix coefficients that are first polynomials in s, and in which terminal transmission-line voltages and currents appear explicitly. Thus, the model is compatible with both the SPICE's numerical integration algorithm and the modified nodal analysis formalism.
{"title":"A general dispersive multiconductor transmission line model for interconnect simulation in SPICE","authors":"M. Çelik, A. Cangellaris","doi":"10.1109/ICCAD.1996.569911","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569911","url":null,"abstract":"Although numerous methods have been proposed for interconnect simulation, no single model exists for all kind of transmission line problems. This paper presents a new, single, general dispersive coupled uniform/nonuniform transmission line model which can be used for interconnect simulation in SPICE. The mathematical model is based on the use of Chebyshev polynomials for the representation of the spatial variation of the transmission-line voltages and currents. A simple collocation procedure is used to obtain a matrix representation of the transmission line equations with matrix coefficients that are first polynomials in s, and in which terminal transmission-line voltages and currents appear explicitly. Thus, the model is compatible with both the SPICE's numerical integration algorithm and the modified nodal analysis formalism.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115831504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569917
M. Lubaszewski, S. Mir, Leandro Pulz
This paper presents a novel multifunctional test structure called Analog BulLt-in Block Observer (ABILBO). This structure is based on analog integrators and achieves analog scan, test frequency generation and test response compaction. A high fault coverage was obtained by using a discrete switched-capacitor ABILBO for testing a biquad filter. The ABILBO area overhead and performance penalty can be very low if functional and testing circuitry are shared. This is typically the case of high order filters based on a cascade of biquads.
{"title":"ABILBO: Analog BuILt-in block observer","authors":"M. Lubaszewski, S. Mir, Leandro Pulz","doi":"10.1109/ICCAD.1996.569917","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569917","url":null,"abstract":"This paper presents a novel multifunctional test structure called Analog BulLt-in Block Observer (ABILBO). This structure is based on analog integrators and achieves analog scan, test frequency generation and test response compaction. A high fault coverage was obtained by using a discrete switched-capacitor ABILBO for testing a biquad filter. The ABILBO area overhead and performance penalty can be very low if functional and testing circuitry are shared. This is typically the case of high order filters based on a cascade of biquads.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130127902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569902
Keerthi Heragu, J. Patel, V. Agrawal
We propose an efficient combinational circuit simulation technique for the recently proposed segment delay fault model. After simulation of a vector pair, activated segments are traced using a depth-first search. A segment numbering scheme finds the number of faults to be simulated. A labeling technique generates edge labels to compute a unique label for each segment fault. The use of labels avoids explicit storing of fault lists and allows efficient access to previously detected segment faults. Experimental results demonstrate several advantages of the segment delay fault model. First, the total number of faults remains manageable for small segment lengths. Second, many segments, not included in any robustly testable path fault, may have robust segment delay fault tests. Generating tests for such segments may increase the delay defect coverage.
{"title":"SIGMA: A simulator for segment delay faults","authors":"Keerthi Heragu, J. Patel, V. Agrawal","doi":"10.1109/ICCAD.1996.569902","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569902","url":null,"abstract":"We propose an efficient combinational circuit simulation technique for the recently proposed segment delay fault model. After simulation of a vector pair, activated segments are traced using a depth-first search. A segment numbering scheme finds the number of faults to be simulated. A labeling technique generates edge labels to compute a unique label for each segment fault. The use of labels avoids explicit storing of fault lists and allows efficient access to previously detected segment faults. Experimental results demonstrate several advantages of the segment delay fault model. First, the total number of faults remains manageable for small segment lengths. Second, many segments, not included in any robustly testable path fault, may have robust segment delay fault tests. Generating tests for such segments may increase the delay defect coverage.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131551615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this study, we present a controllability measure for high-level circuit descriptions and a high-level synthesis-for-testability technique. Unlike many studies in the area of high-level synthesis for testability that focus on improving the testability of data paths, the objective of our approach is to improve the testability of synthesized circuits by enhancing the controllability of the control flow. Experimental results on several high-level synthesis benchmarks show that when this approach is used prior to logic synthesis, a shorter ATPG time, a smaller test set, and better fault coverage and ATPG efficiency are often achieved. Implementation of this technique requires minimal logic and performance overheads and allows test vectors to be applied at clock-speed.
{"title":"Enhancing high-level control-flow for improved testability","authors":"Frank F. Hsu, E. Rudnick, J. Patel","doi":"10.5555/244522.244823","DOIUrl":"https://doi.org/10.5555/244522.244823","url":null,"abstract":"In this study, we present a controllability measure for high-level circuit descriptions and a high-level synthesis-for-testability technique. Unlike many studies in the area of high-level synthesis for testability that focus on improving the testability of data paths, the objective of our approach is to improve the testability of synthesized circuits by enhancing the controllability of the control flow. Experimental results on several high-level synthesis benchmarks show that when this approach is used prior to logic synthesis, a shorter ATPG time, a smaller test set, and better fault coverage and ATPG efficiency are often achieved. Implementation of this technique requires minimal logic and performance overheads and allows test vectors to be applied at clock-speed.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124848585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.568905
S. Corey, A. Yang
An approach is presented for modeling board level, package-level, and MCM substrate-level interconnect circuitry based an measured time domain refectometry data. The time-domain scattering parameters of a multiport system are used to extract a SPICE netlist which uses standard elements to match the behavior of the device up to a user-specified cutoff frequency. Linear or nonlinear circuits may be connected to the model ports, and the entire circuit simulated in a standard circuit simulator. Two-port and four-port example microstrip circuits are characterized, and the simulation results are compared with measured data. Delay, reflection transmission, and crosstalk are accurately modeled in each case.
{"title":"Automatic netlist extraction for measurement-based characterization of off-chip interconnect","authors":"S. Corey, A. Yang","doi":"10.1109/ICCAD.1996.568905","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.568905","url":null,"abstract":"An approach is presented for modeling board level, package-level, and MCM substrate-level interconnect circuitry based an measured time domain refectometry data. The time-domain scattering parameters of a multiport system are used to extract a SPICE netlist which uses standard elements to match the behavior of the device up to a user-specified cutoff frequency. Linear or nonlinear circuits may be connected to the model ports, and the entire circuit simulated in a standard circuit simulator. Two-port and four-port example microstrip circuits are characterized, and the simulation results are compared with measured data. Delay, reflection transmission, and crosstalk are accurately modeled in each case.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125809700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569536
Eric W. Johnson, J. Brockman
As design processes continue to increase in complexity, it is important to base process improvements on quantitative analysis. In this paper we develop an analytical approach to analyze sequential design processes using sensitivity analysis. Two applications illustrate this approach, one involving a Pareto analysis of an ASIC design process and the other an optimization of a software design process to determine the lower bound of the process completion time.
{"title":"Sensitivity analysis of iterative design processes","authors":"Eric W. Johnson, J. Brockman","doi":"10.1109/ICCAD.1996.569536","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569536","url":null,"abstract":"As design processes continue to increase in complexity, it is important to base process improvements on quantitative analysis. In this paper we develop an analytical approach to analyze sequential design processes using sensitivity analysis. Two applications illustrate this approach, one involving a Pareto analysis of an ASIC design process and the other an optimization of a software design process to determine the lower bound of the process completion time.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115213142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569712
P. Feldmann, J. Roychowdhury
In this paper we introduce a novel algorithm for numerically computing the "slow" dynamics (envelope) of circuits in which a "fast" varying carrier signal as also present. The algorithm proceeds at the rate of the slow behavior and its computational cost is fairly insensitive to the rate of the fast signals. The envelope computation problem is formulated as a differential-algebraic system of equations (DAEs) in terms of frequency-domain quantities (e.g. amplitudes and phases) that capture the fast varying behavior of the circuit. The solution of this DAE represents the "slow" variation of these quantities, i.e., the envelope. The efficiency of this method is the result of using the most appropriate method for each of the circuit modes: harmonic balance for the fast behavior and time-domain integration of DAEs for the slow behavior. The paper describes the theoretical foundations of the algorithm and presents several circuit analysis examples.
{"title":"Computation of circuit waveform envelopes using an efficient, matrix-decomposed harmonic balance algorithm","authors":"P. Feldmann, J. Roychowdhury","doi":"10.1109/ICCAD.1996.569712","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569712","url":null,"abstract":"In this paper we introduce a novel algorithm for numerically computing the \"slow\" dynamics (envelope) of circuits in which a \"fast\" varying carrier signal as also present. The algorithm proceeds at the rate of the slow behavior and its computational cost is fairly insensitive to the rate of the fast signals. The envelope computation problem is formulated as a differential-algebraic system of equations (DAEs) in terms of frequency-domain quantities (e.g. amplitudes and phases) that capture the fast varying behavior of the circuit. The solution of this DAE represents the \"slow\" variation of these quantities, i.e., the envelope. The efficiency of this method is the result of using the most appropriate method for each of the circuit modes: harmonic balance for the fast behavior and time-domain integration of DAEs for the slow behavior. The paper describes the theoretical foundations of the algorithm and presents several circuit analysis examples.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130217584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569825
W. Hong, W. Sun, Zhenhai Zhu, Hao Ji, Ben Song, W. Dai
In this paper, we present a new capacitance extraction method named Dimension Reduction Technique (DRT) for 3D VLSI interconnects. The DRT converts a complex 3D problem into a series of cascading simple 2D problems. Each 3D problem is solved separately, so we can choose the most efficient method according to the arrangement of conductors. More importantly, it is very easy to obtain the analytical solutions of 2D problem in many layers such as the pure dielectric layers and the layers with parallel signal lines. Therefore, the domain that has to be analyzed numerically is minimized. This leads to the drastic reduction of the computing time and memory needs. We have used the DRT to extract the capacitances of multilayered and multiconductor cross-overs, bends, via with signal lines and open-end. The results are in good agreement with those of Ansoft's SPICELINK and MIT's FastCap, but the computing time and memory size used by the DRT are several even tens times less than those used by SPICELINK and FastCap.
{"title":"A novel dimension reduction technique for the capacitance extraction of 3D VLSI interconnects","authors":"W. Hong, W. Sun, Zhenhai Zhu, Hao Ji, Ben Song, W. Dai","doi":"10.1109/ICCAD.1996.569825","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569825","url":null,"abstract":"In this paper, we present a new capacitance extraction method named Dimension Reduction Technique (DRT) for 3D VLSI interconnects. The DRT converts a complex 3D problem into a series of cascading simple 2D problems. Each 3D problem is solved separately, so we can choose the most efficient method according to the arrangement of conductors. More importantly, it is very easy to obtain the analytical solutions of 2D problem in many layers such as the pure dielectric layers and the layers with parallel signal lines. Therefore, the domain that has to be analyzed numerically is minimized. This leads to the drastic reduction of the computing time and memory needs. We have used the DRT to extract the capacitances of multilayered and multiconductor cross-overs, bends, via with signal lines and open-end. The results are in good agreement with those of Ansoft's SPICELINK and MIT's FastCap, but the computing time and memory size used by the DRT are several even tens times less than those used by SPICELINK and FastCap.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130867161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.571354
Xiao-Tao Chen, F. Lombardi
This paper presents a new approach for diagnosing stuck-at and short faults in interconnects whose layouts are known. This structural approach exploits different graph coloring and coding techniques to generate a test set with no aliasing and confounding. The conditions for aliasing and confounding are analyzed with respect to the size and number of the shorts in the fault set. The characteristics of unbalanced/balanced codes for encoding the colors in the vector generation process for interconnect diagnosis are discussed and proved using a novel algebra. An algorithm for diagnosis is then presented.
{"title":"A coloring approach to the structural diagnosis of interconnects","authors":"Xiao-Tao Chen, F. Lombardi","doi":"10.1109/ICCAD.1996.571354","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.571354","url":null,"abstract":"This paper presents a new approach for diagnosing stuck-at and short faults in interconnects whose layouts are known. This structural approach exploits different graph coloring and coding techniques to generate a test set with no aliasing and confounding. The conditions for aliasing and confounding are analyzed with respect to the size and number of the shorts in the fault set. The characteristics of unbalanced/balanced codes for encoding the colors in the vector generation process for interconnect diagnosis are discussed and proved using a novel algebra. An algorithm for diagnosis is then presented.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125908705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：