Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.571365
Wojciech Maly, H. Heineken, J. Khare, P. Nag
Key characteristics of newly emerging IC technologies render the traditional concept of die size minimization and traditional "design rules" insufficient to handle the design-manufacturing interface. This tutorial surveys the design and process characteristics relevant to the manufacturability of submicron ICs. The discussion also covers analysis of design for manufacturability (DFM) trade-offs. Yield and cost models needed to analyze these trade-offs are explained as well.
{"title":"Design for manufacturability in submicron domain","authors":"Wojciech Maly, H. Heineken, J. Khare, P. Nag","doi":"10.1109/ICCAD.1996.571365","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.571365","url":null,"abstract":"Key characteristics of newly emerging IC technologies render the traditional concept of die size minimization and traditional \"design rules\" insufficient to handle the design-manufacturing interface. This tutorial surveys the design and process characteristics relevant to the manufacturability of submicron ICs. The discussion also covers analysis of design for manufacturability (DFM) trade-offs. Yield and cost models needed to analyze these trade-offs are explained as well.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126884501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.571334
Inki Hong, M. Potkonjak
While numerous power optimization techniques have been proposed at all levels of design process abstractions for electronic components, until now, power minimization in mixed mechanical-electronic subsystems, such as disks, has not been addressed. We propose a conceptually simple, but realistic power consumption model for disk drives. We present heuristics for optimization of power consumption in several common hard real-time disk-based design systems. We show how to coordinate task scheduling and disk data assignment, in order to minimize power consumption in both electronic and mechanical components of used disks. Extensive experimental results indicate significant power reduction.
{"title":"Power optimization in disk-based real-time application specific systems","authors":"Inki Hong, M. Potkonjak","doi":"10.1109/ICCAD.1996.571334","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.571334","url":null,"abstract":"While numerous power optimization techniques have been proposed at all levels of design process abstractions for electronic components, until now, power minimization in mixed mechanical-electronic subsystems, such as disks, has not been addressed. We propose a conceptually simple, but realistic power consumption model for disk drives. We present heuristics for optimization of power consumption in several common hard real-time disk-based design systems. We show how to coordinate task scheduling and disk data assignment, in order to minimize power consumption in both electronic and mechanical components of used disks. Extensive experimental results indicate significant power reduction.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126081610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569917
M. Lubaszewski, S. Mir, Leandro Pulz
This paper presents a novel multifunctional test structure called Analog BulLt-in Block Observer (ABILBO). This structure is based on analog integrators and achieves analog scan, test frequency generation and test response compaction. A high fault coverage was obtained by using a discrete switched-capacitor ABILBO for testing a biquad filter. The ABILBO area overhead and performance penalty can be very low if functional and testing circuitry are shared. This is typically the case of high order filters based on a cascade of biquads.
{"title":"ABILBO: Analog BuILt-in block observer","authors":"M. Lubaszewski, S. Mir, Leandro Pulz","doi":"10.1109/ICCAD.1996.569917","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569917","url":null,"abstract":"This paper presents a novel multifunctional test structure called Analog BulLt-in Block Observer (ABILBO). This structure is based on analog integrators and achieves analog scan, test frequency generation and test response compaction. A high fault coverage was obtained by using a discrete switched-capacitor ABILBO for testing a biquad filter. The ABILBO area overhead and performance penalty can be very low if functional and testing circuitry are shared. This is typically the case of high order filters based on a cascade of biquads.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130127902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569902
Keerthi Heragu, J. Patel, V. Agrawal
We propose an efficient combinational circuit simulation technique for the recently proposed segment delay fault model. After simulation of a vector pair, activated segments are traced using a depth-first search. A segment numbering scheme finds the number of faults to be simulated. A labeling technique generates edge labels to compute a unique label for each segment fault. The use of labels avoids explicit storing of fault lists and allows efficient access to previously detected segment faults. Experimental results demonstrate several advantages of the segment delay fault model. First, the total number of faults remains manageable for small segment lengths. Second, many segments, not included in any robustly testable path fault, may have robust segment delay fault tests. Generating tests for such segments may increase the delay defect coverage.
{"title":"SIGMA: A simulator for segment delay faults","authors":"Keerthi Heragu, J. Patel, V. Agrawal","doi":"10.1109/ICCAD.1996.569902","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569902","url":null,"abstract":"We propose an efficient combinational circuit simulation technique for the recently proposed segment delay fault model. After simulation of a vector pair, activated segments are traced using a depth-first search. A segment numbering scheme finds the number of faults to be simulated. A labeling technique generates edge labels to compute a unique label for each segment fault. The use of labels avoids explicit storing of fault lists and allows efficient access to previously detected segment faults. Experimental results demonstrate several advantages of the segment delay fault model. First, the total number of faults remains manageable for small segment lengths. Second, many segments, not included in any robustly testable path fault, may have robust segment delay fault tests. Generating tests for such segments may increase the delay defect coverage.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131551615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569536
Eric W. Johnson, J. Brockman
As design processes continue to increase in complexity, it is important to base process improvements on quantitative analysis. In this paper we develop an analytical approach to analyze sequential design processes using sensitivity analysis. Two applications illustrate this approach, one involving a Pareto analysis of an ASIC design process and the other an optimization of a software design process to determine the lower bound of the process completion time.
{"title":"Sensitivity analysis of iterative design processes","authors":"Eric W. Johnson, J. Brockman","doi":"10.1109/ICCAD.1996.569536","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569536","url":null,"abstract":"As design processes continue to increase in complexity, it is important to base process improvements on quantitative analysis. In this paper we develop an analytical approach to analyze sequential design processes using sensitivity analysis. Two applications illustrate this approach, one involving a Pareto analysis of an ASIC design process and the other an optimization of a software design process to determine the lower bound of the process completion time.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115213142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1007/978-1-4615-0292-0_28
A. Conn, P. Coulman, R. Haring, Gregory L. Morrill, C. Visweswariah
{"title":"Optimization of custom MOS circuits by transistor sizing","authors":"A. Conn, P. Coulman, R. Haring, Gregory L. Morrill, C. Visweswariah","doi":"10.1007/978-1-4615-0292-0_28","DOIUrl":"https://doi.org/10.1007/978-1-4615-0292-0_28","url":null,"abstract":"","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114811288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.571354
Xiao-Tao Chen, F. Lombardi
This paper presents a new approach for diagnosing stuck-at and short faults in interconnects whose layouts are known. This structural approach exploits different graph coloring and coding techniques to generate a test set with no aliasing and confounding. The conditions for aliasing and confounding are analyzed with respect to the size and number of the shorts in the fault set. The characteristics of unbalanced/balanced codes for encoding the colors in the vector generation process for interconnect diagnosis are discussed and proved using a novel algebra. An algorithm for diagnosis is then presented.
{"title":"A coloring approach to the structural diagnosis of interconnects","authors":"Xiao-Tao Chen, F. Lombardi","doi":"10.1109/ICCAD.1996.571354","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.571354","url":null,"abstract":"This paper presents a new approach for diagnosing stuck-at and short faults in interconnects whose layouts are known. This structural approach exploits different graph coloring and coding techniques to generate a test set with no aliasing and confounding. The conditions for aliasing and confounding are analyzed with respect to the size and number of the shorts in the fault set. The characteristics of unbalanced/balanced codes for encoding the colors in the vector generation process for interconnect diagnosis are discussed and proved using a novel algebra. An algorithm for diagnosis is then presented.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125908705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569908
Scott Woods, G. Casinovi
This paper describes an algorithm for the efficient solution of large systems of Boolean equations. The algorithm exploits the fact that, in some cases, the composition operation of Boolean functions represented by BDD's can be performed in a very efficient manner. Thus, the algorithm tries to eliminate as many variables and equations as possible through function composition. When the system can no longer be reduced in this way, the elimination process is continued through the use of Shannon decomposition. Numerical results show that the performance of this algorithm is significantly superior to that of a previous algorithm proposed by the authors.
{"title":"Efficient solution of systems of Boolean equations","authors":"Scott Woods, G. Casinovi","doi":"10.1109/ICCAD.1996.569908","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569908","url":null,"abstract":"This paper describes an algorithm for the efficient solution of large systems of Boolean equations. The algorithm exploits the fact that, in some cases, the composition operation of Boolean functions represented by BDD's can be performed in a very efficient manner. Thus, the algorithm tries to eliminate as many variables and equations as possible through function composition. When the system can no longer be reduced in this way, the elimination process is continued through the use of Shannon decomposition. Numerical results show that the performance of this algorithm is significantly superior to that of a previous algorithm proposed by the authors.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126319117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.568905
S. Corey, A. Yang
An approach is presented for modeling board level, package-level, and MCM substrate-level interconnect circuitry based an measured time domain refectometry data. The time-domain scattering parameters of a multiport system are used to extract a SPICE netlist which uses standard elements to match the behavior of the device up to a user-specified cutoff frequency. Linear or nonlinear circuits may be connected to the model ports, and the entire circuit simulated in a standard circuit simulator. Two-port and four-port example microstrip circuits are characterized, and the simulation results are compared with measured data. Delay, reflection transmission, and crosstalk are accurately modeled in each case.
{"title":"Automatic netlist extraction for measurement-based characterization of off-chip interconnect","authors":"S. Corey, A. Yang","doi":"10.1109/ICCAD.1996.568905","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.568905","url":null,"abstract":"An approach is presented for modeling board level, package-level, and MCM substrate-level interconnect circuitry based an measured time domain refectometry data. The time-domain scattering parameters of a multiport system are used to extract a SPICE netlist which uses standard elements to match the behavior of the device up to a user-specified cutoff frequency. Linear or nonlinear circuits may be connected to the model ports, and the entire circuit simulated in a standard circuit simulator. Two-port and four-port example microstrip circuits are characterized, and the simulation results are compared with measured data. Delay, reflection transmission, and crosstalk are accurately modeled in each case.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125809700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this study, we present a controllability measure for high-level circuit descriptions and a high-level synthesis-for-testability technique. Unlike many studies in the area of high-level synthesis for testability that focus on improving the testability of data paths, the objective of our approach is to improve the testability of synthesized circuits by enhancing the controllability of the control flow. Experimental results on several high-level synthesis benchmarks show that when this approach is used prior to logic synthesis, a shorter ATPG time, a smaller test set, and better fault coverage and ATPG efficiency are often achieved. Implementation of this technique requires minimal logic and performance overheads and allows test vectors to be applied at clock-speed.
{"title":"Enhancing high-level control-flow for improved testability","authors":"Frank F. Hsu, E. Rudnick, J. Patel","doi":"10.5555/244522.244823","DOIUrl":"https://doi.org/10.5555/244522.244823","url":null,"abstract":"In this study, we present a controllability measure for high-level circuit descriptions and a high-level synthesis-for-testability technique. Unlike many studies in the area of high-level synthesis for testability that focus on improving the testability of data paths, the objective of our approach is to improve the testability of synthesized circuits by enhancing the controllability of the control flow. Experimental results on several high-level synthesis benchmarks show that when this approach is used prior to logic synthesis, a shorter ATPG time, a smaller test set, and better fault coverage and ATPG efficiency are often achieved. Implementation of this technique requires minimal logic and performance overheads and allows test vectors to be applied at clock-speed.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124848585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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