Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569833
E. Sentovich, Horia Toma, G. Berry
In a gate-level description of a finite state machine (FSM), there is a tradeoff between the number of latches and the size of the logic implementing the next-state and output functions. Typically, an initial implementation is generated via explicit state assignment or translation from a high-level language, and the tradeoff is subsequently only lightly explored. We efficiently explore good latch/logic tradeoffs for large designs generated from high-level specifications. We reduce the number of latches while controlling the logic size. We demonstrate the efficacy of our techniques on some large industrial examples.
{"title":"Latch optimization in circuits generated from high-level descriptions","authors":"E. Sentovich, Horia Toma, G. Berry","doi":"10.1109/ICCAD.1996.569833","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569833","url":null,"abstract":"In a gate-level description of a finite state machine (FSM), there is a tradeoff between the number of latches and the size of the logic implementing the next-state and output functions. Typically, an initial implementation is generated via explicit state assignment or translation from a high-level language, and the tradeoff is subsequently only lightly explored. We efficiently explore good latch/logic tradeoffs for large designs generated from high-level specifications. We reduce the number of latches while controlling the logic size. We demonstrate the efficacy of our techniques on some large industrial examples.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131375814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569613
Edward A. Lee, A. Sangiovanni-Vincentelli
We give a denotational framework (a meta model) within which certain properties of models of computation can be understood and compared. It describes concurrent processes as sets of possible behaviors. Compositions of processes are given as intersections of their behaviors. The interaction between processes is through signals, which are collections of events. Each event is a value-tag pair, where the tags can come from a partially ordered or totally ordered set. Timed models are where the set of tags is totally ordered. Synchronous events share the same tag, and synchronous signals contain events with the same set of tags. Synchronous systems contain synchronous signals. Strict causality (in timed systems) and continuity (in untimed systems) ensure determinacy under certain technical conditions. The framework is used to compare certain essential features of various models of computation, including Kahn process networks, dataflow, sequential processes, concurrent sequential processes with rendezvous, Petri nets, and discrete-event systems.
{"title":"Comparing models of computation","authors":"Edward A. Lee, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCAD.1996.569613","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569613","url":null,"abstract":"We give a denotational framework (a meta model) within which certain properties of models of computation can be understood and compared. It describes concurrent processes as sets of possible behaviors. Compositions of processes are given as intersections of their behaviors. The interaction between processes is through signals, which are collections of events. Each event is a value-tag pair, where the tags can come from a partially ordered or totally ordered set. Timed models are where the set of tags is totally ordered. Synchronous events share the same tag, and synchronous signals contain events with the same set of tags. Synchronous systems contain synchronous signals. Strict causality (in timed systems) and continuity (in untimed systems) ensure determinacy under certain technical conditions. The framework is used to compare certain essential features of various models of computation, including Kahn process networks, dataflow, sequential processes, concurrent sequential processes with rendezvous, Petri nets, and discrete-event systems.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130633867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569915
D. Ciplickas, R. Rohrer
The analysis of CMOS VLSI circuit switching current has become an increasingly important and difficult task from both a VLSI design and simulation software perspective. This paper presents a new static switching current estimation algorithm based on the idea of "Expected Current Distributions" (ECDs). Unlike previous "expected waveform" approaches, ECDs model not only the expected value of switching current waveforms over all time, but also the variances and covariances of all waveform segments as well. This extra information allows a switching current waveform to be modeled by a random process with both first and second order ensemble statistics. This specification provides the power spectral density of the switching current and allows the use of traditional frequency domain noise analysis to simulate the behavior of the switching current in the electrical supply network. An ECD simulation procedure is described and results are presented for the ISCAS85 combinational benchmark circuits. Estimated quantities include total average and RMS VDD current, the autocorrelation function of the total VDD current waveform, and per-gate average and RMS VDD currents. The results show speedups of up to 100 x and good agreement with respect to figures obtained using dynamic logic simulation and statistical mean estimation.
{"title":"Expected current distributions for CMOS circuits","authors":"D. Ciplickas, R. Rohrer","doi":"10.1109/ICCAD.1996.569915","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569915","url":null,"abstract":"The analysis of CMOS VLSI circuit switching current has become an increasingly important and difficult task from both a VLSI design and simulation software perspective. This paper presents a new static switching current estimation algorithm based on the idea of \"Expected Current Distributions\" (ECDs). Unlike previous \"expected waveform\" approaches, ECDs model not only the expected value of switching current waveforms over all time, but also the variances and covariances of all waveform segments as well. This extra information allows a switching current waveform to be modeled by a random process with both first and second order ensemble statistics. This specification provides the power spectral density of the switching current and allows the use of traditional frequency domain noise analysis to simulate the behavior of the switching current in the electrical supply network. An ECD simulation procedure is described and results are presented for the ISCAS85 combinational benchmark circuits. Estimated quantities include total average and RMS VDD current, the autocorrelation function of the total VDD current waveform, and per-gate average and RMS VDD currents. The results show speedups of up to 100 x and good agreement with respect to figures obtained using dynamic logic simulation and statistical mean estimation.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115005306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569903
M. Amin, B. Vinnakota
We present a new multiprocessor sequential circuit fault simulator, Zamlog, based on a novel uniprocessor simulator, Zambezi. Both the fault and test sets are partitioned for multiprocessor simulation. The parallelization technique, designed to preserve the efficiency of Zambezi, is simple to implement and has low communication requirements. Experimental results indicate that Zamlog can obtain speedups of up to 95. The speedups obtained and the scalability are between 3 and 10 times better than any reported in the literature. Furthermore, the speed-ups obtained are with respect to a uniprocessor algorithm which is superior, by an average of 40%, to those used to gauge the speed-ups of previous parallel systems.
{"title":"Zamlog: a parallel algorithm for fault simulation based on Zambezi","authors":"M. Amin, B. Vinnakota","doi":"10.1109/ICCAD.1996.569903","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569903","url":null,"abstract":"We present a new multiprocessor sequential circuit fault simulator, Zamlog, based on a novel uniprocessor simulator, Zambezi. Both the fault and test sets are partitioned for multiprocessor simulation. The parallelization technique, designed to preserve the efficiency of Zambezi, is simple to implement and has low communication requirements. Experimental results indicate that Zamlog can obtain speedups of up to 95. The speedups obtained and the scalability are between 3 and 10 times better than any reported in the literature. Furthermore, the speed-ups obtained are with respect to a uniprocessor algorithm which is superior, by an average of 40%, to those used to gauge the speed-ups of previous parallel systems.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125276439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.568901
R. Puri, A. Bjorksten, T. Rosser
Domino logic is one of the most popular dynamic circuit configurations for implementing high-performance logic designs. Since domino logic is inherently noninverting, it presents a fundamental constraint of implementing logic functions without any intermediate inversions. Removal of intermediate inverters requires logic duplication for generating both the negative and positive signal phases, which results in significant area overhead. This area overhead can be substantially reduced by selecting an optimal output phase assignment, which results in a minimum logic duplication penalty for obtaining inverter-free logic. In this paper, we present this previously unaddressed problem of output phase assignment for minimum area duplication in dynamic logic synthesis. We give both optimal and heuristic algorithms for minimizing logic duplication.
{"title":"Logic optimization by output phase assignment in dynamic logic synthesis","authors":"R. Puri, A. Bjorksten, T. Rosser","doi":"10.1109/ICCAD.1996.568901","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.568901","url":null,"abstract":"Domino logic is one of the most popular dynamic circuit configurations for implementing high-performance logic designs. Since domino logic is inherently noninverting, it presents a fundamental constraint of implementing logic functions without any intermediate inversions. Removal of intermediate inverters requires logic duplication for generating both the negative and positive signal phases, which results in significant area overhead. This area overhead can be substantially reduced by selecting an optimal output phase assignment, which results in a minimum logic duplication penalty for obtaining inverter-free logic. In this paper, we present this previously unaddressed problem of output phase assignment for minimum area duplication in dynamic logic synthesis. We give both optimal and heuristic algorithms for minimizing logic duplication.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"51 5-6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120919258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569834
S. Chaudhuri, M. Quayle
This paper presents a new method used in our RTL-synthesis tool to perform technology mapping with Sequential Functional Modules (SFMs) such as counters, accumulators, shift-registers, or rotators from any target or macro library. If the library contains SFMs, the method automatically recognizes them. If an RTL design contains patterns that can be implemented on SFMs, the method maps them to the SFMs found in the target library. This mapping reduces the design time by leveraging the library developer's effort, leads to more regular and often smaller and faster designs, and helps to reduce timing and routing problems at later stages of the design process.
{"title":"Synthesis using Sequential Functional Modules (SFMs)","authors":"S. Chaudhuri, M. Quayle","doi":"10.1109/ICCAD.1996.569834","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569834","url":null,"abstract":"This paper presents a new method used in our RTL-synthesis tool to perform technology mapping with Sequential Functional Modules (SFMs) such as counters, accumulators, shift-registers, or rotators from any target or macro library. If the library contains SFMs, the method automatically recognizes them. If an RTL design contains patterns that can be implemented on SFMs, the method maps them to the SFMs found in the target library. This mapping reduces the design time by leveraging the library developer's effort, leads to more regular and often smaller and faster designs, and helps to reduce timing and routing problems at later stages of the design process.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"53 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121388648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569409
R. Leupers, P. Marwedel
This paper presents DSP code optimization techniques, which originate from dedicated memory address generation hardware. We define a generic model of DSP address generation units. Based on this model we present efficient heuristics for computing memory layouts for program variables, which optimize utilization of parallel address generation units. Improvements and generalizations of previous work are described, and the efficacy of the proposed algorithms is demonstrated through experimental evaluation.
{"title":"Algorithms for address assignment in DSP code generation","authors":"R. Leupers, P. Marwedel","doi":"10.1109/ICCAD.1996.569409","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569409","url":null,"abstract":"This paper presents DSP code optimization techniques, which originate from dedicated memory address generation hardware. We define a generic model of DSP address generation units. Based on this model we present efficient heuristics for computing memory layouts for program variables, which optimize utilization of parallel address generation units. Improvements and generalizations of previous work are described, and the efficacy of the proposed algorithms is demonstrated through experimental evaluation.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133856624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569832
S. Devadas, Abhijit Ghosh, K. Keutzer
Functional simulation is the most widely used method for design verification. At various levels of abstraction, e.g., behavioral, register-transfer level and gate level, the designer simulates the design using a large number of vectors attempting to debug and verify the design. A major problem with functional simulation is the lack of good metrics and tools to evaluate the quality of a set of functional vectors. Metrics used currently are based on instruction counts and are quite simplistic. Designers are forced to use ad-hoc methods to terminate functional simulation, e.g., CPU time limitations, We propose a new metric for measuring the extent of design verification provided by a set of functional simulation vectors. This metric is universal, and can be used uniformly for all designs. Our metric computes observability information to determine whether effects of errors that are activated by the program stimuli can be observed at the circuit outputs. We provide preliminary experimental evidence that supports the validity of the proposed metric. We believe that using this metric in design verification will result in higher-quality functional tests and improved correctness checking.
{"title":"An observability-based code coverage metric for functional simulation","authors":"S. Devadas, Abhijit Ghosh, K. Keutzer","doi":"10.1109/ICCAD.1996.569832","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569832","url":null,"abstract":"Functional simulation is the most widely used method for design verification. At various levels of abstraction, e.g., behavioral, register-transfer level and gate level, the designer simulates the design using a large number of vectors attempting to debug and verify the design. A major problem with functional simulation is the lack of good metrics and tools to evaluate the quality of a set of functional vectors. Metrics used currently are based on instruction counts and are quite simplistic. Designers are forced to use ad-hoc methods to terminate functional simulation, e.g., CPU time limitations, We propose a new metric for measuring the extent of design verification provided by a set of functional simulation vectors. This metric is universal, and can be used uniformly for all designs. Our metric computes observability information to determine whether effects of errors that are activated by the program stimuli can be observed at the circuit outputs. We provide preliminary experimental evidence that supports the validity of the proposed metric. We believe that using this metric in design verification will result in higher-quality functional tests and improved correctness checking.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125811886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.571334
Inki Hong, M. Potkonjak
While numerous power optimization techniques have been proposed at all levels of design process abstractions for electronic components, until now, power minimization in mixed mechanical-electronic subsystems, such as disks, has not been addressed. We propose a conceptually simple, but realistic power consumption model for disk drives. We present heuristics for optimization of power consumption in several common hard real-time disk-based design systems. We show how to coordinate task scheduling and disk data assignment, in order to minimize power consumption in both electronic and mechanical components of used disks. Extensive experimental results indicate significant power reduction.
{"title":"Power optimization in disk-based real-time application specific systems","authors":"Inki Hong, M. Potkonjak","doi":"10.1109/ICCAD.1996.571334","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.571334","url":null,"abstract":"While numerous power optimization techniques have been proposed at all levels of design process abstractions for electronic components, until now, power minimization in mixed mechanical-electronic subsystems, such as disks, has not been addressed. We propose a conceptually simple, but realistic power consumption model for disk drives. We present heuristics for optimization of power consumption in several common hard real-time disk-based design systems. We show how to coordinate task scheduling and disk data assignment, in order to minimize power consumption in both electronic and mechanical components of used disks. Extensive experimental results indicate significant power reduction.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126081610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.571365
Wojciech Maly, H. Heineken, J. Khare, P. Nag
Key characteristics of newly emerging IC technologies render the traditional concept of die size minimization and traditional "design rules" insufficient to handle the design-manufacturing interface. This tutorial surveys the design and process characteristics relevant to the manufacturability of submicron ICs. The discussion also covers analysis of design for manufacturability (DFM) trade-offs. Yield and cost models needed to analyze these trade-offs are explained as well.
{"title":"Design for manufacturability in submicron domain","authors":"Wojciech Maly, H. Heineken, J. Khare, P. Nag","doi":"10.1109/ICCAD.1996.571365","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.571365","url":null,"abstract":"Key characteristics of newly emerging IC technologies render the traditional concept of die size minimization and traditional \"design rules\" insufficient to handle the design-manufacturing interface. This tutorial surveys the design and process characteristics relevant to the manufacturability of submicron ICs. The discussion also covers analysis of design for manufacturability (DFM) trade-offs. Yield and cost models needed to analyze these trade-offs are explained as well.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126884501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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