Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569825
W. Hong, W. Sun, Zhenhai Zhu, Hao Ji, Ben Song, W. Dai
In this paper, we present a new capacitance extraction method named Dimension Reduction Technique (DRT) for 3D VLSI interconnects. The DRT converts a complex 3D problem into a series of cascading simple 2D problems. Each 3D problem is solved separately, so we can choose the most efficient method according to the arrangement of conductors. More importantly, it is very easy to obtain the analytical solutions of 2D problem in many layers such as the pure dielectric layers and the layers with parallel signal lines. Therefore, the domain that has to be analyzed numerically is minimized. This leads to the drastic reduction of the computing time and memory needs. We have used the DRT to extract the capacitances of multilayered and multiconductor cross-overs, bends, via with signal lines and open-end. The results are in good agreement with those of Ansoft's SPICELINK and MIT's FastCap, but the computing time and memory size used by the DRT are several even tens times less than those used by SPICELINK and FastCap.
{"title":"A novel dimension reduction technique for the capacitance extraction of 3D VLSI interconnects","authors":"W. Hong, W. Sun, Zhenhai Zhu, Hao Ji, Ben Song, W. Dai","doi":"10.1109/ICCAD.1996.569825","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569825","url":null,"abstract":"In this paper, we present a new capacitance extraction method named Dimension Reduction Technique (DRT) for 3D VLSI interconnects. The DRT converts a complex 3D problem into a series of cascading simple 2D problems. Each 3D problem is solved separately, so we can choose the most efficient method according to the arrangement of conductors. More importantly, it is very easy to obtain the analytical solutions of 2D problem in many layers such as the pure dielectric layers and the layers with parallel signal lines. Therefore, the domain that has to be analyzed numerically is minimized. This leads to the drastic reduction of the computing time and memory needs. We have used the DRT to extract the capacitances of multilayered and multiconductor cross-overs, bends, via with signal lines and open-end. The results are in good agreement with those of Ansoft's SPICELINK and MIT's FastCap, but the computing time and memory size used by the DRT are several even tens times less than those used by SPICELINK and FastCap.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130867161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569712
P. Feldmann, J. Roychowdhury
In this paper we introduce a novel algorithm for numerically computing the "slow" dynamics (envelope) of circuits in which a "fast" varying carrier signal as also present. The algorithm proceeds at the rate of the slow behavior and its computational cost is fairly insensitive to the rate of the fast signals. The envelope computation problem is formulated as a differential-algebraic system of equations (DAEs) in terms of frequency-domain quantities (e.g. amplitudes and phases) that capture the fast varying behavior of the circuit. The solution of this DAE represents the "slow" variation of these quantities, i.e., the envelope. The efficiency of this method is the result of using the most appropriate method for each of the circuit modes: harmonic balance for the fast behavior and time-domain integration of DAEs for the slow behavior. The paper describes the theoretical foundations of the algorithm and presents several circuit analysis examples.
{"title":"Computation of circuit waveform envelopes using an efficient, matrix-decomposed harmonic balance algorithm","authors":"P. Feldmann, J. Roychowdhury","doi":"10.1109/ICCAD.1996.569712","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569712","url":null,"abstract":"In this paper we introduce a novel algorithm for numerically computing the \"slow\" dynamics (envelope) of circuits in which a \"fast\" varying carrier signal as also present. The algorithm proceeds at the rate of the slow behavior and its computational cost is fairly insensitive to the rate of the fast signals. The envelope computation problem is formulated as a differential-algebraic system of equations (DAEs) in terms of frequency-domain quantities (e.g. amplitudes and phases) that capture the fast varying behavior of the circuit. The solution of this DAE represents the \"slow\" variation of these quantities, i.e., the envelope. The efficiency of this method is the result of using the most appropriate method for each of the circuit modes: harmonic balance for the fast behavior and time-domain integration of DAEs for the slow behavior. The paper describes the theoretical foundations of the algorithm and presents several circuit analysis examples.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130217584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569537
R. Ho, M. Horowitz
The functional validation of a state-of-the-art digital design is usually performed by simulation of a register-transfer-level model. The degree to which the test vector suite covers the important tests is known as the coverage of the suite. Previous coverage metrics have relied on measures such as the number of simulated cycles or number of toggles on a circuit node, which are indirect metrics at best. This paper proposes a new method of analyzing coverage based on projecting a minimized control finite-state graph onto control signals for the datapath part of the design to yield a meaningful metric and provide detailed feedback about missing tests. The largest hurdle is state-space explosion. We describe two methods of dealing with this in a practical manner and give results of applying this coverage analysis to parts of the node controller of the Stanford FLASH multiprocessor.
{"title":"Validation coverage analysis for complex digital designs","authors":"R. Ho, M. Horowitz","doi":"10.1109/ICCAD.1996.569537","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569537","url":null,"abstract":"The functional validation of a state-of-the-art digital design is usually performed by simulation of a register-transfer-level model. The degree to which the test vector suite covers the important tests is known as the coverage of the suite. Previous coverage metrics have relied on measures such as the number of simulated cycles or number of toggles on a circuit node, which are indirect metrics at best. This paper proposes a new method of analyzing coverage based on projecting a minimized control finite-state graph onto control signals for the datapath part of the design to yield a meaningful metric and provide detailed feedback about missing tests. The largest hurdle is state-space explosion. We describe two methods of dealing with this in a practical manner and give results of applying this coverage analysis to parts of the node controller of the Stanford FLASH multiprocessor.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"488 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130038339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569912
S. Kapur, D. Long, J. Roychowdhury
We describe an efficient algorithm for time-domain simulation of elements described by causal impulse responses. The computational bottleneck in the simulation of such elements is the need to compute convolutions at each time point. Hence, direct approaches for the simulation of such elements require time O(N/sup 2/), where N is the length of the simulation. We apply ideas from approximation theory to reduce this complexity to O(N log N) while maintaining double-precision accuracy. The only restriction imposed by our method is that the impulse response h(t) gets "smoother" as t goes to infinity. Essentially all physically reasonable impulse responses have this characteristic. The ideas presented can also be applied to time-domain simulation of elements described in the frequency domain, including those characterized by measured data. In this paper, we demonstrate the efficiency of the algorithm by applying it to the simulation of lossy transmission lines.
{"title":"Efficient time-domain simulation of frequency-dependent elements","authors":"S. Kapur, D. Long, J. Roychowdhury","doi":"10.1109/ICCAD.1996.569912","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569912","url":null,"abstract":"We describe an efficient algorithm for time-domain simulation of elements described by causal impulse responses. The computational bottleneck in the simulation of such elements is the need to compute convolutions at each time point. Hence, direct approaches for the simulation of such elements require time O(N/sup 2/), where N is the length of the simulation. We apply ideas from approximation theory to reduce this complexity to O(N log N) while maintaining double-precision accuracy. The only restriction imposed by our method is that the impulse response h(t) gets \"smoother\" as t goes to infinity. Essentially all physically reasonable impulse responses have this characteristic. The ideas presented can also be applied to time-domain simulation of elements described in the frequency domain, including those characterized by measured data. In this paper, we demonstrate the efficiency of the algorithm by applying it to the simulation of lossy transmission lines.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"238 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123198799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569866
T. Yamanouchi, Kazuo Tamakashi, T. Kambe
In this paper, we propose a hybrid floorplanning methodology. Two hierarchical strategies for avoiding local optima during iterative improvement are proposed: (1) Partial Clustering, and (2) Module Restructuring. These strategies work for localizing nets connecting small modules in small regions, and conceal such small modules and their nets during the iterative improvement phase. This method is successful in reducing both area and wire length in addition to reducing the computational time required for optimization. Although our method only searches slicing floorplans, the results are superior to the results obtained even with non-slicing floorplans. We applied our method to the largest MCNC floorplan benchmark example, ami49, and industrial data. For the ami49 benchmark, we obtained results superior to any published results for both estimated area and routing results.
{"title":"Hybrid floorplanning based on partial clustering and module restructuring","authors":"T. Yamanouchi, Kazuo Tamakashi, T. Kambe","doi":"10.1109/ICCAD.1996.569866","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569866","url":null,"abstract":"In this paper, we propose a hybrid floorplanning methodology. Two hierarchical strategies for avoiding local optima during iterative improvement are proposed: (1) Partial Clustering, and (2) Module Restructuring. These strategies work for localizing nets connecting small modules in small regions, and conceal such small modules and their nets during the iterative improvement phase. This method is successful in reducing both area and wire length in addition to reducing the computational time required for optimization. Although our method only searches slicing floorplans, the results are superior to the results obtained even with non-slicing floorplans. We applied our method to the largest MCNC floorplan benchmark example, ami49, and industrial data. For the ami49 benchmark, we obtained results superior to any published results for both estimated area and routing results.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126137342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.568939
D. Lehther, S. Sapatnekar
While designing interconnect for MCMs, one must take into consideration the distributed RLC effects, due to which signals may display nonmonotonic behavior and substantial ringing. This paper considers the problem of designing clock trees for MCMs. A fully distributed RLC model is utilized for AWE-based analysis and synthesis, and appropriate measures are taken to ensure adequate signal damping and for buffer insertion to satisfy constraints on the clock signal slew rate. Experimental results, verified by SPICE simulations, show that this method can be used to build clock trees with near-zero skews.
{"title":"Clock tree synthesis for multi-chip modules","authors":"D. Lehther, S. Sapatnekar","doi":"10.1109/ICCAD.1996.568939","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.568939","url":null,"abstract":"While designing interconnect for MCMs, one must take into consideration the distributed RLC effects, due to which signals may display nonmonotonic behavior and substantial ringing. This paper considers the problem of designing clock trees for MCMs. A fully distributed RLC model is utilized for AWE-based analysis and synthesis, and appropriate measures are taken to ensure adequate signal damping and for buffer insertion to satisfy constraints on the clock signal slew rate. Experimental results, verified by SPICE simulations, show that this method can be used to build clock trees with near-zero skews.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115485984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569909
A. Narayan, J. Jain, M. Fujita, A. Sangiovanni-Vincentelli
We present a new representation for Boolean functions called Partitioned ROBDDs. In this representation we divide the Boolean space into 'k' partitions and represent a function over each partition as a separate ROBDD. We show that partitioned-ROBDDs are canonical and can be efficiently manipulated. Further they can be exponentially more compact than monolithic ROBDDs and even free BDDs. Moreover, at any given time, only one partition needs to be manipulated which further increases the space efficiency. In addition to showing the utility of partitioned-ROBDDs on special classes of functions, we provide automatic techniques for their construction. We show that for large circuits our techniques are more efficient in space as well as time over monolithic ROBDDs. Using these techniques, some complex industrial circuits could be verified for the first time.
{"title":"Partitioned ROBDDs-a compact, canonical and efficiently manipulable representation for Boolean functions","authors":"A. Narayan, J. Jain, M. Fujita, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCAD.1996.569909","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569909","url":null,"abstract":"We present a new representation for Boolean functions called Partitioned ROBDDs. In this representation we divide the Boolean space into 'k' partitions and represent a function over each partition as a separate ROBDD. We show that partitioned-ROBDDs are canonical and can be efficiently manipulated. Further they can be exponentially more compact than monolithic ROBDDs and even free BDDs. Moreover, at any given time, only one partition needs to be manipulated which further increases the space efficiency. In addition to showing the utility of partitioned-ROBDDs on special classes of functions, we provide automatic techniques for their construction. We show that for large circuits our techniques are more efficient in space as well as time over monolithic ROBDDs. Using these techniques, some complex industrial circuits could be verified for the first time.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125877009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1007/978-1-4615-0292-0_7
Joao Marques-Silva, K. Sakallah
{"title":"GRASP-A new search algorithm for satisfiability","authors":"Joao Marques-Silva, K. Sakallah","doi":"10.1007/978-1-4615-0292-0_7","DOIUrl":"https://doi.org/10.1007/978-1-4615-0292-0_7","url":null,"abstract":"","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125842458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569621
N. V. D. Meijs, T. Smedes
In this paper we discuss concepts and techniques for the accurate and efficient modeling and extraction of interconnect parasitics in VLSI designs. Due to increasing operating frequencies, microwave-like effects will become important. Therefore stronger demands are put on extraction and verification tools. We indicate the state-of-the-art for capacitance, resistance and substrate resistance extraction and discuss some open problems. We also discuss several model reduction techniques as well as issues related to simulation and implementation in a CAD system.
{"title":"Accurate interconnect modeling: Towards multi-million transistor chips as microwave circuits","authors":"N. V. D. Meijs, T. Smedes","doi":"10.1109/ICCAD.1996.569621","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569621","url":null,"abstract":"In this paper we discuss concepts and techniques for the accurate and efficient modeling and extraction of interconnect parasitics in VLSI designs. Due to increasing operating frequencies, microwave-like effects will become important. Therefore stronger demands are put on extraction and verification tools. We indicate the state-of-the-art for capacitance, resistance and substrate resistance extraction and discuss some open problems. We also discuss several model reduction techniques as well as issues related to simulation and implementation in a CAD system.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131041855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569707
R. Freund, P. Feldmann
This paper discusses the analysis of large linear electrical networks consisting of passive components, such as resistors, capacitors, inductors, and transformers. Such networks admit a symmetric formulation of their circuit equations. We introduce SyPVL, an efficient and numerically stable algorithm for the computation of reduced-order models of large, linear, passive networks. SyPVL represents the specialization of the more general PVL algorithm, to symmetric problems. Besides the gain in efficiency over PVL, SyPVL also preserves the symmetry of the problem, and, as a consequence, can often guarantee the stability of the resulting reduced-order models. Moreover, these reduced-order models can be synthesized as actual physical circuits, thus facilitating compatibility with existing analysis tools. The application of SyPVL is illustrated with two interconnect-analysis examples.
{"title":"Reduced-order modeling of large passive linear circuits by means of the SyPVL algorithm","authors":"R. Freund, P. Feldmann","doi":"10.1109/ICCAD.1996.569707","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569707","url":null,"abstract":"This paper discusses the analysis of large linear electrical networks consisting of passive components, such as resistors, capacitors, inductors, and transformers. Such networks admit a symmetric formulation of their circuit equations. We introduce SyPVL, an efficient and numerically stable algorithm for the computation of reduced-order models of large, linear, passive networks. SyPVL represents the specialization of the more general PVL algorithm, to symmetric problems. Besides the gain in efficiency over PVL, SyPVL also preserves the symmetry of the problem, and, as a consequence, can often guarantee the stability of the resulting reduced-order models. Moreover, these reduced-order models can be synthesized as actual physical circuits, thus facilitating compatibility with existing analysis tools. The application of SyPVL is illustrated with two interconnect-analysis examples.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131175775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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