Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569621
N. V. D. Meijs, T. Smedes
In this paper we discuss concepts and techniques for the accurate and efficient modeling and extraction of interconnect parasitics in VLSI designs. Due to increasing operating frequencies, microwave-like effects will become important. Therefore stronger demands are put on extraction and verification tools. We indicate the state-of-the-art for capacitance, resistance and substrate resistance extraction and discuss some open problems. We also discuss several model reduction techniques as well as issues related to simulation and implementation in a CAD system.
{"title":"Accurate interconnect modeling: Towards multi-million transistor chips as microwave circuits","authors":"N. V. D. Meijs, T. Smedes","doi":"10.1109/ICCAD.1996.569621","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569621","url":null,"abstract":"In this paper we discuss concepts and techniques for the accurate and efficient modeling and extraction of interconnect parasitics in VLSI designs. Due to increasing operating frequencies, microwave-like effects will become important. Therefore stronger demands are put on extraction and verification tools. We indicate the state-of-the-art for capacitance, resistance and substrate resistance extraction and discuss some open problems. We also discuss several model reduction techniques as well as issues related to simulation and implementation in a CAD system.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131041855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.571327
B. Iyer, M. Ciesielski
This paper presents Metamorphosis-a novel technique for optimal state assignment targeting multi-level logic implementations. We present an elegant matrix formulation and a graph partitioning based synthesis technique which permits both bit-constrained and unconstrained encoding of a symbolic finite state machine (FSM) represented initially with a one-hot code. Optimal state encoding is achieved by controlled retiming/re-encoding and resynthesis of the symbolic FSM. The synthesis is guided directly by the cost function (optimization criterion) rather than speculative estimates of the encoding heuristics on the final design cost. The technique is illustrated through performance driven synthesis of FSM and extensions to handle other cost metrics is outlined.
{"title":"Metamorphosis: state assignment by retiming and re-encoding","authors":"B. Iyer, M. Ciesielski","doi":"10.1109/ICCAD.1996.571327","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.571327","url":null,"abstract":"This paper presents Metamorphosis-a novel technique for optimal state assignment targeting multi-level logic implementations. We present an elegant matrix formulation and a graph partitioning based synthesis technique which permits both bit-constrained and unconstrained encoding of a symbolic finite state machine (FSM) represented initially with a one-hot code. Optimal state encoding is achieved by controlled retiming/re-encoding and resynthesis of the symbolic FSM. The synthesis is guided directly by the cost function (optimization criterion) rather than speculative estimates of the encoding heuristics on the final design cost. The technique is illustrated through performance driven synthesis of FSM and extensions to handle other cost metrics is outlined.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133834053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.571340
S. Minato
We propose a new method for generating BDDs from hardware algorithm descriptions written in a programming language. Our system can deal with control structures, such as conditional branches (if-then-else) and data dependent loops (while-end). Once BDDs are generated, we can immediately check the equivalence of two different algorithm descriptions just by comparing BDDs. This method can also be applied to verification between algorithm-level and gate-level designs. Another interesting application is to synthesize loop-free logic circuits from algorithm descriptions. We show the experimental results for some practical examples, such as Greatest Common Divisor (GCD) calculation. Although our method has a limitation in size of problems, it is very practical and useful for actual design verification.
{"title":"Generation of BDDs from hardware algorithm descriptions","authors":"S. Minato","doi":"10.1109/ICCAD.1996.571340","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.571340","url":null,"abstract":"We propose a new method for generating BDDs from hardware algorithm descriptions written in a programming language. Our system can deal with control structures, such as conditional branches (if-then-else) and data dependent loops (while-end). Once BDDs are generated, we can immediately check the equivalence of two different algorithm descriptions just by comparing BDDs. This method can also be applied to verification between algorithm-level and gate-level designs. Another interesting application is to synthesize loop-free logic circuits from algorithm descriptions. We show the experimental results for some practical examples, such as Greatest Common Divisor (GCD) calculation. Although our method has a limitation in size of problems, it is very practical and useful for actual design verification.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131080485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.571363
K. Chakraborty, P. Mazumder
This paper presents a new, layout-based approach to board-level shorts diagnosis for bussed drivers, with the goal of early repair of interconnect shorts so as to minimize (a) fault masking during opens testing and (b) driver abuse. This approach leads to an early diagnosis of more than 96% of shorts and simplifies the subsequent rest for opens considerably. Besides, this approach improves the production yield and field survivability of boards.
{"title":"An efficient, bus-layout based method for early diagnosis of bussed driver shorts in printed circuit boards","authors":"K. Chakraborty, P. Mazumder","doi":"10.1109/ICCAD.1996.571363","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.571363","url":null,"abstract":"This paper presents a new, layout-based approach to board-level shorts diagnosis for bussed drivers, with the goal of early repair of interconnect shorts so as to minimize (a) fault masking during opens testing and (b) driver abuse. This approach leads to an early diagnosis of more than 96% of shorts and simplifies the subsequent rest for opens considerably. Besides, this approach improves the production yield and field survivability of boards.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134540765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569803
H. Wunderlich, G. Kiefer
A scan-based BIST scheme is presented which guarantees complete fault coverage with very low hardware overhead. A probabilistic analysis shows that the output of an LFSR which feeds a scan path has to be modified only at a few bits in order to transform the random patterns into a complete test set. These modifications may be implemented by a bit-flipping function which has the LFSR-state as an input, and flips the value shifted into the scan path at certain times. A procedure is described for synthesizing the additional bit-flipping circuitry, and the experimental results indicate that this mixed-mode BIST scheme requires less hardware for complete fault coverage than all the other scan-based BIST approaches published so far.
{"title":"Bit-flipping BIST","authors":"H. Wunderlich, G. Kiefer","doi":"10.1109/ICCAD.1996.569803","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569803","url":null,"abstract":"A scan-based BIST scheme is presented which guarantees complete fault coverage with very low hardware overhead. A probabilistic analysis shows that the output of an LFSR which feeds a scan path has to be modified only at a few bits in order to transform the random patterns into a complete test set. These modifications may be implemented by a bit-flipping function which has the LFSR-state as an input, and flips the value shifted into the scan path at certain times. A procedure is described for synthesizing the additional bit-flipping circuitry, and the experimental results indicate that this mixed-mode BIST scheme requires less hardware for complete fault coverage than all the other scan-based BIST approaches published so far.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131297942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569170
Youngsoo Shin, Kiyoung Choi
Latency tolerance is one of main problems of software synthesis in the design of hardware-software mixed systems. This paper presents a methodology for speeding up systems through latency tolerance which is obtained by decomposition of tasks and generation of an efficient scheduler. The task decomposition process focuses on the dependency analysis of system i/o operations. Scheduling of the decomposed tasks is performed in a mixed static and dynamic fashion. Experimental results show the significance of our approach.
{"title":"Software synthesis through task decomposition by dependency analysis","authors":"Youngsoo Shin, Kiyoung Choi","doi":"10.1109/ICCAD.1996.569170","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569170","url":null,"abstract":"Latency tolerance is one of main problems of software synthesis in the design of hardware-software mixed systems. This paper presents a methodology for speeding up systems through latency tolerance which is obtained by decomposition of tasks and generation of an efficient scheduler. The task decomposition process focuses on the dependency analysis of system i/o operations. Scheduling of the decomposed tasks is performed in a mixed static and dynamic fashion. Experimental results show the significance of our approach.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131328988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.568941
I. Hartanto, V. Boppana, W. Fuchs
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (hip-hops) that are either difficult to set or unsettable. This is achieved by performing test generation on certain transformed circuits to identify state elements that are not settable to specific logic values. Two applications that benefit from this identification are sequential circuit test generation and partial scan design. The knowledge of the state space is shown to be useful in creating early backtracks in deterministic test generation. Partial scan selection is also shown to benefit from the knowledge of the difficult-to-set hip-hops. Experiments on the ISCAS89 circuits are presented to show the reduction in time for test generation and the improvements in the testability of the resulting partial scan circuits.
{"title":"Identification of unsettable flip-flops for partial scan and faster ATPG","authors":"I. Hartanto, V. Boppana, W. Fuchs","doi":"10.1109/ICCAD.1996.568941","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.568941","url":null,"abstract":"State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (hip-hops) that are either difficult to set or unsettable. This is achieved by performing test generation on certain transformed circuits to identify state elements that are not settable to specific logic values. Two applications that benefit from this identification are sequential circuit test generation and partial scan design. The knowledge of the state space is shown to be useful in creating early backtracks in deterministic test generation. Partial scan selection is also shown to benefit from the knowledge of the difficult-to-set hip-hops. Experiments on the ISCAS89 circuits are presented to show the reduction in time for test generation and the improvements in the testability of the resulting partial scan circuits.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134614367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569900
M. Sivaraman, A. Strojwas
In this paper, we propose a new and realistic definition of delay fault coverage, based on the percentage of fabricated faulty chips which can be detected as faulty by a given test set. This metric takes into account the probability distribution of delay fault sizes caused by fabrication process effects, as opposed to previously defined metrics which have been based primarily on the percentage of faults tested. In addition to proposing a realistic delay fault coverage metric, we also present a computationally viable scheme for using this metric to estimate the coverage of any given test set for a class of path delay faults caused by distributed fabrication process variations. We use the results for the ISCAS'89 benchmark circuits to demonstrate wide discrepancies between distributed path delay fault coverage estimates for robust test sets obtained using our realistic definition, and the ones obtained by using the traditional notion of coverage as the percentage of paths tested.
{"title":"Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults","authors":"M. Sivaraman, A. Strojwas","doi":"10.1109/ICCAD.1996.569900","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569900","url":null,"abstract":"In this paper, we propose a new and realistic definition of delay fault coverage, based on the percentage of fabricated faulty chips which can be detected as faulty by a given test set. This metric takes into account the probability distribution of delay fault sizes caused by fabrication process effects, as opposed to previously defined metrics which have been based primarily on the percentage of faults tested. In addition to proposing a realistic delay fault coverage metric, we also present a computationally viable scheme for using this metric to estimate the coverage of any given test set for a class of path delay faults caused by distributed fabrication process variations. We use the results for the ISCAS'89 benchmark circuits to demonstrate wide discrepancies between distributed path delay fault coverage estimates for robust test sets obtained using our realistic definition, and the ones obtained by using the traditional notion of coverage as the percentage of paths tested.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114549919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.571329
V. Singhal, S. Malik, R. Brayton
Retiming is often used to optimize synchronous sequential circuits for area or delay or both. If the latches that are retimed have a hardware reset value, the initial state of the circuit must also be retimed, i.e. an initial state must be derived for the retimed circuit. Previously, it has been suggested that this can be avoided if the hardware reset signals are represented explicitly. However, it was thought that this adds unnecessary area and restricts the space of possible retimings. We demonstrate that this is not the case. In addition, we show that this methodology does not require the restriction that all reset signals be asserted at the beginning of circuit operation-a restriction that was imposed by existing algorithms for determining the retimed initial state. Finally we show how our explicit reset (ER) framework enables us to retime when some latches may be driven by different hardware resets, and some others may not have any hardware resets. We also consider the case where the resets are asynchronous. We expect these solutions to the "retimed initial state" problem to help increase the practical applicability of retiming.
{"title":"The case for retiming with explicit reset circuitry","authors":"V. Singhal, S. Malik, R. Brayton","doi":"10.1109/ICCAD.1996.571329","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.571329","url":null,"abstract":"Retiming is often used to optimize synchronous sequential circuits for area or delay or both. If the latches that are retimed have a hardware reset value, the initial state of the circuit must also be retimed, i.e. an initial state must be derived for the retimed circuit. Previously, it has been suggested that this can be avoided if the hardware reset signals are represented explicitly. However, it was thought that this adds unnecessary area and restricts the space of possible retimings. We demonstrate that this is not the case. In addition, we show that this methodology does not require the restriction that all reset signals be asserted at the beginning of circuit operation-a restriction that was imposed by existing algorithms for determining the retimed initial state. Finally we show how our explicit reset (ER) framework enables us to retime when some latches may be driven by different hardware resets, and some others may not have any hardware resets. We also consider the case where the resets are asynchronous. We expect these solutions to the \"retimed initial state\" problem to help increase the practical applicability of retiming.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127721869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-10DOI: 10.1109/ICCAD.1996.569587
E. Charbon, Paolo Miliozzi, E. Malavasi, A. Sangiovanni-Vincentelli
In a constraint-driven layout synthesis environment, parasitic constraints are generated and implemented in each phase of the design process to meet a given set of performance specifications. The success of the synthesis phase depends in great part on the effectiveness and the generality of the constraint generation process. None of the existing approaches to the constraint generation problem however are suitable for a number of parasitic effects in active and passive devices due to non-deterministic process variations. To address this problem a novel methodology is proposed based on the separation of all variables associated with non-deterministic parasitics, thus allowing the translation of the problem into an equivalent one in which conventional constrained optimization techniques can be used. The requirements, of the method are a well-defined set of statistical properties for all parasitics and a reasonable degree of linearity of the performance measures relevant to design.
{"title":"Generalized constraint generation in the presence of non-deterministic parasitics","authors":"E. Charbon, Paolo Miliozzi, E. Malavasi, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCAD.1996.569587","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569587","url":null,"abstract":"In a constraint-driven layout synthesis environment, parasitic constraints are generated and implemented in each phase of the design process to meet a given set of performance specifications. The success of the synthesis phase depends in great part on the effectiveness and the generality of the constraint generation process. None of the existing approaches to the constraint generation problem however are suitable for a number of parasitic effects in active and passive devices due to non-deterministic process variations. To address this problem a novel methodology is proposed based on the separation of all variables associated with non-deterministic parasitics, thus allowing the translation of the problem into an equivalent one in which conventional constrained optimization techniques can be used. The requirements, of the method are a well-defined set of statistical properties for all parasitics and a reasonable degree of linearity of the performance measures relevant to design.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"17 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132609653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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