Pub Date : 1997-02-04DOI: 10.1109/MCMC.1997.569341
Y. Low, R. Frye
We have designed multichip modules using three alternative technologies for a variety of applications, and have used the results to study the impact of miniaturization and passive component integration on module size, distribution of net length and estimated cost. We have chosen representative applications that include: a digital application with dense interconnections, a mixed-signal application for low-end portable electronics and an analog application requiring a large number of passive components. We compare conventional, laminate-based MCM technology with advanced thin-film-on-laminate technology and silicon-based thin-film MCM technology. We find that the advanced highly miniaturized technologies result not only in higher packaging density and shorter average net length, but in lower estimated module cost as well. Passive component integration can also lower module cost especially in mixed-signal and analog applications.
{"title":"The impact of miniaturization and passive component integration in emerging MCM applications","authors":"Y. Low, R. Frye","doi":"10.1109/MCMC.1997.569341","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569341","url":null,"abstract":"We have designed multichip modules using three alternative technologies for a variety of applications, and have used the results to study the impact of miniaturization and passive component integration on module size, distribution of net length and estimated cost. We have chosen representative applications that include: a digital application with dense interconnections, a mixed-signal application for low-end portable electronics and an analog application requiring a large number of passive components. We compare conventional, laminate-based MCM technology with advanced thin-film-on-laminate technology and silicon-based thin-film MCM technology. We find that the advanced highly miniaturized technologies result not only in higher packaging density and shorter average net length, but in lower estimated module cost as well. Passive component integration can also lower module cost especially in mixed-signal and analog applications.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121833290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-02-04DOI: 10.1109/MCMC.1997.569358
W. Hansford, J. Peltier, P. Franzon, S. Lipa, J. Schaeffer
The MIDAS service at USC/ISI interfaces system designers to domestic Multichip Module (MCM) foundries. Users share tooling and manufacturing costs by merging multiple designs onto a fabrication run and through the use of standard module sizes and packages. MIDAS is developing flip chip bumping and assembly services for MCM-D users. Demonstration designs have been developed by North Carolina State University, including a 7-chip noise evaluator for verifying SSN prediction models and a 3-chip Data Encryption Standard (DES) processor which uses the MCM substrate to distribute global power, ground, and clock that is normally done on-chip.
{"title":"Prototype development of flip chip MCMs","authors":"W. Hansford, J. Peltier, P. Franzon, S. Lipa, J. Schaeffer","doi":"10.1109/MCMC.1997.569358","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569358","url":null,"abstract":"The MIDAS service at USC/ISI interfaces system designers to domestic Multichip Module (MCM) foundries. Users share tooling and manufacturing costs by merging multiple designs onto a fabrication run and through the use of standard module sizes and packages. MIDAS is developing flip chip bumping and assembly services for MCM-D users. Demonstration designs have been developed by North Carolina State University, including a 7-chip noise evaluator for verifying SSN prediction models and a 3-chip Data Encryption Standard (DES) processor which uses the MCM substrate to distribute global power, ground, and clock that is normally done on-chip.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133710899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-02-04DOI: 10.1109/MCMC.1997.569337
R. Lomax, R.B. Brown, M. Nanua, T. D. Strong
This paper discusses an approach using area interconnect to achieve high performance for an experimental multichip microprocessor. The described method is being used in the PUMA project at the University of Michigan to design a processor that has a clock speed goal of 1 GHz. The approach relies on the coordinated placement of functional blocks on chips, and the resulting chips on the MCM. The use of area array pads to provide high bandwidth interconnections between the chips, and low inductance power connection to the MCM is also essential. Three stages of MCM development for the project are described.
{"title":"Area I/O flip-chip packaging to minimize interconnect length","authors":"R. Lomax, R.B. Brown, M. Nanua, T. D. Strong","doi":"10.1109/MCMC.1997.569337","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569337","url":null,"abstract":"This paper discusses an approach using area interconnect to achieve high performance for an experimental multichip microprocessor. The described method is being used in the PUMA project at the University of Michigan to design a processor that has a clock speed goal of 1 GHz. The approach relies on the coordinated placement of functional blocks on chips, and the resulting chips on the MCM. The use of area array pads to provide high bandwidth interconnections between the chips, and low inductance power connection to the MCM is also essential. Three stages of MCM development for the project are described.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114202107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-02-04DOI: 10.1109/MCMC.1997.569340
R. Thompson, M. Degerstrom, W. Walters, M.E. Vickberg, P. Riemer, Eric L. H. Amundsen, B. Gilbert
This paper will discuss multichip module (MCM) technology as it is applied to a prototype high performance direct digitizing channelized radar receiver system under development for the Navy's E2-C Airborne Early Warning Aircraft, which encompasses both analog signals at UHF frequencies and multi-gigahertz digital signals. Critical issues which arise in the design of such a system will be discussed, including thermal management, transmission line, voltage standing wave ratio, and simultaneous switching noise analyses. This paper will also describe the various simulation and analysis software tools employed in the development of the MCM containing the analog-to-digital converter (A/D converter) and demultiplexer for this system, and the roles of these tools in providing insight into the design of the MCM.
{"title":"An 8-bit 2.5 gigasample A/D converter multichip module for all-digital radar receiver for AN/APS 145 radar on Navy E2-C Airborne Early Warning Aircraft","authors":"R. Thompson, M. Degerstrom, W. Walters, M.E. Vickberg, P. Riemer, Eric L. H. Amundsen, B. Gilbert","doi":"10.1109/MCMC.1997.569340","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569340","url":null,"abstract":"This paper will discuss multichip module (MCM) technology as it is applied to a prototype high performance direct digitizing channelized radar receiver system under development for the Navy's E2-C Airborne Early Warning Aircraft, which encompasses both analog signals at UHF frequencies and multi-gigahertz digital signals. Critical issues which arise in the design of such a system will be discussed, including thermal management, transmission line, voltage standing wave ratio, and simultaneous switching noise analyses. This paper will also describe the various simulation and analysis software tools employed in the development of the MCM containing the analog-to-digital converter (A/D converter) and demultiplexer for this system, and the roles of these tools in providing insight into the design of the MCM.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124813102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-02-04DOI: 10.1109/MCMC.1997.569361
H. Werkmann, B. Hofflinger
A cost model for silicon-carrier based MCM systems is presented. The purpose of this cost model is the comparison of test methods for silicon carriers regarding passive substrates and active substrates with integrated test capabilities. Modular models of the different system fabrication steps are developed and combined to a model covering the whole fabrication process. Emphasis is put on the cost modules for substrate fabrication comparing active to passive silicon substrates and on the substrate and system test comparing different test approaches for silicon substrates using test circuitry integrated into an active silicon substrate and the test of passive silicon carriers with conventional test methods.
{"title":"Comparative cost analysis for smart-substrate MCM system","authors":"H. Werkmann, B. Hofflinger","doi":"10.1109/MCMC.1997.569361","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569361","url":null,"abstract":"A cost model for silicon-carrier based MCM systems is presented. The purpose of this cost model is the comparison of test methods for silicon carriers regarding passive substrates and active substrates with integrated test capabilities. Modular models of the different system fabrication steps are developed and combined to a model covering the whole fabrication process. Emphasis is put on the cost modules for substrate fabrication comparing active to passive silicon substrates and on the substrate and system test comparing different test approaches for silicon substrates using test circuitry integrated into an active silicon substrate and the test of passive silicon carriers with conventional test methods.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122888383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-02-04DOI: 10.1109/MCMC.1997.569352
A. Kahng, K. Masuko, S. Muddu
Elmore delay has been extensively used for interconnect delay estimation because its simplicity of evaluation makes it appropriate for layout design. However, since Elmore delay does not take into account the effect of inductance, the discrepancy between actual delay and Elmore delay becomes significant for long RLC transmission lines, such as for MCM and PCB interconnects. We describe a simple two-pole based analytic delay model that estimates arbitrary threshold delays for RLC lines when the response is nonmonotone; our model is far more accurate than the Elmore model. We also describe an application of our model for controlling response undershoot/overshoot and for the reduction of interconnect delay through constraints on the moments.
{"title":"Delay models for MCM interconnects when response is nonmonotone","authors":"A. Kahng, K. Masuko, S. Muddu","doi":"10.1109/MCMC.1997.569352","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569352","url":null,"abstract":"Elmore delay has been extensively used for interconnect delay estimation because its simplicity of evaluation makes it appropriate for layout design. However, since Elmore delay does not take into account the effect of inductance, the discrepancy between actual delay and Elmore delay becomes significant for long RLC transmission lines, such as for MCM and PCB interconnects. We describe a simple two-pole based analytic delay model that estimates arbitrary threshold delays for RLC lines when the response is nonmonotone; our model is far more accurate than the Elmore model. We also describe an application of our model for controlling response undershoot/overshoot and for the reduction of interconnect delay through constraints on the moments.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130474633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-02-04DOI: 10.1109/MCMC.1997.569362
B. Kaminska, G. Fortin, E. Sokolowska, C. Roy
This paper presents an approach to switched electrical and optical transmissions using a pseudo-optical switching system. Packaging alternatives for the switching matrix are explored for OC-3 and OC-12 norms, with the aim of achieving a low system noise. The characteristics of a prototype pseudo-optical switch composed of transimpedance and differential amplifiers, multiplexers and GaAs laser drivers are also presented.
{"title":"Switched optical transmission: exploration of trade-offs between packaging options","authors":"B. Kaminska, G. Fortin, E. Sokolowska, C. Roy","doi":"10.1109/MCMC.1997.569362","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569362","url":null,"abstract":"This paper presents an approach to switched electrical and optical transmissions using a pseudo-optical switching system. Packaging alternatives for the switching matrix are explored for OC-3 and OC-12 norms, with the aim of achieving a low system noise. The characteristics of a prototype pseudo-optical switch composed of transimpedance and differential amplifiers, multiplexers and GaAs laser drivers are also presented.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116701014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：