Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9371993
W. Yang, B. Y. Chen, C. Chuang, E. Hsieh, K. S. Li, S. Chung
For the first time, we use a gate-switching resistance memory to implement the TRNG (True random number generator). First, a resistance memory was built on a FinFET platform, named RG-FinFET(resistive-gate) RRAM which was simply an MIM(metal-insulator-metal) integrated on top of the FinFET gate. It performed as a novolatile memory (NVM) which used resistance switching to distinguish 0 and 1 states through the drain current of the FinFET. The experimental results show that RG-FinFET exhibits high SET speed of 50ns at 3.4V/RESET speed of 10ns at 2.4V, read time as small as 16ns at 1.1V. Furthermore, excellent 107 cycles endurance and data-retention under 125°C for over one month can be achieved. The array-level performance is also analyzed, showing well disturbance-immune during SET, RESET and read. Secondly, a TRNG was developed based on the drain current variation of RG-FinFET. In terms of the security, this TRNG exhibits ideal un-biased normal distribution of hamming distance, and narrow distribution of hamming weight. Moreover, we introduced the concept of XNOR-enhanced operation to TRNG at high temperature to enhance its uniformity. In NIST test, this TRNG passed all items. More importantly, this work is ready for an embedded FinFET technology to develop TRNG with full logic CMOS compatibility.
{"title":"Novel Concept of Hardware Security in Using Gate-switching FinFET Nonvolatile Memory to Implement True-Random-Number Generator","authors":"W. Yang, B. Y. Chen, C. Chuang, E. Hsieh, K. S. Li, S. Chung","doi":"10.1109/IEDM13553.2020.9371993","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371993","url":null,"abstract":"For the first time, we use a gate-switching resistance memory to implement the TRNG (True random number generator). First, a resistance memory was built on a FinFET platform, named RG-FinFET(resistive-gate) RRAM which was simply an MIM(metal-insulator-metal) integrated on top of the FinFET gate. It performed as a novolatile memory (NVM) which used resistance switching to distinguish 0 and 1 states through the drain current of the FinFET. The experimental results show that RG-FinFET exhibits high SET speed of 50ns at 3.4V/RESET speed of 10ns at 2.4V, read time as small as 16ns at 1.1V. Furthermore, excellent 107 cycles endurance and data-retention under 125°C for over one month can be achieved. The array-level performance is also analyzed, showing well disturbance-immune during SET, RESET and read. Secondly, a TRNG was developed based on the drain current variation of RG-FinFET. In terms of the security, this TRNG exhibits ideal un-biased normal distribution of hamming distance, and narrow distribution of hamming weight. Moreover, we introduced the concept of XNOR-enhanced operation to TRNG at high temperature to enhance its uniformity. In NIST test, this TRNG passed all items. More importantly, this work is ready for an embedded FinFET technology to develop TRNG with full logic CMOS compatibility.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122088878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9371953
P. Neudeck, D. Spry, M. Krasowski, L. Chen, N. Prokop, L. Greer, C. Chang
This invited paper describes prototype SiC JFET integrated circuit (IC) and packaging technology that has produced arguably the most harsh-environment durable electronics ever demonstrated. Prototype medium-scale integration (MSI) ICs fabricated by NASA Glenn Research Center have successfully operated for over 1 year in 500 °C air-ambient, over 60 days in 460 °C and 9.3 MPa pressure caustic Venus surface environment test chamber, from -190 °C to +812 °C, and radiation exposure through 7 MRad(Si) total ionizing dose and 86 MeV-cm2/mg heavy ion strikes. Recent on-going work focused on upscaling this “go anywhere” IC capability from MSI to large-scale integration (LSI) prototype via benchmark memory ICs is described.
{"title":"Progressing -190 °C to +500 °C Durable SiC JFET ICs From MSI to LSI","authors":"P. Neudeck, D. Spry, M. Krasowski, L. Chen, N. Prokop, L. Greer, C. Chang","doi":"10.1109/IEDM13553.2020.9371953","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371953","url":null,"abstract":"This invited paper describes prototype SiC JFET integrated circuit (IC) and packaging technology that has produced arguably the most harsh-environment durable electronics ever demonstrated. Prototype medium-scale integration (MSI) ICs fabricated by NASA Glenn Research Center have successfully operated for over 1 year in 500 °C air-ambient, over 60 days in 460 °C and 9.3 MPa pressure caustic Venus surface environment test chamber, from -190 °C to +812 °C, and radiation exposure through 7 MRad(Si) total ionizing dose and 86 MeV-cm2/mg heavy ion strikes. Recent on-going work focused on upscaling this “go anywhere” IC capability from MSI to large-scale integration (LSI) prototype via benchmark memory ICs is described.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129908052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372098
Zheng Wang, M. M. Islam, Panni Wang, Shan Deng, Shimeng Yu, A. Khan, K. Ni
Doped HfO2 based ferroelectric FET (FeFET) exhibits a greatly improved retention performance compared with its perovskite counterpart due to its large coercive field, which prevents domain flip during retention. In this work, however, through extensive temperature dependent experimental characterization and modeling, we are demonstrating that: 1) with FeFET geometry scaling, the polarization states are no longer stable, but exhibit multi-step degradation and cause reduced sense margin in distinguishable adjacent levels or even eventual memory window collapse; 2) the instability is caused by the temperature activated accumulation of switching probability under depolarization field stress, which could cause domain switching within the retention time at operating temperatures.
{"title":"Depolarization Field Induced Instability of Polarization States in HfO2 Based Ferroelectric FET","authors":"Zheng Wang, M. M. Islam, Panni Wang, Shan Deng, Shimeng Yu, A. Khan, K. Ni","doi":"10.1109/IEDM13553.2020.9372098","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372098","url":null,"abstract":"Doped HfO2 based ferroelectric FET (FeFET) exhibits a greatly improved retention performance compared with its perovskite counterpart due to its large coercive field, which prevents domain flip during retention. In this work, however, through extensive temperature dependent experimental characterization and modeling, we are demonstrating that: 1) with FeFET geometry scaling, the polarization states are no longer stable, but exhibit multi-step degradation and cause reduced sense margin in distinguishable adjacent levels or even eventual memory window collapse; 2) the instability is caused by the temperature activated accumulation of switching probability under depolarization field stress, which could cause domain switching within the retention time at operating temperatures.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128437110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9371974
S. Dutta, H. Ye, W. Chakraborty, Y. Luo, M. Jose, B. Grisafe, A. Khanna, I. Lightcap, S. Shinde, S. Yu, S. Datta
We demonstrate, for the first time, monolithic 3D (M3D) integration of back-end-of-line (BEOL) compatible Hf0.5Zr0.5O2 (HZO) ferroelectric FET (FeFET) with front-end-of-line (FEOL) high-k/metal gate (HKMG) Si-NMOS. We use low thermal budget (<4000C) processing to integrate HZO with 1% Tungsten (W)-doped amorphous In2O3 (IWO) semiconducting oxide channel and demonstrate high remnant polarization charge density 2PR, of 40μC/cm2 reliable with switching characteristics. We report (a) read memory window of 0.45V in ultra-scaled 20nm channel length IWO FeFET, (b) write speed of 100ns, and (c) write endurance >108 cycle. We further demonstrate a 2bit/cell synaptic weight cell with well separated conductance states. System-level analysis of compute-in-memory (CIM) accelerators for performing inference on CIFAR-10 image dataset using VGG-8 model shows that 22nm BEOL FeFET achieves 3× higher energy-efficiency than 7nm SRAM while occupying a smaller memory array area due to area folding enabled by M3D architecture.
{"title":"Monolithic 3D Integration of High Endurance Multi-Bit Ferroelectric FET for Accelerating Compute-In-Memory","authors":"S. Dutta, H. Ye, W. Chakraborty, Y. Luo, M. Jose, B. Grisafe, A. Khanna, I. Lightcap, S. Shinde, S. Yu, S. Datta","doi":"10.1109/IEDM13553.2020.9371974","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371974","url":null,"abstract":"We demonstrate, for the first time, monolithic 3D (M3D) integration of back-end-of-line (BEOL) compatible Hf0.5Zr0.5O2 (HZO) ferroelectric FET (FeFET) with front-end-of-line (FEOL) high-k/metal gate (HKMG) Si-NMOS. We use low thermal budget (<4000C) processing to integrate HZO with 1% Tungsten (W)-doped amorphous In2O3 (IWO) semiconducting oxide channel and demonstrate high remnant polarization charge density 2PR, of 40μC/cm2 reliable with switching characteristics. We report (a) read memory window of 0.45V in ultra-scaled 20nm channel length IWO FeFET, (b) write speed of 100ns, and (c) write endurance >108 cycle. We further demonstrate a 2bit/cell synaptic weight cell with well separated conductance states. System-level analysis of compute-in-memory (CIM) accelerators for performing inference on CIFAR-10 image dataset using VGG-8 model shows that 22nm BEOL FeFET achieves 3× higher energy-efficiency than 7nm SRAM while occupying a smaller memory array area due to area folding enabled by M3D architecture.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129584645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/iedm13553.2020.9372008
{"title":"Conference highlights and awards","authors":"","doi":"10.1109/iedm13553.2020.9372008","DOIUrl":"https://doi.org/10.1109/iedm13553.2020.9372008","url":null,"abstract":"","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127132392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9371934
F. Arnaud, P. Ferreira, F. Piazza, A. Gandolfo, P. Zuliani, P. Mattavelli, E. Gomiero, G. Samanni, J. Jasse, C. Jahan, J. Reynard, R. Berthelon, O. Weber, A. Villaret, B. Dumont, J. Grenier, R. Ranica, C. Gallon, C. Boccaccio, A. Souhaite, L. Desvoivres, D. Ristoiu, L. Favennec, V. Caubet, S. DelMedico, N. Cherault, R. Beneyton, S. Chouteau, P. Sassoulas, L. Clément, P. Boivin, D. Turgis, F. Disegni, J. Ogier, X. Federspiel, O. Kermarrec, M. Molgg, A. Viscuso, R. Annunziata, A. Maurelli, P. Cappelletti, E. Ciantar
in this paper we present an enhancement of our 28nm FDSOI-PCM solution using Bipolar Junction Transistor (BJT) selector co-integrated with triple gate oxide devices scheme (logic/1,8V/5V) for advanced automotive microcontroller designs. Leveraging FDSOI substrate, innovative Super-STI (SSTI) scheme has been developed enabling 0,019um2 PCM cell. It is the densest eNVM cell reported so far, based on our knowledge. Ultimate analog performance targets for automotive have been successfully demonstrated without compromising reliability for 5V transistor thanks to a novel gate stack & spacers architecture. Automotive grade-0 reliability criteria have been achieved on 16MB PCM array, including 3x aggressive runs of soldering reflow thermal stress (265°C/210s). Finally, wide reading window has been shown even after 250K writing operation at 165°C.
在本文中，我们提出了我们的28nm FDSOI-PCM解决方案的增强，使用双极结晶体管(BJT)选择器与三栅氧化物器件方案(逻辑/1,8 v /5V)共集成，用于先进的汽车微控制器设计。利用FDSOI衬底，开发了创新的Super-STI (SSTI)方案，可实现0,019um2 PCM电池。据我们所知，这是迄今为止报道的密度最大的eNVM细胞。由于采用了新颖的栅极堆栈和间隔器架构，汽车的终极模拟性能目标已成功演示，而不会影响5V晶体管的可靠性。在16MB PCM阵列上实现了汽车0级可靠性标准，包括3倍的焊接回流热应力(265°C/210s)。最后，在165°C下，即使在250K的写入操作后，也显示出宽的读取窗口。
{"title":"High Density Embedded PCM Cell in 28nm FDSOI Technology for Automotive Micro-Controller Applications","authors":"F. Arnaud, P. Ferreira, F. Piazza, A. Gandolfo, P. Zuliani, P. Mattavelli, E. Gomiero, G. Samanni, J. Jasse, C. Jahan, J. Reynard, R. Berthelon, O. Weber, A. Villaret, B. Dumont, J. Grenier, R. Ranica, C. Gallon, C. Boccaccio, A. Souhaite, L. Desvoivres, D. Ristoiu, L. Favennec, V. Caubet, S. DelMedico, N. Cherault, R. Beneyton, S. Chouteau, P. Sassoulas, L. Clément, P. Boivin, D. Turgis, F. Disegni, J. Ogier, X. Federspiel, O. Kermarrec, M. Molgg, A. Viscuso, R. Annunziata, A. Maurelli, P. Cappelletti, E. Ciantar","doi":"10.1109/IEDM13553.2020.9371934","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371934","url":null,"abstract":"in this paper we present an enhancement of our 28nm FDSOI-PCM solution using Bipolar Junction Transistor (BJT) selector co-integrated with triple gate oxide devices scheme (logic/1,8V/5V) for advanced automotive microcontroller designs. Leveraging FDSOI substrate, innovative Super-STI (SSTI) scheme has been developed enabling 0,019um2 PCM cell. It is the densest eNVM cell reported so far, based on our knowledge. Ultimate analog performance targets for automotive have been successfully demonstrated without compromising reliability for 5V transistor thanks to a novel gate stack & spacers architecture. Automotive grade-0 reliability criteria have been achieved on 16MB PCM array, including 3x aggressive runs of soldering reflow thermal stress (265°C/210s). Finally, wide reading window has been shown even after 250K writing operation at 165°C.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130581976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9371896
Qifeng Cai, Shuo Liu, Minzhi Du, Lei Xu, Chunyan Zhao, Congwei Tan, Teng Tu, Kun Zhang, H. Peng, Xing Zhang, Ming Li, M. He, Ru Huang
In this work, we reported high-sensitivity thermal- bolometric integrated transistor sensors based on the layered Bi2O2Se nanosheets for the first time, wherein the temperature- promoted ionization of selenium vacancies and the ultrahigh in-plane electron mobility were demonstrated to yield a recordhigh temperature resolution of 1.5 mK. And the integrated sensors simultaneously detected the thermal, photoconductive, and bolometric stimuli with outstanding performances including the temperature sensitivity of 4.6 %K-1, the bolometric coefficient of 41.8 μA/K, the bolometric response of >3300 A/W, and the working range of 30-200 °C. Furthermore, the stochastic resonance decoupling model was proposed to extract the coupled signals by amplifying signals through the coherent energy transferring from the imbedded noises.
{"title":"Sub-10mK-Resolution Thermal-Bolometric Integrated FET-Type Sensors Based on Layered Bi2O2Se Semiconductor Nanosheets","authors":"Qifeng Cai, Shuo Liu, Minzhi Du, Lei Xu, Chunyan Zhao, Congwei Tan, Teng Tu, Kun Zhang, H. Peng, Xing Zhang, Ming Li, M. He, Ru Huang","doi":"10.1109/IEDM13553.2020.9371896","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371896","url":null,"abstract":"In this work, we reported high-sensitivity thermal- bolometric integrated transistor sensors based on the layered Bi2O2Se nanosheets for the first time, wherein the temperature- promoted ionization of selenium vacancies and the ultrahigh in-plane electron mobility were demonstrated to yield a recordhigh temperature resolution of 1.5 mK. And the integrated sensors simultaneously detected the thermal, photoconductive, and bolometric stimuli with outstanding performances including the temperature sensitivity of 4.6 %K-1, the bolometric coefficient of 41.8 μA/K, the bolometric response of >3300 A/W, and the working range of 30-200 °C. Furthermore, the stochastic resonance decoupling model was proposed to extract the coupled signals by amplifying signals through the coherent energy transferring from the imbedded noises.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132312469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372076
H. Bae, S. Nam, T. Moon, Yunseong Lee, Sanghyun Jo, Duk-Hyun Choe, Sangwook Kim, Kwang-Hee Lee, J. Heo
In this work, we report sub-ns polarization switching in highly scaled 25 nm ferroelectric (FE) FinFET with Hf0.5Zr0.5O2 (HZO) ferroelectric (FE)/SiO2 dielectric (DE) gate stack for high performance CPU application for the first time. Observed limited endurance was attributed to the increase of trap density in the stack, which was quantitatively analyzed upon program/erase cycles by various methods including newly adopted low-frequency noise (LFN) characteristics for resolving spatial and energetic distribution of traps. In particular, we identified three different types of traps at FE/DE interface (Dit_2) and SiO2/Si channel interface (Dit_1) as well as in the bulk oxide (Not) of the HZO/SiO2 gate stack of FE FinFETs. In addition, with the developed trap analysis, we investigated radiation-induced degradation of HZO/SiO2 gate stack for application under harsh environments. Highly scaled and high performance FE FinFETs with enhanced endurance would provide a viable solution for future platform of low-power computing.
{"title":"Sub-ns Polarization Switching in 25nm FE FinFET toward Post CPU and Spatial-Energetic Mapping of Traps for Enhanced Endurance","authors":"H. Bae, S. Nam, T. Moon, Yunseong Lee, Sanghyun Jo, Duk-Hyun Choe, Sangwook Kim, Kwang-Hee Lee, J. Heo","doi":"10.1109/IEDM13553.2020.9372076","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372076","url":null,"abstract":"In this work, we report sub-ns polarization switching in highly scaled 25 nm ferroelectric (FE) FinFET with Hf0.5Zr0.5O2 (HZO) ferroelectric (FE)/SiO2 dielectric (DE) gate stack for high performance CPU application for the first time. Observed limited endurance was attributed to the increase of trap density in the stack, which was quantitatively analyzed upon program/erase cycles by various methods including newly adopted low-frequency noise (LFN) characteristics for resolving spatial and energetic distribution of traps. In particular, we identified three different types of traps at FE/DE interface (Dit_2) and SiO2/Si channel interface (Dit_1) as well as in the bulk oxide (Not) of the HZO/SiO2 gate stack of FE FinFETs. In addition, with the developed trap analysis, we investigated radiation-induced degradation of HZO/SiO2 gate stack for application under harsh environments. Highly scaled and high performance FE FinFETs with enhanced endurance would provide a viable solution for future platform of low-power computing.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126516810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We demonstrate a 2-levels-stacked multi-bridge-channels (MBC) FET with channel thickness only 0.6nm and 1.2nm which is the thinnest channel record among reported MBC FET. The normalized drive current of a single stacked channel is 13.2μA•μm/μm (VDS=1V) which is comparable to the latest 7-levels-stacked Si MBC FET. What’s more, this ultrathin MBC FET demonstrates a very low leakage current per level (0.92pA•μm/μm, VDS=1V), only 6.5% of the value of the Si MBC FET. We also explore a self-aligned edge-contact process, paving the way toward higher-levels-stacked ultrathin MBC FET.
我们展示了2级堆叠的多桥通道(MBC)场效应管，通道厚度仅为0.6nm和1.2nm，这是目前报道的最薄的MBC场效应管。单个堆叠通道的归一化驱动电流为13.2μA•μm/μm (VDS=1V)，可与最新的7级堆叠Si MBC场效应管相媲美。此外，该超薄MBC FET具有非常低的每级漏电流(0.92pA•μm/μm, VDS=1V)，仅为Si MBC FET的6.5%。我们还探索了一种自对准边接触工艺，为更高水平堆叠超薄MBC场效应管铺平了道路。
{"title":"High Drive and Low Leakage Current MBC FET with Channel Thickness 1.2nm/0.6nm","authors":"Xiaohe Huang, Chunsen Liu, Zhaowu Tang, Senfeng Zeng, Liwei Liu, Xiang Hou, Huawei Chen, Jiayi Li, Yu-Gang Jiang, David-Wei Zhang, P. Zhou","doi":"10.1109/IEDM13553.2020.9371941","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371941","url":null,"abstract":"We demonstrate a 2-levels-stacked multi-bridge-channels (MBC) FET with channel thickness only 0.6nm and 1.2nm which is the thinnest channel record among reported MBC FET. The normalized drive current of a single stacked channel is 13.2μA•μm/μm (VDS=1V) which is comparable to the latest 7-levels-stacked Si MBC FET. What’s more, this ultrathin MBC FET demonstrates a very low leakage current per level (0.92pA•μm/μm, VDS=1V), only 6.5% of the value of the Si MBC FET. We also explore a self-aligned edge-contact process, paving the way toward higher-levels-stacked ultrathin MBC FET.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121422506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372079
R. Kaplar, B. Gunning, A. Allerman, M. Crawford, J. Flicker, A. Armstrong, L. Yates, A. Binder, J. Dickerson, G. Pickrell, P. Sharps, T. Anderson, J. Gallagher, A. Jacobs, A. Koehler, M. Tadjer, K. Hobart, M. Ebrish, M. Porter, R. Martinez, K. Zeng, D. Ji, S. Chowdhury, O. Aktas, J. Cooper
This paper describes the development of vertical GaN PN diodes for high-voltage applications. A centerpiece of this work is the creation of a foundry effort that incorporates epitaxial growth, wafer metrology, device design, processing, and characterization, and reliability evaluation and failure analysis. A parallel effort aims to develop very high voltage (up to 20 kV) GaN PN diodes for use as devices to protect the electric grid against electromagnetic pulses.
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