Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9371942
S. King, J. Plombon, J. Bielefeld, J. Blackwell, S. Vyas, R. Chebiam, C. Naylor, D. Michalak, M. Kobrinsky, F. Gstrein, M. Metz, J. Clarke, R. Thapa, M. Paquette, V. Vemuri, N. Strandwitz, Y. Fan, M. Orlowski
The remarkable advancement of CMOS electronics over the past two decades has been greatly aided by innovations allowing dielectric scaling across both ends of the permittivity spectrum. This paper describes how new dielectric innovations beyond permittivity scaling will allow both the extension of Moore’s law for another decade and usher in an array of new devices and computational paradigms.
{"title":"A Selectively Colorful yet Chilly Perspective on the Highs and Lows of Dielectric Materials for CMOS Nanoelectronics","authors":"S. King, J. Plombon, J. Bielefeld, J. Blackwell, S. Vyas, R. Chebiam, C. Naylor, D. Michalak, M. Kobrinsky, F. Gstrein, M. Metz, J. Clarke, R. Thapa, M. Paquette, V. Vemuri, N. Strandwitz, Y. Fan, M. Orlowski","doi":"10.1109/IEDM13553.2020.9371942","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371942","url":null,"abstract":"The remarkable advancement of CMOS electronics over the past two decades has been greatly aided by innovations allowing dielectric scaling across both ends of the permittivity spectrum. This paper describes how new dielectric innovations beyond permittivity scaling will allow both the extension of Moore’s law for another decade and usher in an array of new devices and computational paradigms.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134216431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372040
S. H. Han, J. Lee, H. Shin, J. Lee, K. Suh, K. Nam, B. Kwon, M. Cho, J. Lee, J. Jeong, J. Park, S. C. Oh, S. O. Park, S. Hwang, S. Pyo, H. Jung, Y. Ji, J. Bak, D. S. Kim, W. S. Ham, Y. Kim, K. Lee, Y. J. Song, G. Koh, Y. Hong, G. Jeong
We present the world-first demonstration of 28-nm embedded MRAM (eMRAM) for frame buffer memory, highlighting the smallest macro size (0.08 mm2/Mb) reported to date. Compared to SRAM that is commonly used for frame buffer memory, eMRAM provides 47% area saving. For frame buffer applications, read disturbance and endurance are the most critical reliability considerations. With magnetic tunnel junction process improvements, we have verified sufficient read disturbance margins and met the endurance requirement (> 1E10 cycles) which corresponds to 10-year continuous usage. Compared to flash-type eMRAM, we have achieved 40% switching current reduction with < 50ns read/write speed.
{"title":"28-nm 0.08 mm2/Mb Embedded MRAM for Frame Buffer Memory","authors":"S. H. Han, J. Lee, H. Shin, J. Lee, K. Suh, K. Nam, B. Kwon, M. Cho, J. Lee, J. Jeong, J. Park, S. C. Oh, S. O. Park, S. Hwang, S. Pyo, H. Jung, Y. Ji, J. Bak, D. S. Kim, W. S. Ham, Y. Kim, K. Lee, Y. J. Song, G. Koh, Y. Hong, G. Jeong","doi":"10.1109/IEDM13553.2020.9372040","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372040","url":null,"abstract":"We present the world-first demonstration of 28-nm embedded MRAM (eMRAM) for frame buffer memory, highlighting the smallest macro size (0.08 mm2/Mb) reported to date. Compared to SRAM that is commonly used for frame buffer memory, eMRAM provides 47% area saving. For frame buffer applications, read disturbance and endurance are the most critical reliability considerations. With magnetic tunnel junction process improvements, we have verified sufficient read disturbance margins and met the endurance requirement (> 1E10 cycles) which corresponds to 10-year continuous usage. Compared to flash-type eMRAM, we have achieved 40% switching current reduction with < 50ns read/write speed.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131532145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9371948
H. Park, D. Kang, J. Lee, D. Minn, Y. Aoki, K. Kim, S. Lee, D. Lee, S. Kim, J. Kim, W. Lee, C. Kim, S. Park, J. Park, B. Suh, J. Jang, M. Kim, K. Min, S. Jeon, A.-S. Ryu, Y. Kim, J. Lee, J. Son, S.-G. Yang
This paper presents design challenges and solutions for the fifth generation (5G) phased-array transceiver ICs in millimeter-wave (MMW) frequency bands. A 28nm bulk CMOS device technology is selected to integrate multiple RF phased-array elements in a single-chip to achieve a high-level of TX EIRP and RX sensitivity. Several design approaches of gain, POUT, stability, reliability and linearity enhancement techniques are applied to enable CMOS as a key device solution for 5G applications in MMW frequency bands. A 39GHz band 16-channel CMOS RF phased-array transceiver IC is designed and can support 4T/4R MIMO base-station applications including ×64 RF phased-array ICs (total 1,024 phased-array elements). T/RX paths have gain dynamic ranges of >30/40dB for flexibility and scalability. The TX path shows POUT/Ch. of >6.0dBm at EVM of -34dB (800MHz) and PDC/Ch. of 105mW. The RX path performs NF of 4.2dB, EVM of -38dB (100MHz) and PDC/Ch. of 39mW. These state-of-the-art results lead to TX EIRP of >55dBm and RX sensitivity of <-113dBm/100MHz in the 5G NR base-station system.
{"title":"Millimeter-Wave Band CMOS RF Phased-Array Transceiver IC Designs for 5G Applications","authors":"H. Park, D. Kang, J. Lee, D. Minn, Y. Aoki, K. Kim, S. Lee, D. Lee, S. Kim, J. Kim, W. Lee, C. Kim, S. Park, J. Park, B. Suh, J. Jang, M. Kim, K. Min, S. Jeon, A.-S. Ryu, Y. Kim, J. Lee, J. Son, S.-G. Yang","doi":"10.1109/IEDM13553.2020.9371948","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371948","url":null,"abstract":"This paper presents design challenges and solutions for the fifth generation (5G) phased-array transceiver ICs in millimeter-wave (MMW) frequency bands. A 28nm bulk CMOS device technology is selected to integrate multiple RF phased-array elements in a single-chip to achieve a high-level of TX EIRP and RX sensitivity. Several design approaches of gain, POUT, stability, reliability and linearity enhancement techniques are applied to enable CMOS as a key device solution for 5G applications in MMW frequency bands. A 39GHz band 16-channel CMOS RF phased-array transceiver IC is designed and can support 4T/4R MIMO base-station applications including ×64 RF phased-array ICs (total 1,024 phased-array elements). T/RX paths have gain dynamic ranges of >30/40dB for flexibility and scalability. The TX path shows POUT/Ch. of >6.0dBm at EVM of -34dB (800MHz) and PDC/Ch. of 105mW. The RX path performs NF of 4.2dB, EVM of -38dB (100MHz) and PDC/Ch. of 39mW. These state-of-the-art results lead to TX EIRP of >55dBm and RX sensitivity of <-113dBm/100MHz in the 5G NR base-station system.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"35 15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131563294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372020
E. Butaud, S. Ballandras, M. Bousquet, A. Drouin, B. Tavel, I. Huyet, A. Clairet, I. Bertrand, A. Ghorbel, A. Reinhardt
5G standards implementation drive significant challenges at the acoustic filter level and requires innovative solutions. A promising approach relies in Surface Acoustic Waves technology combined with a thin LiTaO3 piezoelectric crystal layer bonded on Silicon substrate – so called POI-substrate, but suffers from volume manufacturing solution. We will report how Smart Cut™ layer transfer technology enables it.
{"title":"Innovative Smart Cut™ Piezo On Insulator (POI) Substrates for 5G acoustic filters","authors":"E. Butaud, S. Ballandras, M. Bousquet, A. Drouin, B. Tavel, I. Huyet, A. Clairet, I. Bertrand, A. Ghorbel, A. Reinhardt","doi":"10.1109/IEDM13553.2020.9372020","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372020","url":null,"abstract":"5G standards implementation drive significant challenges at the acoustic filter level and requires innovative solutions. A promising approach relies in Surface Acoustic Waves technology combined with a thin LiTaO3 piezoelectric crystal layer bonded on Silicon substrate – so called POI-substrate, but suffers from volume manufacturing solution. We will report how Smart Cut™ layer transfer technology enables it.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131977259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372013
Taekyong Kim, J. D. del Alamo, D. Antoniadis
We have carried out a detailed experimental study of the switching dynamics of HfZrO2 Metal-Ferroelectric-Metal (MFM) and Metal-Ferroelectric-Insulator-Metal (MFIM) structures. In order to extract the intrinsic dynamic response, our experimental methodology has paid close attention to minimizing and calibrating all circuit and sample parasitics. In MFM structures, we have found no evidence of negative capacitance (NC) effect. A new dynamic model based on the multi-domain Preisach model describes well all observed behavior including major and minor charge-voltage loops. Our study also reveals the crucial role that parasitics play in the observed device dynamics and can explain claims of NC effects in MFM structures in the literature. In our MFIM structures, we observe clear NC behavior. We not only confirm the transient quasi-static S-like ferroelectric (FE) charge-field behavior described in the literature, but for the first time, we report a dynamic response that displays a hysteretic behavior in the NC region. A model based on the Landau-Khalatnikov (L-K) equation that incorporates FE dynamics via a phenomenological frictional resistance adequately describes the observed results when that resistance is made dependent on the direction of the voltage drive vs. time. Mitigation of this hysteretic NC behavior will be crucial for the harnessing of NC in practical MOSFETs.
{"title":"Dynamics of HfZrO2 Ferroelectric Structures: Experiments and Models","authors":"Taekyong Kim, J. D. del Alamo, D. Antoniadis","doi":"10.1109/IEDM13553.2020.9372013","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372013","url":null,"abstract":"We have carried out a detailed experimental study of the switching dynamics of HfZrO2 Metal-Ferroelectric-Metal (MFM) and Metal-Ferroelectric-Insulator-Metal (MFIM) structures. In order to extract the intrinsic dynamic response, our experimental methodology has paid close attention to minimizing and calibrating all circuit and sample parasitics. In MFM structures, we have found no evidence of negative capacitance (NC) effect. A new dynamic model based on the multi-domain Preisach model describes well all observed behavior including major and minor charge-voltage loops. Our study also reveals the crucial role that parasitics play in the observed device dynamics and can explain claims of NC effects in MFM structures in the literature. In our MFIM structures, we observe clear NC behavior. We not only confirm the transient quasi-static S-like ferroelectric (FE) charge-field behavior described in the literature, but for the first time, we report a dynamic response that displays a hysteretic behavior in the NC region. A model based on the Landau-Khalatnikov (L-K) equation that incorporates FE dynamics via a phenomenological frictional resistance adequately describes the observed results when that resistance is made dependent on the direction of the voltage drive vs. time. Mitigation of this hysteretic NC behavior will be crucial for the harnessing of NC in practical MOSFETs.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132671365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9371952
C. I, Yingchao Lin, Guizhen Wang
Facing the severe power consumption and energy efficiency challenges in 5G era, a novel DPD solution enabled by deep learning and big data is proposed. This is a flexible system suitable for various wireless network architectures and diverse application scenarios. The architecture, mechanism and deployment strategy along with its advantages are presented. Preliminary validation and analyses are also illustrated for the feasibility.
{"title":"A Deep Learning Enabled Universal DPD System","authors":"C. I, Yingchao Lin, Guizhen Wang","doi":"10.1109/IEDM13553.2020.9371952","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371952","url":null,"abstract":"Facing the severe power consumption and energy efficiency challenges in 5G era, a novel DPD solution enabled by deep learning and big data is proposed. This is a flexible system suitable for various wireless network architectures and diverse application scenarios. The architecture, mechanism and deployment strategy along with its advantages are presented. Preliminary validation and analyses are also illustrated for the feasibility.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116357375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372124
T. Soliman, F. Müller, T. Kirchner, T. Hoffmann, H. Ganem, E. Karimov, T. Ali, M. Lederer, C. Sudarshan, T. Kämpfe, A. Guntoro, N. Wehn
This paper presents an efficient crossbar design and implementation intended for analog compute-in-memory (ACiM) acceleration of artificial neural networks based on ferroelectric FET (FeFET) technology. The novel mixed signal blocks presented in this work reduce the device-to-device variation and are optimized for low area, low power and high throughput. In addition, we illustrate the operation and programmability of the crossbar that adopts bit decomposition techniques for MAC operation. Our crossbar based ACiM accelerator achieves a record peak performance of 13714 TOPS/W.
{"title":"Ultra-Low Power Flexible Precision FeFET Based Analog In-Memory Computing","authors":"T. Soliman, F. Müller, T. Kirchner, T. Hoffmann, H. Ganem, E. Karimov, T. Ali, M. Lederer, C. Sudarshan, T. Kämpfe, A. Guntoro, N. Wehn","doi":"10.1109/IEDM13553.2020.9372124","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372124","url":null,"abstract":"This paper presents an efficient crossbar design and implementation intended for analog compute-in-memory (ACiM) acceleration of artificial neural networks based on ferroelectric FET (FeFET) technology. The novel mixed signal blocks presented in this work reduce the device-to-device variation and are optimized for low area, low power and high throughput. In addition, we illustrate the operation and programmability of the crossbar that adopts bit decomposition techniques for MAC operation. Our crossbar based ACiM accelerator achieves a record peak performance of 13714 TOPS/W.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116581330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9371912
Panni Wang, Xiaochen Peng, W. Chakraborty, A. Khan, S. Datta, Shimeng Yu
Even at deep cryogenic temperature ~20 milli-Kevin, the qubit is fragile, therefore a feedback loop is needed to perform the quantum error correction (QEC). It is highly desirable to operate the QEC at 4K to minimize the thermal heat transfer between the physical qubits and the peripheral control circuitry. In this work, we propose implementing the surface code QEC circuitry with compute-in-memory (CIM) based recurrent neural network accelerator at 4K. To serve this purpose, we develop Cryo-NeuroSim, a device-to-system modeling framework that calibrate the transistor and interconnect parameters with experimental data at cryogenic temperature. Then we benchmark the QEC circuitry with SRAM technologies and optimize its energy-delay-product (EDP) with reengineered threshold voltage and supply voltage.
{"title":"Cryogenic Benchmarks of Embedded Memory Technologies for Recurrent Neural Network based Quantum Error Correction","authors":"Panni Wang, Xiaochen Peng, W. Chakraborty, A. Khan, S. Datta, Shimeng Yu","doi":"10.1109/IEDM13553.2020.9371912","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371912","url":null,"abstract":"Even at deep cryogenic temperature ~20 milli-Kevin, the qubit is fragile, therefore a feedback loop is needed to perform the quantum error correction (QEC). It is highly desirable to operate the QEC at 4K to minimize the thermal heat transfer between the physical qubits and the peripheral control circuitry. In this work, we propose implementing the surface code QEC circuitry with compute-in-memory (CIM) based recurrent neural network accelerator at 4K. To serve this purpose, we develop Cryo-NeuroSim, a device-to-system modeling framework that calibrate the transistor and interconnect parameters with experimental data at cryogenic temperature. Then we benchmark the QEC circuitry with SRAM technologies and optimize its energy-delay-product (EDP) with reengineered threshold voltage and supply voltage.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114878853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9371903
Z. Tokei, V. Vega, G. Murdoch, M. O'Toole, K. Croes, R. Baert, M. V. Veen, C. Adelmann, J. Soulie, J. Boemmels, C. Wilson, S. Park, K. Sankaran, G. Pourtois, J. Sweerts, S. Paolillo, S. Decoster, M. Mao, F. Lazzarino, J. Versluijs, V. Blanco, M. Ercken, E. Kesters, Q. Le, F. Holsteyns, N. Heylen, L. Teugels, K. Devriendt, H. Struyf, P. Morin, N. Jourdan, S. Elshocht, I. Ciofi, A. Gupta, H. Zahedmanesh, K. Vanstreels, M. Na
Interconnect options will be introduced and reviewed targeting tight pitch metal layers at the local levels. Examples include hybrid metallization, semi-damascene interconnects as well as potential new conductor materials.
{"title":"Inflection points in interconnect research and trends for 2nm and beyond in order to solve the RC bottleneck","authors":"Z. Tokei, V. Vega, G. Murdoch, M. O'Toole, K. Croes, R. Baert, M. V. Veen, C. Adelmann, J. Soulie, J. Boemmels, C. Wilson, S. Park, K. Sankaran, G. Pourtois, J. Sweerts, S. Paolillo, S. Decoster, M. Mao, F. Lazzarino, J. Versluijs, V. Blanco, M. Ercken, E. Kesters, Q. Le, F. Holsteyns, N. Heylen, L. Teugels, K. Devriendt, H. Struyf, P. Morin, N. Jourdan, S. Elshocht, I. Ciofi, A. Gupta, H. Zahedmanesh, K. Vanstreels, M. Na","doi":"10.1109/IEDM13553.2020.9371903","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371903","url":null,"abstract":"Interconnect options will be introduced and reviewed targeting tight pitch metal layers at the local levels. Examples include hybrid metallization, semi-damascene interconnects as well as potential new conductor materials.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123236003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372014
A. Valdes-Garcia, P. Pepeljugoski, Ivan Duran, J. Plouchart, M. Yeck, Huijuan Liu
Recent advances in semiconductor and packaging technologies have accelerated the miniaturization of portable sensing devices including visible-domain cameras, IR cameras, and millimeter-wave (mmWave) radars. Simultaneously, image and sensor data processing capabilities based on Systems-on-Chip (SoCs) have evolved as well to the extent toward the goal of implementing learning-based automatic recognition capabilities. This paper discusses the challenges and opportunities associated with the vertical sensors-to-software integration of portable systems capable of performing multi-spectral imaging, where data from different portions of the EM spectrum is captured, processed, and displayed simultaneously. An example hardware implementation, multi-spectral image data, and potential applications are discussed
{"title":"Portable Multi-Spectral Imaging: Devices, Vertical Integration, and Applications","authors":"A. Valdes-Garcia, P. Pepeljugoski, Ivan Duran, J. Plouchart, M. Yeck, Huijuan Liu","doi":"10.1109/IEDM13553.2020.9372014","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372014","url":null,"abstract":"Recent advances in semiconductor and packaging technologies have accelerated the miniaturization of portable sensing devices including visible-domain cameras, IR cameras, and millimeter-wave (mmWave) radars. Simultaneously, image and sensor data processing capabilities based on Systems-on-Chip (SoCs) have evolved as well to the extent toward the goal of implementing learning-based automatic recognition capabilities. This paper discusses the challenges and opportunities associated with the vertical sensors-to-software integration of portable systems capable of performing multi-spectral imaging, where data from different portions of the EM spectrum is captured, processed, and displayed simultaneously. An example hardware implementation, multi-spectral image data, and potential applications are discussed","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123364008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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