Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372059
Sun Il Kim, Junghyun Park, B. Jeong, Duhyun Lee, Jungwoo Kim, C. Shin, Chang-Bum Lee, Tatsuhiro Otsuka, Sangwook Kim, Kiyeon Yang, Yong-Young Park, Jisan Lee, Inoh Hwang, Jaeduck Jang, K. Ha, H. Choo, B. Choi, Sungwoo Hwang
For the first time, we have successfully demonstrated a 3-dimensional (3-D) depth scan using an electrically-tunable active metasurface, which is an array of plasmonic resonators with an active indium-tin-oxide (ITO) layer. Our active device can steer a beam in reflection with a positive side-mode suppression ratio by independently controlling the amplitude and the phase from 0 to 360° using two separate bias controls. These are very promising results for small and high speed 3D depth sensing for mobile and automotive applications.
{"title":"Electrically Reconfigurable Active Metasurface for 3D Distance Ranging","authors":"Sun Il Kim, Junghyun Park, B. Jeong, Duhyun Lee, Jungwoo Kim, C. Shin, Chang-Bum Lee, Tatsuhiro Otsuka, Sangwook Kim, Kiyeon Yang, Yong-Young Park, Jisan Lee, Inoh Hwang, Jaeduck Jang, K. Ha, H. Choo, B. Choi, Sungwoo Hwang","doi":"10.1109/IEDM13553.2020.9372059","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372059","url":null,"abstract":"For the first time, we have successfully demonstrated a 3-dimensional (3-D) depth scan using an electrically-tunable active metasurface, which is an array of plasmonic resonators with an active indium-tin-oxide (ITO) layer. Our active device can steer a beam in reflection with a positive side-mode suppression ratio by independently controlling the amplitude and the phase from 0 to 360° using two separate bias controls. These are very promising results for small and high speed 3D depth sensing for mobile and automotive applications.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115863786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9371903
Z. Tokei, V. Vega, G. Murdoch, M. O'Toole, K. Croes, R. Baert, M. V. Veen, C. Adelmann, J. Soulie, J. Boemmels, C. Wilson, S. Park, K. Sankaran, G. Pourtois, J. Sweerts, S. Paolillo, S. Decoster, M. Mao, F. Lazzarino, J. Versluijs, V. Blanco, M. Ercken, E. Kesters, Q. Le, F. Holsteyns, N. Heylen, L. Teugels, K. Devriendt, H. Struyf, P. Morin, N. Jourdan, S. Elshocht, I. Ciofi, A. Gupta, H. Zahedmanesh, K. Vanstreels, M. Na
Interconnect options will be introduced and reviewed targeting tight pitch metal layers at the local levels. Examples include hybrid metallization, semi-damascene interconnects as well as potential new conductor materials.
{"title":"Inflection points in interconnect research and trends for 2nm and beyond in order to solve the RC bottleneck","authors":"Z. Tokei, V. Vega, G. Murdoch, M. O'Toole, K. Croes, R. Baert, M. V. Veen, C. Adelmann, J. Soulie, J. Boemmels, C. Wilson, S. Park, K. Sankaran, G. Pourtois, J. Sweerts, S. Paolillo, S. Decoster, M. Mao, F. Lazzarino, J. Versluijs, V. Blanco, M. Ercken, E. Kesters, Q. Le, F. Holsteyns, N. Heylen, L. Teugels, K. Devriendt, H. Struyf, P. Morin, N. Jourdan, S. Elshocht, I. Ciofi, A. Gupta, H. Zahedmanesh, K. Vanstreels, M. Na","doi":"10.1109/IEDM13553.2020.9371903","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371903","url":null,"abstract":"Interconnect options will be introduced and reviewed targeting tight pitch metal layers at the local levels. Examples include hybrid metallization, semi-damascene interconnects as well as potential new conductor materials.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123236003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372046
M. Perumkunnil, F. Yasin, S. Rao, S. Salahuddin, D. Milojevic, G. van der Plas, J. Ryckaert, E. Beyne, A. Furnémont, G. Kar
This paper analyzes the most feasible 3D integration and partitioning scheme for STT-MRAM based caches in an advanced Mobile SoC based on the process demonstration of the first ever functional 3D integrated STT devices. We present 3D partitioning schemes from a design -architecture perspective and Power Performance and Area (PPA) analysis is carried out for the 2D and 3D SoC designs with both SRAM and STT-MRAM caches. Our work shows that the PPA benefits from 3D Memory on Logic partitioning are magnified when it can be exploited to accommodate larger caches in general. We also show that STT-MRAM based 3D partitioned caches can exploit this potential increase in capacity to improve performance even more than SRAM. These 3D Wafer-to-Wafer (W2W) integrated STT-MRAM caches can result in up-to 30% performance improvement at 17% power and 15% footprint reduction for our target SoC.
{"title":"System exploration and technology demonstration of 3D Wafer-to-Wafer integrated STT-MRAM based caches for advanced Mobile SoCs","authors":"M. Perumkunnil, F. Yasin, S. Rao, S. Salahuddin, D. Milojevic, G. van der Plas, J. Ryckaert, E. Beyne, A. Furnémont, G. Kar","doi":"10.1109/IEDM13553.2020.9372046","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372046","url":null,"abstract":"This paper analyzes the most feasible 3D integration and partitioning scheme for STT-MRAM based caches in an advanced Mobile SoC based on the process demonstration of the first ever functional 3D integrated STT devices. We present 3D partitioning schemes from a design -architecture perspective and Power Performance and Area (PPA) analysis is carried out for the 2D and 3D SoC designs with both SRAM and STT-MRAM caches. Our work shows that the PPA benefits from 3D Memory on Logic partitioning are magnified when it can be exploited to accommodate larger caches in general. We also show that STT-MRAM based 3D partitioned caches can exploit this potential increase in capacity to improve performance even more than SRAM. These 3D Wafer-to-Wafer (W2W) integrated STT-MRAM caches can result in up-to 30% performance improvement at 17% power and 15% footprint reduction for our target SoC.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123314641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372014
A. Valdes-Garcia, P. Pepeljugoski, Ivan Duran, J. Plouchart, M. Yeck, Huijuan Liu
Recent advances in semiconductor and packaging technologies have accelerated the miniaturization of portable sensing devices including visible-domain cameras, IR cameras, and millimeter-wave (mmWave) radars. Simultaneously, image and sensor data processing capabilities based on Systems-on-Chip (SoCs) have evolved as well to the extent toward the goal of implementing learning-based automatic recognition capabilities. This paper discusses the challenges and opportunities associated with the vertical sensors-to-software integration of portable systems capable of performing multi-spectral imaging, where data from different portions of the EM spectrum is captured, processed, and displayed simultaneously. An example hardware implementation, multi-spectral image data, and potential applications are discussed
{"title":"Portable Multi-Spectral Imaging: Devices, Vertical Integration, and Applications","authors":"A. Valdes-Garcia, P. Pepeljugoski, Ivan Duran, J. Plouchart, M. Yeck, Huijuan Liu","doi":"10.1109/IEDM13553.2020.9372014","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372014","url":null,"abstract":"Recent advances in semiconductor and packaging technologies have accelerated the miniaturization of portable sensing devices including visible-domain cameras, IR cameras, and millimeter-wave (mmWave) radars. Simultaneously, image and sensor data processing capabilities based on Systems-on-Chip (SoCs) have evolved as well to the extent toward the goal of implementing learning-based automatic recognition capabilities. This paper discusses the challenges and opportunities associated with the vertical sensors-to-software integration of portable systems capable of performing multi-spectral imaging, where data from different portions of the EM spectrum is captured, processed, and displayed simultaneously. An example hardware implementation, multi-spectral image data, and potential applications are discussed","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123364008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372018
Jiwon Lee, Epimitheas Georgitzikis, Yunlong Li, Ziduo Lin, Jihoon Park, I. Lieberman, D. Cheyns, M. Jayapala, A. Lambrechts, S. Thijs, R. Stahl, P. Malinowski
A high pixel density image sensor for the Short Wave Infrared (SWIR) range is presented. A PbS quantum dot (QD) photodiode array is monolithically integrated on a silicon custom readout IC. Imaging in VIS and SWIR is demonstrated using focal plane arrays with pixel pitch down to record 1.82 μm. Through-silicon vision and lens-free imaging (LFI) microscopy are shown as applications that can benefit from high resolution/small pixel dimensions. In the LFI demonstration, the captured hologram is computationally reconstructed to acquire SWIR microscopic images, resulting in a wavelength equivalent resolution LFI microscopy system. To our knowledge, this is the smallest pitch SWIR pixel ever reported and the first LFI system using a QD image sensor.
{"title":"Imaging in Short-Wave Infrared with 1.82 μm Pixel Pitch Quantum Dot Image Sensor","authors":"Jiwon Lee, Epimitheas Georgitzikis, Yunlong Li, Ziduo Lin, Jihoon Park, I. Lieberman, D. Cheyns, M. Jayapala, A. Lambrechts, S. Thijs, R. Stahl, P. Malinowski","doi":"10.1109/IEDM13553.2020.9372018","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372018","url":null,"abstract":"A high pixel density image sensor for the Short Wave Infrared (SWIR) range is presented. A PbS quantum dot (QD) photodiode array is monolithically integrated on a silicon custom readout IC. Imaging in VIS and SWIR is demonstrated using focal plane arrays with pixel pitch down to record 1.82 μm. Through-silicon vision and lens-free imaging (LFI) microscopy are shown as applications that can benefit from high resolution/small pixel dimensions. In the LFI demonstration, the captured hologram is computationally reconstructed to acquire SWIR microscopic images, resulting in a wavelength equivalent resolution LFI microscopy system. To our knowledge, this is the smallest pitch SWIR pixel ever reported and the first LFI system using a QD image sensor.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121782547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372095
E. Persson, D. Wilhelm
In high-volume applications like home appliance motor drives, system cost and density are key value metrics. In many cases, system packaging puts severe limits on the power dissipation ability of the power electronics, so inverter losses must be kept to a minimum. GaN power transistors can offer significant improvements in power loss compared to IGBT or MOSFET-based inverters [1], [2], but controlling switching speed (dv/dt) can be challenging.This paper proposes a simplified active dv/dt control method that can be integrated into the driver IC and GaN transistor using low-cost techniques without adding passive components or bondwires inside the Integrated Power Module (IPM). The circuit is implemented in a monolithic 3-phase gate driver IC using low-cost 0.35 μm HVJI CMOS process. The package- integrated 3-phase inverter using the IC with 6 discrete GaN GIT is demonstrated to be capable of delivering 226 W from a 12x12 mm package, about double the power delivered by today’s silicon-based inverter in the same package size.The results of simulation and experiment are provided for an integrated IPM driving a motor load up to 226 W.
{"title":"Gate Drive Concept for dv/dt Control of GaN GIT-Based Motor Drive Inverters","authors":"E. Persson, D. Wilhelm","doi":"10.1109/IEDM13553.2020.9372095","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372095","url":null,"abstract":"In high-volume applications like home appliance motor drives, system cost and density are key value metrics. In many cases, system packaging puts severe limits on the power dissipation ability of the power electronics, so inverter losses must be kept to a minimum. GaN power transistors can offer significant improvements in power loss compared to IGBT or MOSFET-based inverters [1], [2], but controlling switching speed (dv/dt) can be challenging.This paper proposes a simplified active dv/dt control method that can be integrated into the driver IC and GaN transistor using low-cost techniques without adding passive components or bondwires inside the Integrated Power Module (IPM). The circuit is implemented in a monolithic 3-phase gate driver IC using low-cost 0.35 μm HVJI CMOS process. The package- integrated 3-phase inverter using the IC with 6 discrete GaN GIT is demonstrated to be capable of delivering 226 W from a 12x12 mm package, about double the power delivered by today’s silicon-based inverter in the same package size.The results of simulation and experiment are provided for an integrated IPM driving a motor load up to 226 W.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121423864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9371916
Mengyao Yan, Ming-Hung Wu, Hsin-Hui Huang, Yu-Hao Chen, Y. Chu, Tian-Li Wu, P. Yeh, Chih-Yao Wang, Yu-De Lin, Jian-Wei Su, P. Tzeng, S. Sheu, W. Lo, Chih-I Wu, T. Hou
An experiment-calibrated SPICE model considering dynamic ferroelectric switching and charge injection is established to co-optimize memory window, write speed, endurance, and retention of MFMFET where a standard BEOL HfZrOx MFM capacitor is stacked on top of the logic transistor. This promising SOC-compatible, low-power and low-voltage embedded memory achieves a high current on-off ratio > 104 when programming at ±2.5 V for 3 μs without compromising 10-year retention and MFM-equivalent endurance. A novel m-MFMFET utilizing multiple MFMs is also proposed. m-MFMFET achieves equivalent performance as the standard MFMFET but further reduces the unit cell size by 22 %.
{"title":"BEOL-Compatible Multiple Metal-Ferroelectric-Metal (m-MFM) FETs Designed for Low Voltage (2.5 V), High Density, and Excellent Reliability","authors":"Mengyao Yan, Ming-Hung Wu, Hsin-Hui Huang, Yu-Hao Chen, Y. Chu, Tian-Li Wu, P. Yeh, Chih-Yao Wang, Yu-De Lin, Jian-Wei Su, P. Tzeng, S. Sheu, W. Lo, Chih-I Wu, T. Hou","doi":"10.1109/IEDM13553.2020.9371916","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371916","url":null,"abstract":"An experiment-calibrated SPICE model considering dynamic ferroelectric switching and charge injection is established to co-optimize memory window, write speed, endurance, and retention of MFMFET where a standard BEOL HfZrOx MFM capacitor is stacked on top of the logic transistor. This promising SOC-compatible, low-power and low-voltage embedded memory achieves a high current on-off ratio > 104 when programming at ±2.5 V for 3 μs without compromising 10-year retention and MFM-equivalent endurance. A novel m-MFMFET utilizing multiple MFMs is also proposed. m-MFMFET achieves equivalent performance as the standard MFMFET but further reduces the unit cell size by 22 %.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"179 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122807921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372007
H. Arimura, E. Capogreco, A. Vohra, C. Porret, R. Loo, E. Rosseel, A. Hikavyy, D. Cott, G. Boccardi, L. Witters, G. Eneman, J. Mitard, N. Collaert, N. Horiguchi
This paper describes our recent research progress on high-mobility Ge-channel n/pFETs. Gate stack, junction and contact are the key challenging components of Ge n/pFETs. Through the improvement of those unit modules, the electrical performance and reliability of Ge FinFET and gate-all-around (GAA) nanowire (NW) pFETs have been improved. Remaining technical challenges for the realization of high performance and reliable Ge n/pFETs will be discussed.
{"title":"Toward high-performance and reliable Ge channel devices for 2 nm node and beyond","authors":"H. Arimura, E. Capogreco, A. Vohra, C. Porret, R. Loo, E. Rosseel, A. Hikavyy, D. Cott, G. Boccardi, L. Witters, G. Eneman, J. Mitard, N. Collaert, N. Horiguchi","doi":"10.1109/IEDM13553.2020.9372007","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372007","url":null,"abstract":"This paper describes our recent research progress on high-mobility Ge-channel n/pFETs. Gate stack, junction and contact are the key challenging components of Ge n/pFETs. Through the improvement of those unit modules, the electrical performance and reliability of Ge FinFET and gate-all-around (GAA) nanowire (NW) pFETs have been improved. Remaining technical challenges for the realization of high performance and reliable Ge n/pFETs will be discussed.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130837234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372026
P. Basset, H. Zhang, F. Marty, A. Delbani, N. Hodžić, A. Karami, D. Galayko
As for any electrostatic transducer, triboelectric energy generators (TENGs) need to maximize their bias voltage for a good kinetic-to-electrical energy conversion. If several hundreds of volts can be obtained directly by triboelectric contacts for some state-of-art devices, unstable charge-pump (UCP) conditioning circuits can also be used to reach such high values with more basic TENGs. Whatever the chosen solution, this high-voltage must be reduced to a few volts to power an electronic device. In this abstract, we first compare the three main UCPs and we propose to use an autonomous MEMS micro-plasma switch in a Buck DC-DC converter in order to maximized the voltage across the TENG while obtaining a low voltage rectified output without any external control.
{"title":"High-voltage micro-plasma switch for efficient power management of triboelectric kinetic energy harvesters","authors":"P. Basset, H. Zhang, F. Marty, A. Delbani, N. Hodžić, A. Karami, D. Galayko","doi":"10.1109/IEDM13553.2020.9372026","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372026","url":null,"abstract":"As for any electrostatic transducer, triboelectric energy generators (TENGs) need to maximize their bias voltage for a good kinetic-to-electrical energy conversion. If several hundreds of volts can be obtained directly by triboelectric contacts for some state-of-art devices, unstable charge-pump (UCP) conditioning circuits can also be used to reach such high values with more basic TENGs. Whatever the chosen solution, this high-voltage must be reduced to a few volts to power an electronic device. In this abstract, we first compare the three main UCPs and we propose to use an autonomous MEMS micro-plasma switch in a Buck DC-DC converter in order to maximized the voltage across the TENG while obtaining a low voltage rectified output without any external control.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131143114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372005
Y. Cheng, F. Lee, M.F. Chen, J. Yuan, Tze-Chiang Huang, K.-J. Chen, C. Wang, C.-L. Chen, C. Tsai, Douglas C. H. Yu
This paper demonstrates the next-generation design and technology co-optimization (DTCO) of system on integrated chip (SoIC) for mobile and HPC applications, where the SoIC technology was proposed to integrate multichips with different functionality and technology into a single SoC chip. The new DTCO includes overall die partitioning, die integration, and interconnect. These methodologies can be used for improving time-to-market and trade-off between performance and cost. In this paper, two prototypes of stacking CPU and memory dies are demonstrated with 15% performance gain and 30% average point-to-point distance reduction.
{"title":"Next-Generation Design and Technology Co-optimization (DTCO) of System on Integrated Chip (SoIC) for Mobile and HPC Applications","authors":"Y. Cheng, F. Lee, M.F. Chen, J. Yuan, Tze-Chiang Huang, K.-J. Chen, C. Wang, C.-L. Chen, C. Tsai, Douglas C. H. Yu","doi":"10.1109/IEDM13553.2020.9372005","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372005","url":null,"abstract":"This paper demonstrates the next-generation design and technology co-optimization (DTCO) of system on integrated chip (SoIC) for mobile and HPC applications, where the SoIC technology was proposed to integrate multichips with different functionality and technology into a single SoC chip. The new DTCO includes overall die partitioning, die integration, and interconnect. These methodologies can be used for improving time-to-market and trade-off between performance and cost. In this paper, two prototypes of stacking CPU and memory dies are demonstrated with 15% performance gain and 30% average point-to-point distance reduction.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130200397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：