Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372095
E. Persson, D. Wilhelm
In high-volume applications like home appliance motor drives, system cost and density are key value metrics. In many cases, system packaging puts severe limits on the power dissipation ability of the power electronics, so inverter losses must be kept to a minimum. GaN power transistors can offer significant improvements in power loss compared to IGBT or MOSFET-based inverters [1], [2], but controlling switching speed (dv/dt) can be challenging.This paper proposes a simplified active dv/dt control method that can be integrated into the driver IC and GaN transistor using low-cost techniques without adding passive components or bondwires inside the Integrated Power Module (IPM). The circuit is implemented in a monolithic 3-phase gate driver IC using low-cost 0.35 μm HVJI CMOS process. The package- integrated 3-phase inverter using the IC with 6 discrete GaN GIT is demonstrated to be capable of delivering 226 W from a 12x12 mm package, about double the power delivered by today’s silicon-based inverter in the same package size.The results of simulation and experiment are provided for an integrated IPM driving a motor load up to 226 W.
{"title":"Gate Drive Concept for dv/dt Control of GaN GIT-Based Motor Drive Inverters","authors":"E. Persson, D. Wilhelm","doi":"10.1109/IEDM13553.2020.9372095","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372095","url":null,"abstract":"In high-volume applications like home appliance motor drives, system cost and density are key value metrics. In many cases, system packaging puts severe limits on the power dissipation ability of the power electronics, so inverter losses must be kept to a minimum. GaN power transistors can offer significant improvements in power loss compared to IGBT or MOSFET-based inverters [1], [2], but controlling switching speed (dv/dt) can be challenging.This paper proposes a simplified active dv/dt control method that can be integrated into the driver IC and GaN transistor using low-cost techniques without adding passive components or bondwires inside the Integrated Power Module (IPM). The circuit is implemented in a monolithic 3-phase gate driver IC using low-cost 0.35 μm HVJI CMOS process. The package- integrated 3-phase inverter using the IC with 6 discrete GaN GIT is demonstrated to be capable of delivering 226 W from a 12x12 mm package, about double the power delivered by today’s silicon-based inverter in the same package size.The results of simulation and experiment are provided for an integrated IPM driving a motor load up to 226 W.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121423864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372018
Jiwon Lee, Epimitheas Georgitzikis, Yunlong Li, Ziduo Lin, Jihoon Park, I. Lieberman, D. Cheyns, M. Jayapala, A. Lambrechts, S. Thijs, R. Stahl, P. Malinowski
A high pixel density image sensor for the Short Wave Infrared (SWIR) range is presented. A PbS quantum dot (QD) photodiode array is monolithically integrated on a silicon custom readout IC. Imaging in VIS and SWIR is demonstrated using focal plane arrays with pixel pitch down to record 1.82 μm. Through-silicon vision and lens-free imaging (LFI) microscopy are shown as applications that can benefit from high resolution/small pixel dimensions. In the LFI demonstration, the captured hologram is computationally reconstructed to acquire SWIR microscopic images, resulting in a wavelength equivalent resolution LFI microscopy system. To our knowledge, this is the smallest pitch SWIR pixel ever reported and the first LFI system using a QD image sensor.
{"title":"Imaging in Short-Wave Infrared with 1.82 μm Pixel Pitch Quantum Dot Image Sensor","authors":"Jiwon Lee, Epimitheas Georgitzikis, Yunlong Li, Ziduo Lin, Jihoon Park, I. Lieberman, D. Cheyns, M. Jayapala, A. Lambrechts, S. Thijs, R. Stahl, P. Malinowski","doi":"10.1109/IEDM13553.2020.9372018","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372018","url":null,"abstract":"A high pixel density image sensor for the Short Wave Infrared (SWIR) range is presented. A PbS quantum dot (QD) photodiode array is monolithically integrated on a silicon custom readout IC. Imaging in VIS and SWIR is demonstrated using focal plane arrays with pixel pitch down to record 1.82 μm. Through-silicon vision and lens-free imaging (LFI) microscopy are shown as applications that can benefit from high resolution/small pixel dimensions. In the LFI demonstration, the captured hologram is computationally reconstructed to acquire SWIR microscopic images, resulting in a wavelength equivalent resolution LFI microscopy system. To our knowledge, this is the smallest pitch SWIR pixel ever reported and the first LFI system using a QD image sensor.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121782547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372128
Hongyan Zhou, Shibin Zhang, Zhongxu Li, Kai Huang, Pengcheng Zheng, Jinbo Wu, Chen Shen, Liping Zhang, T. You, Lianghui Zhang, Kang Liu, Huarui Sun, Hongtao Xu, Xiaomeng Zhao, X. Ou
We demonstrate groups of surface wave (SH0 mode) and Lamb wave (S0 mode) acoustic devices on lithium niobate thin films on silicon carbide (LNOSiC) heterogeneous substrate. The 4-inch LNOSiC with an excellent thermal transport property is prepared by ion-cutting process. The fabricated acoustic resonators on the LNOSiC substrate show scalable resonances from 2.0 to 4.72 GHz, in which the SH0 (S0) mode resonator shows a $k_t^2$ of 24.1% (15.5%) and a maximum Bode-Q of 976 (577) at 2.54 (3.56) GHz. Moreover, the phase velocity (Vp) of the SH0 (S0) mode is greater than 5000 (6400) m/s, which is about 1.25 (1.6) times higher than that of the conventional SAWs, so as the operating frequency. The filter with a center frequency of 2.62 GHz, an insertion loss (IL) of 1.06 dB, and a 3-dB fractional bandwidth (FBW) of 12.6% (three times larger than that of the conventional SAWs) is also achieved. The acoustic devices on heterogeneous substrate are very promising for high frequency, wideband and high power 5G front-ends.
{"title":"Surface Wave and Lamb Wave Acoustic Devices on Heterogenous Substrate for 5G Front-Ends","authors":"Hongyan Zhou, Shibin Zhang, Zhongxu Li, Kai Huang, Pengcheng Zheng, Jinbo Wu, Chen Shen, Liping Zhang, T. You, Lianghui Zhang, Kang Liu, Huarui Sun, Hongtao Xu, Xiaomeng Zhao, X. Ou","doi":"10.1109/IEDM13553.2020.9372128","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372128","url":null,"abstract":"We demonstrate groups of surface wave (SH0 mode) and Lamb wave (S0 mode) acoustic devices on lithium niobate thin films on silicon carbide (LNOSiC) heterogeneous substrate. The 4-inch LNOSiC with an excellent thermal transport property is prepared by ion-cutting process. The fabricated acoustic resonators on the LNOSiC substrate show scalable resonances from 2.0 to 4.72 GHz, in which the SH0 (S0) mode resonator shows a $k_t^2$ of 24.1% (15.5%) and a maximum Bode-Q of 976 (577) at 2.54 (3.56) GHz. Moreover, the phase velocity (Vp) of the SH0 (S0) mode is greater than 5000 (6400) m/s, which is about 1.25 (1.6) times higher than that of the conventional SAWs, so as the operating frequency. The filter with a center frequency of 2.62 GHz, an insertion loss (IL) of 1.06 dB, and a 3-dB fractional bandwidth (FBW) of 12.6% (three times larger than that of the conventional SAWs) is also achieved. The acoustic devices on heterogeneous substrate are very promising for high frequency, wideband and high power 5G front-ends.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125443901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372059
Sun Il Kim, Junghyun Park, B. Jeong, Duhyun Lee, Jungwoo Kim, C. Shin, Chang-Bum Lee, Tatsuhiro Otsuka, Sangwook Kim, Kiyeon Yang, Yong-Young Park, Jisan Lee, Inoh Hwang, Jaeduck Jang, K. Ha, H. Choo, B. Choi, Sungwoo Hwang
For the first time, we have successfully demonstrated a 3-dimensional (3-D) depth scan using an electrically-tunable active metasurface, which is an array of plasmonic resonators with an active indium-tin-oxide (ITO) layer. Our active device can steer a beam in reflection with a positive side-mode suppression ratio by independently controlling the amplitude and the phase from 0 to 360° using two separate bias controls. These are very promising results for small and high speed 3D depth sensing for mobile and automotive applications.
{"title":"Electrically Reconfigurable Active Metasurface for 3D Distance Ranging","authors":"Sun Il Kim, Junghyun Park, B. Jeong, Duhyun Lee, Jungwoo Kim, C. Shin, Chang-Bum Lee, Tatsuhiro Otsuka, Sangwook Kim, Kiyeon Yang, Yong-Young Park, Jisan Lee, Inoh Hwang, Jaeduck Jang, K. Ha, H. Choo, B. Choi, Sungwoo Hwang","doi":"10.1109/IEDM13553.2020.9372059","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372059","url":null,"abstract":"For the first time, we have successfully demonstrated a 3-dimensional (3-D) depth scan using an electrically-tunable active metasurface, which is an array of plasmonic resonators with an active indium-tin-oxide (ITO) layer. Our active device can steer a beam in reflection with a positive side-mode suppression ratio by independently controlling the amplitude and the phase from 0 to 360° using two separate bias controls. These are very promising results for small and high speed 3D depth sensing for mobile and automotive applications.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115863786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372046
M. Perumkunnil, F. Yasin, S. Rao, S. Salahuddin, D. Milojevic, G. van der Plas, J. Ryckaert, E. Beyne, A. Furnémont, G. Kar
This paper analyzes the most feasible 3D integration and partitioning scheme for STT-MRAM based caches in an advanced Mobile SoC based on the process demonstration of the first ever functional 3D integrated STT devices. We present 3D partitioning schemes from a design -architecture perspective and Power Performance and Area (PPA) analysis is carried out for the 2D and 3D SoC designs with both SRAM and STT-MRAM caches. Our work shows that the PPA benefits from 3D Memory on Logic partitioning are magnified when it can be exploited to accommodate larger caches in general. We also show that STT-MRAM based 3D partitioned caches can exploit this potential increase in capacity to improve performance even more than SRAM. These 3D Wafer-to-Wafer (W2W) integrated STT-MRAM caches can result in up-to 30% performance improvement at 17% power and 15% footprint reduction for our target SoC.
{"title":"System exploration and technology demonstration of 3D Wafer-to-Wafer integrated STT-MRAM based caches for advanced Mobile SoCs","authors":"M. Perumkunnil, F. Yasin, S. Rao, S. Salahuddin, D. Milojevic, G. van der Plas, J. Ryckaert, E. Beyne, A. Furnémont, G. Kar","doi":"10.1109/IEDM13553.2020.9372046","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372046","url":null,"abstract":"This paper analyzes the most feasible 3D integration and partitioning scheme for STT-MRAM based caches in an advanced Mobile SoC based on the process demonstration of the first ever functional 3D integrated STT devices. We present 3D partitioning schemes from a design -architecture perspective and Power Performance and Area (PPA) analysis is carried out for the 2D and 3D SoC designs with both SRAM and STT-MRAM caches. Our work shows that the PPA benefits from 3D Memory on Logic partitioning are magnified when it can be exploited to accommodate larger caches in general. We also show that STT-MRAM based 3D partitioned caches can exploit this potential increase in capacity to improve performance even more than SRAM. These 3D Wafer-to-Wafer (W2W) integrated STT-MRAM caches can result in up-to 30% performance improvement at 17% power and 15% footprint reduction for our target SoC.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123314641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9371916
Mengyao Yan, Ming-Hung Wu, Hsin-Hui Huang, Yu-Hao Chen, Y. Chu, Tian-Li Wu, P. Yeh, Chih-Yao Wang, Yu-De Lin, Jian-Wei Su, P. Tzeng, S. Sheu, W. Lo, Chih-I Wu, T. Hou
An experiment-calibrated SPICE model considering dynamic ferroelectric switching and charge injection is established to co-optimize memory window, write speed, endurance, and retention of MFMFET where a standard BEOL HfZrOx MFM capacitor is stacked on top of the logic transistor. This promising SOC-compatible, low-power and low-voltage embedded memory achieves a high current on-off ratio > 104 when programming at ±2.5 V for 3 μs without compromising 10-year retention and MFM-equivalent endurance. A novel m-MFMFET utilizing multiple MFMs is also proposed. m-MFMFET achieves equivalent performance as the standard MFMFET but further reduces the unit cell size by 22 %.
{"title":"BEOL-Compatible Multiple Metal-Ferroelectric-Metal (m-MFM) FETs Designed for Low Voltage (2.5 V), High Density, and Excellent Reliability","authors":"Mengyao Yan, Ming-Hung Wu, Hsin-Hui Huang, Yu-Hao Chen, Y. Chu, Tian-Li Wu, P. Yeh, Chih-Yao Wang, Yu-De Lin, Jian-Wei Su, P. Tzeng, S. Sheu, W. Lo, Chih-I Wu, T. Hou","doi":"10.1109/IEDM13553.2020.9371916","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371916","url":null,"abstract":"An experiment-calibrated SPICE model considering dynamic ferroelectric switching and charge injection is established to co-optimize memory window, write speed, endurance, and retention of MFMFET where a standard BEOL HfZrOx MFM capacitor is stacked on top of the logic transistor. This promising SOC-compatible, low-power and low-voltage embedded memory achieves a high current on-off ratio > 104 when programming at ±2.5 V for 3 μs without compromising 10-year retention and MFM-equivalent endurance. A novel m-MFMFET utilizing multiple MFMs is also proposed. m-MFMFET achieves equivalent performance as the standard MFMFET but further reduces the unit cell size by 22 %.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"179 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122807921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372004
M. Garcia Bardon, P. Wuytens, L. Ragnarsson, G. Mirabelli, D. Jang, G. Willems, A. Mallik, A. Spessot, J. Ryckaert, B. Parvais
Driven by concerns on climate change, resources depletion, local and global pollution, sustainability is becoming an integral component of business and of regulations. The progress of Design Technology Co- Optimization (DTCO) methodologies and tools, building transversal knowledge from manufacturing to design, provides an opportunity to develop a framework for early sustainability assessments of logic technologies. Environmental scores can be derived together with the established Power, Performance, Area, Cost (PPAC) metrics. To demonstrate this approach, we evaluate the energy and water consumption as well as the greenhouse gas emissions trends from processing logic nodes from iN28 to iN3 with different scaling scenarios.
{"title":"DTCO including Sustainability: Power-Performance-Area-Cost-Environmental score (PPACE) Analysis for Logic Technologies","authors":"M. Garcia Bardon, P. Wuytens, L. Ragnarsson, G. Mirabelli, D. Jang, G. Willems, A. Mallik, A. Spessot, J. Ryckaert, B. Parvais","doi":"10.1109/IEDM13553.2020.9372004","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372004","url":null,"abstract":"Driven by concerns on climate change, resources depletion, local and global pollution, sustainability is becoming an integral component of business and of regulations. The progress of Design Technology Co- Optimization (DTCO) methodologies and tools, building transversal knowledge from manufacturing to design, provides an opportunity to develop a framework for early sustainability assessments of logic technologies. Environmental scores can be derived together with the established Power, Performance, Area, Cost (PPAC) metrics. To demonstrate this approach, we evaluate the energy and water consumption as well as the greenhouse gas emissions trends from processing logic nodes from iN28 to iN3 with different scaling scenarios.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128347876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372041
S. Mochizuki, M. Bhuiyan, H. Zhou, J. Zhang, E. Stuckert, J. Li, K. Zhao, M. Wang, V. Basker, N. Loubet, D. Guo, B. Haran, H. Bu
Stacked Gate-All-Around (GAA) nanosheet pFETs with compressively strained Si1-xGex channel have been fabricated to explore their electrical benefits. The Si1-xGex NS channel structure with high crystalline quality and 1GPa compressive stress has been realized for the first time. Systematic study has been performed to understand the effect of epitaxial Si1-xGex thickness, Ge fraction, and Si cap thickness on the Si1-xGex NS channel device characteristics. It is found that the compressively strained Si1-xGex NS channel provides a 100% uplift in peak hole mobility with a corresponding channel resistance reduction of 40% while maintaining an excellent subthreshold slope of below 70 mV/dec.
{"title":"Stacked Gate-All-Around Nanosheet pFET with Highly Compressive Strained Si1-xGex Channel","authors":"S. Mochizuki, M. Bhuiyan, H. Zhou, J. Zhang, E. Stuckert, J. Li, K. Zhao, M. Wang, V. Basker, N. Loubet, D. Guo, B. Haran, H. Bu","doi":"10.1109/IEDM13553.2020.9372041","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372041","url":null,"abstract":"Stacked Gate-All-Around (GAA) nanosheet pFETs with compressively strained Si<inf>1-x</inf>Ge<inf>x</inf> channel have been fabricated to explore their electrical benefits. The Si<inf>1-x</inf>Ge<inf>x</inf> NS channel structure with high crystalline quality and 1GPa compressive stress has been realized for the first time. Systematic study has been performed to understand the effect of epitaxial Si<inf>1-x</inf>Ge<inf>x</inf> thickness, Ge fraction, and Si cap thickness on the Si<inf>1-x</inf>Ge<inf>x</inf> NS channel device characteristics. It is found that the compressively strained Si<inf>1-x</inf>Ge<inf>x</inf> NS channel provides a 100% uplift in peak hole mobility with a corresponding channel resistance reduction of 40% while maintaining an excellent subthreshold slope of below 70 mV/dec.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"1993 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128628055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372016
R. Siddique, L. Liedtke, H. Park, S. Y. Lee, H. Raniwala, D. Y. Park, D. Lim, H. Choo
Glaucoma, one of the leading cause of irreversible blindness, is largely caused by an elevated intraocular pressure (IOP). However, current IOP monitoring techniques inherit major disadvantages such as imprecision, no real or long time monitoring, and difficult readout. Here, we report on a highly miniaturized (200 um thick) optomechanical nanophotonic sensor implant for long-term, continuous and on-demand IOP monitoring. This IOP sensor is made of a flexible 3D hybrid photonic crystals (HPC) that functions as a pressure-sensitive optical resonator (0.1 nm/mm Hg) and delivers IOP readings when interrogated with near-infrared light with an average accuracy of 0.56 mm Hg over the range of 0–40 mm Hg. A new fabrication process is developed using colloidal self-assembly leading to a single step formation of hybrid periodic and amorphous layers exploiting the inverse process of a drying "coffee-stain" effect. The HPC results in a wide-angle strong resonance of ±40° ensuring an easy and accurate remote and long readout distance. 8 sensors were mounted inside the anterior chamber in New Zealand white rabbits and provided continuous, accurate measurements of IOP with handheld detector for up to 6 months with no signs of inflammation.
青光眼是不可逆失明的主要原因之一，主要由眼压升高引起。然而，目前的IOP监测技术存在着不精确、不能实时监测或长时间监测、读数困难等主要缺点。在这里，我们报道了一种高度小型化(200um厚)的光机械纳米光子传感器植入物，用于长期、连续和按需监测IOP。该IOP传感器由柔性3D混合光子晶体(HPC)制成，可作为压敏光学谐振器(0.1 nm/mm Hg)，并在近红外光下提供IOP读数，在0-40 mm Hg范围内平均精度为0.56 mm Hg。利用胶体自组装技术开发了一种新的制造工艺，利用干燥“咖啡渍”效应的逆过程，可一步形成混合周期性和非晶态层。HPC产生±40°的广角强共振，确保轻松准确的远程和长读数距离。在新西兰大白兔的前房内安装8个传感器，用手持探测器连续、准确地测量IOP长达6个月，无炎症迹象。
{"title":"Nanophotonic sensor implants with 3D hybrid periodic-amorphous photonic crystals for wide-angle monitoring of long-term in-vivo intraocular pressure","authors":"R. Siddique, L. Liedtke, H. Park, S. Y. Lee, H. Raniwala, D. Y. Park, D. Lim, H. Choo","doi":"10.1109/IEDM13553.2020.9372016","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372016","url":null,"abstract":"Glaucoma, one of the leading cause of irreversible blindness, is largely caused by an elevated intraocular pressure (IOP). However, current IOP monitoring techniques inherit major disadvantages such as imprecision, no real or long time monitoring, and difficult readout. Here, we report on a highly miniaturized (200 um thick) optomechanical nanophotonic sensor implant for long-term, continuous and on-demand IOP monitoring. This IOP sensor is made of a flexible 3D hybrid photonic crystals (HPC) that functions as a pressure-sensitive optical resonator (0.1 nm/mm Hg) and delivers IOP readings when interrogated with near-infrared light with an average accuracy of 0.56 mm Hg over the range of 0–40 mm Hg. A new fabrication process is developed using colloidal self-assembly leading to a single step formation of hybrid periodic and amorphous layers exploiting the inverse process of a drying \"coffee-stain\" effect. The HPC results in a wide-angle strong resonance of ±40° ensuring an easy and accurate remote and long readout distance. 8 sensors were mounted inside the anterior chamber in New Zealand white rabbits and provided continuous, accurate measurements of IOP with handheld detector for up to 6 months with no signs of inflammation.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129023026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372055
D. Lin, Xiangyu Wu, D. Cott, D. Verreck, B. Groven, S. Sergeant, Q. Smets, S. Sutar, I. Asselberghs, I. Radu
We have engineered dual gate WS2 transistors with scaled top and back gate stacks based on a surface physisorption ALD approach for advanced logic applications. Connected dual gate MOSFET operation with a 2ML WS2 channel reaches 210μA/um drain current and 2.7μF/cm2 capacitance (>3.4×1013/cm2 sheet charge density) at 3V gate bias, with >108 on-off ratio, 120μS/um max. transconductance and 109mV/dec sub-threshold swing at 100nm Lch. This dual gate design enables us to explore EOT scaling, ambipolar I-V and C-V(capacitance-voltage) response on CVD WS2 channel.
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