Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772735
Siavash Kananian, Cheng Chen, A. Poon
Fully passive sensors (FPS) consist of a sensing element $(mathrm{R}_{mathrm{s}}$ or $mathrm{C}_{2}$ in Fig. 1) and an inductor forming an RLC tank. Compared to legacy sensors (NFC, BLE, RFID), FPSs offer a simple chipless solution with battery-free operation and extremely low cost for scenarios such as implantable, biodegradable, biocompatible, and stretchable applications where legacy sensors cannot be deployed. Typically, sensor measurement is performed through near-field inductive coupling (NFIC) of a reader coil to the sensor with the goal of measuring $mathrm{R}_{mathrm{s}}$ or $mathrm{C}_{2}$ (Fig. 1). Unlike the sensor, the reader remains the bottleneck due to its large size, high power consumption and distance-dependency of the results due to NFIC and may require extensive calibration. As such, existing readers [1]–[4] are not well-suited for handheld low-power operation with non-fixed readout distance. We utilize the properties of coupled resonators and a dual-mode LC-VCO as the reader to address the challenges discussed above for resistive FPS measurement.
{"title":"An energy-harvesting stamp-sized reader for distance-immune interrogation of passive wireless sensors","authors":"Siavash Kananian, Cheng Chen, A. Poon","doi":"10.1109/CICC53496.2022.9772735","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772735","url":null,"abstract":"Fully passive sensors (FPS) consist of a sensing element $(mathrm{R}_{mathrm{s}}$ or $mathrm{C}_{2}$ in Fig. 1) and an inductor forming an RLC tank. Compared to legacy sensors (NFC, BLE, RFID), FPSs offer a simple chipless solution with battery-free operation and extremely low cost for scenarios such as implantable, biodegradable, biocompatible, and stretchable applications where legacy sensors cannot be deployed. Typically, sensor measurement is performed through near-field inductive coupling (NFIC) of a reader coil to the sensor with the goal of measuring $mathrm{R}_{mathrm{s}}$ or $mathrm{C}_{2}$ (Fig. 1). Unlike the sensor, the reader remains the bottleneck due to its large size, high power consumption and distance-dependency of the results due to NFIC and may require extensive calibration. As such, existing readers [1]–[4] are not well-suited for handheld low-power operation with non-fixed readout distance. We utilize the properties of coupled resonators and a dual-mode LC-VCO as the reader to address the challenges discussed above for resistive FPS measurement.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134273261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772838
Yijie Wei, Xi Chen, Jie Gu
Two million amputee patients in the US rely on prosthetic devices for assistance or rehabilitation. Compared with skin-mounted devices, muscle implantable devices offer better signal quality, lower noise inference, less wires and skin irritation. In prior works, a near-infrared powered neural recoding system was demonstrated with optical light TX/RX [1]. An Ultrasound powered neural recorder with AM backscatter was presented [2]. Stimulus systems powered by on/off-chip RF coil via inductive link were also developed [3]–[5]. However, prior implantable systems only perform neural recording with neural signals transferred to external devices for further classification. As in Fig. 1, the transmission of raw neural signals consumes high power and suffers from high bit errors. In addition, external devices may not meet the millisecond classification latency needed for real-time prosthetic control. Hence, a fully integrated solution with embedded classifiers for EMG-based gesture classification offers significant benefits of reduced transmission efforts, low latency, and low error rate. However, a neural network (NN) classifier under wireless power poses challenges of robustly sending weights into the device under noisy conditions. This work, for the first time, presents a fully integrated implantable wireless powered SoC with an embedded NN classifier. The contributions of this work include (1) a wireless powered SoC with NN classifiers and on-chip coil is presented paving the way to embed AI techniques into implantable devices; (2) To reduce the NN weight for sending into the chip at startup, Huffman coding and low-rank singular value decomposition (SVD) techniques are implemented reducing data volume by 29%; (3) New activity detection for NN computing and adaptive power control under unstable wireless power are developed improving power efficiency of the system by 45%; (4) A unique data encoding strategy is also utilized to reduce the bit error rate by orders of magnitudes.
{"title":"A 65nm Implantable Gesture Classification SoC for Rehabilitation with Enhanced Data Compression and Encoding for Robust Neural Network Operation Under Wireless Power Condition","authors":"Yijie Wei, Xi Chen, Jie Gu","doi":"10.1109/CICC53496.2022.9772838","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772838","url":null,"abstract":"Two million amputee patients in the US rely on prosthetic devices for assistance or rehabilitation. Compared with skin-mounted devices, muscle implantable devices offer better signal quality, lower noise inference, less wires and skin irritation. In prior works, a near-infrared powered neural recoding system was demonstrated with optical light TX/RX [1]. An Ultrasound powered neural recorder with AM backscatter was presented [2]. Stimulus systems powered by on/off-chip RF coil via inductive link were also developed [3]–[5]. However, prior implantable systems only perform neural recording with neural signals transferred to external devices for further classification. As in Fig. 1, the transmission of raw neural signals consumes high power and suffers from high bit errors. In addition, external devices may not meet the millisecond classification latency needed for real-time prosthetic control. Hence, a fully integrated solution with embedded classifiers for EMG-based gesture classification offers significant benefits of reduced transmission efforts, low latency, and low error rate. However, a neural network (NN) classifier under wireless power poses challenges of robustly sending weights into the device under noisy conditions. This work, for the first time, presents a fully integrated implantable wireless powered SoC with an embedded NN classifier. The contributions of this work include (1) a wireless powered SoC with NN classifiers and on-chip coil is presented paving the way to embed AI techniques into implantable devices; (2) To reduce the NN weight for sending into the chip at startup, Huffman coding and low-rank singular value decomposition (SVD) techniques are implemented reducing data volume by 29%; (3) New activity detection for NN computing and adaptive power control under unstable wireless power are developed improving power efficiency of the system by 45%; (4) A unique data encoding strategy is also utilized to reduce the bit error rate by orders of magnitudes.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134383191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772795
J. Liu, J. Xiao, J. Fan, Q. Liu, Z. Zhu, S. Li, Z. Zhang, S. Yang, W. Shan, S. Lin, L. Chang, L. Zhou, J. Zhou
Wearable intelligent ECG sensors integrating cardiac arrhythmia classification processor have been used to detect and classify arrhythmia to alert users for potential cardiovascular diseases [1] [2]. The state-of-the-art arrhythmia classification processors using neural network (NN) can achieve high accuracy, but the high complexity of NN computation brings significant energy consumption. Another challenge is that the accuracy of the NN is affected by the patient-to-patient variation, leading to accuracy degradation when applying a trained NN to the patients whose ECG features differ from that in the training database. To address the above issues, in this work, we proposed an arrhythmia classification processor using heartbeat difference encoding and event-driven NN to achieve high energy efficiency and high accuracy against patient-to-patient variation. The main features of the proposed processor include a) heartbeat difference based classification to improve the accuracy under the patient-to-patient variation and reduce the energy consumption. b) event-driven NN computation with shared feature extraction to reduce the energy consumption. c) adaptive NN wake-up technique to reduce the energy consumption while maintaining accuracy.
{"title":"An Energy-Efficient Cardiac Arrhythmia Classification Processor using Heartbeat Difference based Classification and Event-Driven Neural Network Computation with Adaptive Wake-Up","authors":"J. Liu, J. Xiao, J. Fan, Q. Liu, Z. Zhu, S. Li, Z. Zhang, S. Yang, W. Shan, S. Lin, L. Chang, L. Zhou, J. Zhou","doi":"10.1109/CICC53496.2022.9772795","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772795","url":null,"abstract":"Wearable intelligent ECG sensors integrating cardiac arrhythmia classification processor have been used to detect and classify arrhythmia to alert users for potential cardiovascular diseases [1] [2]. The state-of-the-art arrhythmia classification processors using neural network (NN) can achieve high accuracy, but the high complexity of NN computation brings significant energy consumption. Another challenge is that the accuracy of the NN is affected by the patient-to-patient variation, leading to accuracy degradation when applying a trained NN to the patients whose ECG features differ from that in the training database. To address the above issues, in this work, we proposed an arrhythmia classification processor using heartbeat difference encoding and event-driven NN to achieve high energy efficiency and high accuracy against patient-to-patient variation. The main features of the proposed processor include a) heartbeat difference based classification to improve the accuracy under the patient-to-patient variation and reduce the energy consumption. b) event-driven NN computation with shared feature extraction to reduce the energy consumption. c) adaptive NN wake-up technique to reduce the energy consumption while maintaining accuracy.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116462431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772854
Muhammad Ali Montazerolghaem, L. D. Vreede, M. Babaie
Recent sub-6GHz receivers (RXs) attempted to realize RF channel selection at the RX input for suppressing large close-in blockers. Although mixer-first RXs can achieve sharp RF filtering and good out-of-band (OOB) linearity, they suffer from large noise figure (NF) and high LO leakage [1] [2]. Alternatively, [3]–[5] exploited an N-path notch filter around an LNTA to simultaneously achieve low NF and a moderate channel selection at the RX input. However, their OOB IIP3 and blocker 1dB compression point (B1dS) are at least 10dB worse than the mixer-first RXs. This paper proposes an LNTA-based RX that shows a similar OOB linearity as prior art mixer-first RXs without sacrificing NF. This is achieved by (1) adding a parallel preselect filter at the RX input to improve the RF selectivity and achieve +6dBm B1dB; (2) proposing third-order RF and baseband filters to attenuate close-in blockers by a 120dB/dec roll-off; (3) introducing a feedback network to reduce the in-band (IB) gain fluctuations to <0.5dB.
{"title":"A 0.5-3GHz Receiver with a Parallel Preselect Filter Achieving 120dB/dec Channel Selectivity and +28dBm Out-of-Band IIP3","authors":"Muhammad Ali Montazerolghaem, L. D. Vreede, M. Babaie","doi":"10.1109/CICC53496.2022.9772854","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772854","url":null,"abstract":"Recent sub-6GHz receivers (RXs) attempted to realize RF channel selection at the RX input for suppressing large close-in blockers. Although mixer-first RXs can achieve sharp RF filtering and good out-of-band (OOB) linearity, they suffer from large noise figure (NF) and high LO leakage [1] [2]. Alternatively, [3]–[5] exploited an N-path notch filter around an LNTA to simultaneously achieve low NF and a moderate channel selection at the RX input. However, their OOB IIP3 and blocker 1dB compression point (B1dS) are at least 10dB worse than the mixer-first RXs. This paper proposes an LNTA-based RX that shows a similar OOB linearity as prior art mixer-first RXs without sacrificing NF. This is achieved by (1) adding a parallel preselect filter at the RX input to improve the RF selectivity and achieve +6dBm B1dB; (2) proposing third-order RF and baseband filters to attenuate close-in blockers by a 120dB/dec roll-off; (3) introducing a feedback network to reduce the in-band (IB) gain fluctuations to <0.5dB.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128754035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772855
Hongchang Qiao, Chenchang Zhan
The Internet of Things (loT) is developing rapidly, and energy harvesting (EH) provides the power source impetus for it. Still the energy collected from EH is generally underfed, which obliges EH powered modules to achieve low power consumption as much as possible. Hence, the growth of low voltage and low quiescent current designs are pushed forward. For applications with sub-10µA under low-supply (200-300mV), such as sensors for monitoring, SRAM [1], designing an additional regulator is overburdened and one solution is the voltage reference (VR) integrated with output buffer. Whereas the added buffer brings extra area and power consumption (e.g., microwatt), the mismatch substantially degrades the temperature coefficient (TC). Therefore, a sub-nanowatt VR with current sourcing capability is of momentous significance. Besides, supposing that the power consumption of the designed VR is in the order of picowatt, and due to the process restraint, the subsequent gates of MOS transistors connected to the VR output have leakage current of picoampere, it will directly cause the VR to be shut down, needless to mention the microampere loading capability. However, the existing CMOS voltage references (CVRs) hardly source current [2]–[6].
{"title":"A 19-30ppm/°C Temperature Coefficient Sub-Nanowatt CMOS Voltage Reference with 10-µA Sourcing Capability","authors":"Hongchang Qiao, Chenchang Zhan","doi":"10.1109/CICC53496.2022.9772855","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772855","url":null,"abstract":"The Internet of Things (loT) is developing rapidly, and energy harvesting (EH) provides the power source impetus for it. Still the energy collected from EH is generally underfed, which obliges EH powered modules to achieve low power consumption as much as possible. Hence, the growth of low voltage and low quiescent current designs are pushed forward. For applications with sub-10µA under low-supply (200-300mV), such as sensors for monitoring, SRAM [1], designing an additional regulator is overburdened and one solution is the voltage reference (VR) integrated with output buffer. Whereas the added buffer brings extra area and power consumption (e.g., microwatt), the mismatch substantially degrades the temperature coefficient (TC). Therefore, a sub-nanowatt VR with current sourcing capability is of momentous significance. Besides, supposing that the power consumption of the designed VR is in the order of picowatt, and due to the process restraint, the subsequent gates of MOS transistors connected to the VR output have leakage current of picoampere, it will directly cause the VR to be shut down, needless to mention the microampere loading capability. However, the existing CMOS voltage references (CVRs) hardly source current [2]–[6].","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121227383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772874
Xiaofeng Guo, Run Chen, Rongfeng Xu, Bin Li, Zhenqi Chen
With the increased demand for high data throughput of next-generation wireless communication, pipelined-SAR ADC has become a popular architecture for data conversion due to its superior power efficiency. For 5G/6G wireless communication, near-GHz signal bandwidth requires the residue amplifier (RA) to settle as fast as possible with precise amplification. Previous works [1], [2], [3] have exploited open-loop RAs for high-speed data conversion. However, significant gain error and PVT-related gain variation limit its dynamic range and require gain calibration. Closed-loop RA has been proposed for accurate gain control [4], but its limited bandwidth is not suitable for high-speed applications. In [5], the comparator metastability has been explored to increase the conversion speed in a binary searching SAR topology.
{"title":"A Calibration-Free 13b 625MS/s Tri-State Pipelined-SAR ADC with PVT-Insensitive Inverter-Based Residue Amplifier","authors":"Xiaofeng Guo, Run Chen, Rongfeng Xu, Bin Li, Zhenqi Chen","doi":"10.1109/CICC53496.2022.9772874","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772874","url":null,"abstract":"With the increased demand for high data throughput of next-generation wireless communication, pipelined-SAR ADC has become a popular architecture for data conversion due to its superior power efficiency. For 5G/6G wireless communication, near-GHz signal bandwidth requires the residue amplifier (RA) to settle as fast as possible with precise amplification. Previous works [1], [2], [3] have exploited open-loop RAs for high-speed data conversion. However, significant gain error and PVT-related gain variation limit its dynamic range and require gain calibration. Closed-loop RA has been proposed for accurate gain control [4], but its limited bandwidth is not suitable for high-speed applications. In [5], the comparator metastability has been explored to increase the conversion speed in a binary searching SAR topology.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122617173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772732
J. Hasler
This discussion reviews the current capabilities of large-scale Field Programmable Analog Arrays (FPAA) and considers the future potential of these SoC FPAA devices, including techniques to enable ubiquitous use of FPAA devices similar to FPGA devices. Today's FPAA devices include integrated analog and digital fabric as well as specialized processors and infrastructure, becoming a platform of mixed-signal development as well as analog-enabled computing. Investigating the scaling of FPAA devices shows the potential fine-grain capabilities through analyzing the tradeoff between granularity and flexibility as well as the opportunities through CMOS scaling.
{"title":"The Rise of SoC FPAA Devices","authors":"J. Hasler","doi":"10.1109/CICC53496.2022.9772732","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772732","url":null,"abstract":"This discussion reviews the current capabilities of large-scale Field Programmable Analog Arrays (FPAA) and considers the future potential of these SoC FPAA devices, including techniques to enable ubiquitous use of FPAA devices similar to FPGA devices. Today's FPAA devices include integrated analog and digital fabric as well as specialized processors and infrastructure, becoming a platform of mixed-signal development as well as analog-enabled computing. Investigating the scaling of FPAA devices shows the potential fine-grain capabilities through analyzing the tradeoff between granularity and flexibility as well as the opportunities through CMOS scaling.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"328 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122711606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772816
H. Chandrakumar, T. Brown, D. Frolov, Zinia Tuli, I-Lun Huang, S. Rami
With the ever-increasing demand for higher throughput in communication systems, data converters require higher conversion rates at moderate resolutions (> 7b) while remaining power efficient. This work presents a 9b, 50GS/s current-steering DAC that achieves a worst case 48.2dBc SFDR in the Nyquist band. A dynamically boosted fast-switching current-cell, 16:1 serializers and AC-coupled coil-less CMOS clock buffers enable a sub-DAC rate of 25GS/s that reduce the interleaving factor to only two. This greatly simplifies calibration and limits the timing-critical areas of the system to the final 2:1 analog multiplexer (MUX). The topology of the current-cell also enables reduced supply voltage for the digital blocks, which leads to a significant reduction in power consumption.
{"title":"A 48dB-SFDR, 43dB-SNDR, 50GS/s 9-bit 2x-interleaved Nyquist DAC in Intel 16","authors":"H. Chandrakumar, T. Brown, D. Frolov, Zinia Tuli, I-Lun Huang, S. Rami","doi":"10.1109/CICC53496.2022.9772816","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772816","url":null,"abstract":"With the ever-increasing demand for higher throughput in communication systems, data converters require higher conversion rates at moderate resolutions (> 7b) while remaining power efficient. This work presents a 9b, 50GS/s current-steering DAC that achieves a worst case 48.2dBc SFDR in the Nyquist band. A dynamically boosted fast-switching current-cell, 16:1 serializers and AC-coupled coil-less CMOS clock buffers enable a sub-DAC rate of 25GS/s that reduce the interleaving factor to only two. This greatly simplifies calibration and limits the timing-critical areas of the system to the final 2:1 analog multiplexer (MUX). The topology of the current-cell also enables reduced supply voltage for the digital blocks, which leads to a significant reduction in power consumption.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122864526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772856
J. Velamala, Siang-jhih Sean Wu, P. Penmatsa, K. Shen, D. Johnston, R. Parker
Integrated circuit security applications often require a unique ID on each die that can be read reliably over the lifetime of the product [1]. Physical Unclonable Functions (PUFs) are low-cost cryptographic primitives used to generate unique, stable, and secure IDs for device authentication and secure communication [2] [3]. PUFs rely on random process variations inherent in the manufacturing flow making it impossible to predict, or clone chip IDs, providing a high level of security and tamper resistance [1]. 1kb PUF arrays are fabricated in Intel's 7nm FinFET technology featuring (i) a hybrid-SRAM based PUF [1] [2] and (ii) a new NFET only PUF with a novel stress operation exploiting Hot Carrier Injection (HCI).
{"title":"PVT Tolerant Zero Bit-Error-Rate Physical Unclonable Function Exploiting Hot Carrier Injection Aging in 7nm FinFET Technology","authors":"J. Velamala, Siang-jhih Sean Wu, P. Penmatsa, K. Shen, D. Johnston, R. Parker","doi":"10.1109/CICC53496.2022.9772856","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772856","url":null,"abstract":"Integrated circuit security applications often require a unique ID on each die that can be read reliably over the lifetime of the product [1]. Physical Unclonable Functions (PUFs) are low-cost cryptographic primitives used to generate unique, stable, and secure IDs for device authentication and secure communication [2] [3]. PUFs rely on random process variations inherent in the manufacturing flow making it impossible to predict, or clone chip IDs, providing a high level of security and tamper resistance [1]. 1kb PUF arrays are fabricated in Intel's 7nm FinFET technology featuring (i) a hybrid-SRAM based PUF [1] [2] and (ii) a new NFET only PUF with a novel stress operation exploiting Hot Carrier Injection (HCI).","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128146167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772799
Marcel Runge, Julius Edler, Dario Schmock, Tobias Kaiser, F. Gerfers
Wide-band, power-efficient continuous-time (CT) $DeltaSigma$ modulators have become the core building block for modern wireless receiver architectures. In particular, the multi-bit $DeltaSigma$ modulator topology is very popular compared to the single-bit variant, as this not only enables a reduced oversampling ratio (OSR) for a given bandwidth and SNDR but also leads to significant power savings. However, as multi-bit DACs are inherently non-linear, these errors fundamentally limit the linearity of the entire modulator. State of the art analog correction concepts [1] compensate multi-bit DAC errors by placing an auxiliary DAC (AUXDAC) in parallel to the main feedback DAC. The AUXDAC operates at full modulator clock speed, giving rise to four major drawbacks highlighted in Fig. 1. This work proposes a body-bias DAC calibration scheme that overcomes all these drawbacks by utilizing the transistor back gate as a control node to correct static DAC unit cell mismatch to 15bit accuracy.
{"title":"A 30-MHz BW 74.6-dB SNDR 92-dB SFDR CT ΔΣ Modulator with Active Body-Bias DAC Calibration in 22nm FDSOI CMOS","authors":"Marcel Runge, Julius Edler, Dario Schmock, Tobias Kaiser, F. Gerfers","doi":"10.1109/CICC53496.2022.9772799","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772799","url":null,"abstract":"Wide-band, power-efficient continuous-time (CT) $DeltaSigma$ modulators have become the core building block for modern wireless receiver architectures. In particular, the multi-bit $DeltaSigma$ modulator topology is very popular compared to the single-bit variant, as this not only enables a reduced oversampling ratio (OSR) for a given bandwidth and SNDR but also leads to significant power savings. However, as multi-bit DACs are inherently non-linear, these errors fundamentally limit the linearity of the entire modulator. State of the art analog correction concepts [1] compensate multi-bit DAC errors by placing an auxiliary DAC (AUXDAC) in parallel to the main feedback DAC. The AUXDAC operates at full modulator clock speed, giving rise to four major drawbacks highlighted in Fig. 1. This work proposes a body-bias DAC calibration scheme that overcomes all these drawbacks by utilizing the transistor back gate as a control node to correct static DAC unit cell mismatch to 15bit accuracy.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134409754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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