Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772842
S. Levantino
Whether employed as local oscillators in wireless communications or radar systems, or as clock generators in data converters, high-performance frequency synthesizers are essential elements of any advanced electronic systems. In wireless applications, highly spectral-efficient modulations, such as quadrature amplitude modulation with large number of symbols (256 or above), enables higher bit rate at same bandwidth occupation, at the price of tighter constraints on the error-vector magnitude. This demands for an ultra-low jitter local oscillator (LO). For instance, the 5G new radio for cellular communications at frequencies around 28GHz calls for an integrated phase noise well below -36dBc, translating into an absolute rms jitter well below 90fs, over all the operating conditions. Similar performance is also required to the clock of high-speed analog-to-digital converters not to deteriorate their signal-to-noise ratio (SNR). An SNR of 62dB (i.e., 10 equivalent bits) at 1GHz bandwidth requires a clock jitter well below 130fs.
{"title":"Recent Advances in High-Performance Frequency Synthesizer Design","authors":"S. Levantino","doi":"10.1109/CICC53496.2022.9772842","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772842","url":null,"abstract":"Whether employed as local oscillators in wireless communications or radar systems, or as clock generators in data converters, high-performance frequency synthesizers are essential elements of any advanced electronic systems. In wireless applications, highly spectral-efficient modulations, such as quadrature amplitude modulation with large number of symbols (256 or above), enables higher bit rate at same bandwidth occupation, at the price of tighter constraints on the error-vector magnitude. This demands for an ultra-low jitter local oscillator (LO). For instance, the 5G new radio for cellular communications at frequencies around 28GHz calls for an integrated phase noise well below -36dBc, translating into an absolute rms jitter well below 90fs, over all the operating conditions. Similar performance is also required to the clock of high-speed analog-to-digital converters not to deteriorate their signal-to-noise ratio (SNR). An SNR of 62dB (i.e., 10 equivalent bits) at 1GHz bandwidth requires a clock jitter well below 130fs.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121279830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772845
H. Hashemi
In the early 20th century, the reflection of electromagnetic waves emitted by ships from the metallic frame of other nearby ships was used as early collision warning system in poor visibility weather condition. In subsequent decades, the importance of detecting incoming bombers motivated the advancement of radio detection and ranging (radar) systems where the roundtrip time of a short pulse was used to find the target distance whereas the direction of the antenna was used to localize the target. Later advancements in phased array technology replaced the mechanically scanned antenna with electronically scanned versions enabling faster target localization, and ultimately, tracking multiple concurrent targets. Light detection and ranging (Iidar), initially referred to as laser radar, was developed shortly after the invention of lasers in the $1960mathrm{s}$. The primary early applications were in metrology, military, and scientific discoveries and research. There has been a recent commercial interest in lidar for its potential application in advanced driver-assistance systems (ADAS) and self-driving cars.
{"title":"A Review of Silicon Photonics LiDAR","authors":"H. Hashemi","doi":"10.1109/CICC53496.2022.9772845","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772845","url":null,"abstract":"In the early 20th century, the reflection of electromagnetic waves emitted by ships from the metallic frame of other nearby ships was used as early collision warning system in poor visibility weather condition. In subsequent decades, the importance of detecting incoming bombers motivated the advancement of radio detection and ranging (radar) systems where the roundtrip time of a short pulse was used to find the target distance whereas the direction of the antenna was used to localize the target. Later advancements in phased array technology replaced the mechanically scanned antenna with electronically scanned versions enabling faster target localization, and ultimately, tracking multiple concurrent targets. Light detection and ranging (Iidar), initially referred to as laser radar, was developed shortly after the invention of lasers in the $1960mathrm{s}$. The primary early applications were in metrology, military, and scientific discoveries and research. There has been a recent commercial interest in lidar for its potential application in advanced driver-assistance systems (ADAS) and self-driving cars.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121441741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772781
Bo Zhang, Jyotishman Saikia, Jian Meng, Dewei Wang, Soon-Chan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae-sun Seo, Mingoo Seok
Capacitor-based in-memory computing (IMC) SRAM has recently gained significant attention as it achieves high energy-efficiency for deep convolutional neural networks (DCNN) and robustness against PVT variations [1], [3], [7], [8]. To further improve energy-efficiency and robustness, we identify two places of bottleneck in prior capacitive IMC works, namely (i) input drivers (or digital-to-analog converters, DACs) which charge and discharge various capacitors, and (ii) analog-to-digital converters (ADCs) which convert analog voltage/current signals into digital values.
{"title":"A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks","authors":"Bo Zhang, Jyotishman Saikia, Jian Meng, Dewei Wang, Soon-Chan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae-sun Seo, Mingoo Seok","doi":"10.1109/CICC53496.2022.9772781","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772781","url":null,"abstract":"Capacitor-based in-memory computing (IMC) SRAM has recently gained significant attention as it achieves high energy-efficiency for deep convolutional neural networks (DCNN) and robustness against PVT variations [1], [3], [7], [8]. To further improve energy-efficiency and robustness, we identify two places of bottleneck in prior capacitive IMC works, namely (i) input drivers (or digital-to-analog converters, DACs) which charge and discharge various capacitors, and (ii) analog-to-digital converters (ADCs) which convert analog voltage/current signals into digital values.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"179 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122454858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772810
H. Sumbul, Tony F. Wu, Yuecheng Li, Syed Shakib Sarwar, W. Koven, Eli Murphy-Trotzky, Xingxing Cai, E. Ansari, D. Morris, Huichu Liu, Doyun Kim, E. Beigné
Augmented Reality / Virtual Reality (AR/VR) devices aim to connect people in the Metaverse with photorealistic virtual avatars, referred to as “Codec Avatars”. Delivering a high visual performance for Codec Avatar workloads, however, is a challenging task for mobile SoCs as AR/VR devices have limited power and form factor constraints. On-device, local, near-sensor processing provides the best system-level energy-efficiency and enables strong security and privacy features in the long run. In this work, we present a custom-built, prototype small-scale mobile SoC that achieves energy-efficient performance for running eye gaze extraction of the Codec Avatar model. The test-chip, fabricated in 7nm technology node, features a Neural Network (NN) accelerator consisting of a 1024 Multiply-Accumulate (MAC) array, 2MB on-chip SRAM, and a 32bit RISC-V CPU. The featured test-chip is integrated on a prototype mobile VR headset to run the Codec Avatar application. This work aims to show the full stack design considerations of system-level integration, hardware-aware model customization, and circuit-level acceleration to meet the challenging mobile AR/VR SoC specifications for a Codec Avatar demonstration. By re-architecting the Convolutional NN (CNN) based eye gaze extraction model and tailoring it for the hardware, the entire model fits on the chip to mitigate system-level energy and latency cost of off-chip memory accesses. By efficiently accelerating the convolution operation at the circuit-level, the presented prototype SoC achieves 30 frames per second performance with low-power consumption at low form factors. With the full-stack design considerations presented in this work, the featured test-chip consumes 22.7mW power to run inference on the entire CNN model in 16.5ms from input to output for a single sensor image. As a result, the test-chip achieves 375 µJ/frame/eye energy-efficiency within a 2.56 mm2 silicon area.
{"title":"System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars","authors":"H. Sumbul, Tony F. Wu, Yuecheng Li, Syed Shakib Sarwar, W. Koven, Eli Murphy-Trotzky, Xingxing Cai, E. Ansari, D. Morris, Huichu Liu, Doyun Kim, E. Beigné","doi":"10.1109/CICC53496.2022.9772810","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772810","url":null,"abstract":"Augmented Reality / Virtual Reality (AR/VR) devices aim to connect people in the Metaverse with photorealistic virtual avatars, referred to as “Codec Avatars”. Delivering a high visual performance for Codec Avatar workloads, however, is a challenging task for mobile SoCs as AR/VR devices have limited power and form factor constraints. On-device, local, near-sensor processing provides the best system-level energy-efficiency and enables strong security and privacy features in the long run. In this work, we present a custom-built, prototype small-scale mobile SoC that achieves energy-efficient performance for running eye gaze extraction of the Codec Avatar model. The test-chip, fabricated in 7nm technology node, features a Neural Network (NN) accelerator consisting of a 1024 Multiply-Accumulate (MAC) array, 2MB on-chip SRAM, and a 32bit RISC-V CPU. The featured test-chip is integrated on a prototype mobile VR headset to run the Codec Avatar application. This work aims to show the full stack design considerations of system-level integration, hardware-aware model customization, and circuit-level acceleration to meet the challenging mobile AR/VR SoC specifications for a Codec Avatar demonstration. By re-architecting the Convolutional NN (CNN) based eye gaze extraction model and tailoring it for the hardware, the entire model fits on the chip to mitigate system-level energy and latency cost of off-chip memory accesses. By efficiently accelerating the convolution operation at the circuit-level, the presented prototype SoC achieves 30 frames per second performance with low-power consumption at low form factors. With the full-stack design considerations presented in this work, the featured test-chip consumes 22.7mW power to run inference on the entire CNN model in 16.5ms from input to output for a single sensor image. As a result, the test-chip achieves 375 µJ/frame/eye energy-efficiency within a 2.56 mm2 silicon area.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126114725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772778
Zhiyong Li, Sangjin Kim, Dongseok Im, Donghyeon Han, H. Yoo
With the rise of contactless communication and streaming services, Super-resolution (SR) in mobile devices has become one of the most important image processing technologies. Also, The popularity of high-end Application Processor (AP) and high resolution display in mobile drives the development of the lightweight mobile SR-CNNs [1], [2], which show the high reconstruction quality. However, the large size and wide dynamic range of both images and intermediate feature maps in CNN hidden layers pose challenges for mobile platforms. Constraints from the limited power $(< 100text{mW})$ and shared bandwidth $(< 2text{GB}/mathrm{s})$ on mobile platform, a low power and energy-efficient architecture is required.
{"title":"An 0.92 mJ/frame High-quality FHD Super-resolution Mobile Accelerator SoC with Hybrid-precision and Energy-efficient Cache","authors":"Zhiyong Li, Sangjin Kim, Dongseok Im, Donghyeon Han, H. Yoo","doi":"10.1109/CICC53496.2022.9772778","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772778","url":null,"abstract":"With the rise of contactless communication and streaming services, Super-resolution (SR) in mobile devices has become one of the most important image processing technologies. Also, The popularity of high-end Application Processor (AP) and high resolution display in mobile drives the development of the lightweight mobile SR-CNNs [1], [2], which show the high reconstruction quality. However, the large size and wide dynamic range of both images and intermediate feature maps in CNN hidden layers pose challenges for mobile platforms. Constraints from the limited power $(< 100text{mW})$ and shared bandwidth $(< 2text{GB}/mathrm{s})$ on mobile platform, a low power and energy-efficient architecture is required.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121612385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-03-14DOI: 10.48550/arXiv.2203.07006
A. Basu, C. Frenkel, Lei Deng, Xueyong Zhang
The rapid growth of deep learning, spurred by its successes in various fields ranging from face recognition [1] to game playing [2], has also triggered a growing interest in the design of specialized hardware accelerators to support these algorithms. This specialized hardware targets one of two categories-either operating in datacenters or on mobile devices at the network edge. While energy efficiency is important in both cases, the need is extremely stringent in the latter class of applications due to limited battery life. Several techniques have been used in the past to improve the energy efficiency of these accelerators [3], including reducing off-chip DRAM access, managing data flow across processing elements as well as in-memory computing (IMC) by exploiting analog processing of data within digital memory arrays [4].
{"title":"Spiking Neural Network Integrated Circuits: A Review of Trends and Future Directions","authors":"A. Basu, C. Frenkel, Lei Deng, Xueyong Zhang","doi":"10.48550/arXiv.2203.07006","DOIUrl":"https://doi.org/10.48550/arXiv.2203.07006","url":null,"abstract":"The rapid growth of deep learning, spurred by its successes in various fields ranging from face recognition [1] to game playing [2], has also triggered a growing interest in the design of specialized hardware accelerators to support these algorithms. This specialized hardware targets one of two categories-either operating in datacenters or on mobile devices at the network edge. While energy efficiency is important in both cases, the need is extremely stringent in the latter class of applications due to limited battery life. Several techniques have been used in the past to improve the energy efficiency of these accelerators [3], including reducing off-chip DRAM access, managing data flow across processing elements as well as in-memory computing (IMC) by exploiting analog processing of data within digital memory arrays [4].","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127183668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-24DOI: 10.48550/arXiv.2203.01413
Xueyong Zhang, A. Basu
The bio-inspired asynchronous event-based neuromorphic vision sensors (NVS) are introducing a paradigm shift in visual information sensing and processing [1]. The feature of event-driven operation makes it ideal for low-power operation in the Internet-of-Things scenario such as traffic monitoring. However, the inherent noise in the sensor causes redundant wake-up operation and reduces tracking performance [2]. Energy efficient in-memory computing (IMC) based denoise operation allows blank-frame detection to gain 2X energy savings. Further energy savings can be obtained by exploiting spatial redundancy-objects usually occupy a small part ~5% of the frame in traffic monitoring [3]. Hence, region proposal (RP) is required to detect the region of interests (ROIs) in a valid frame along with their bounding box location coordinates, as shown in Fig. 1. For binary images, the conventional connected component labeling (CCL) algorithm [4] can propose ROIs by raster scanning the whole frame, but leads to longer search time and higher computing energy due to von Neumann operation. The promising IMC approach [3] has high energy efficiency, but has limited accuracy due to a simple algorithm constrained by in-memory operations as well as object fragmentation due to smooth surfaces (e.g. car windows) that do not generate events. In this work, we present a hybrid memory bit cell-collocated SRAM and DRAM (CRAM) consisting of 11 transistors for IMC-based image restoration (IR) and RP. The proposed CRAM supports image storage in SRAM and DRAM modes, denoise and region filling in diffusion mode and RP algorithm in projection mode.
{"title":"A 915–1220 TOPS/W Hybrid In-Memory Computing based Image Restoration and Region Proposal Integrated Circuit for Neuromorphic Vision Sensors in 65nm CMOS","authors":"Xueyong Zhang, A. Basu","doi":"10.48550/arXiv.2203.01413","DOIUrl":"https://doi.org/10.48550/arXiv.2203.01413","url":null,"abstract":"The bio-inspired asynchronous event-based neuromorphic vision sensors (NVS) are introducing a paradigm shift in visual information sensing and processing [1]. The feature of event-driven operation makes it ideal for low-power operation in the Internet-of-Things scenario such as traffic monitoring. However, the inherent noise in the sensor causes redundant wake-up operation and reduces tracking performance [2]. Energy efficient in-memory computing (IMC) based denoise operation allows blank-frame detection to gain 2X energy savings. Further energy savings can be obtained by exploiting spatial redundancy-objects usually occupy a small part ~5% of the frame in traffic monitoring [3]. Hence, region proposal (RP) is required to detect the region of interests (ROIs) in a valid frame along with their bounding box location coordinates, as shown in Fig. 1. For binary images, the conventional connected component labeling (CCL) algorithm [4] can propose ROIs by raster scanning the whole frame, but leads to longer search time and higher computing energy due to von Neumann operation. The promising IMC approach [3] has high energy efficiency, but has limited accuracy due to a simple algorithm constrained by in-memory operations as well as object fragmentation due to smooth surfaces (e.g. car windows) that do not generate events. In this work, we present a hybrid memory bit cell-collocated SRAM and DRAM (CRAM) consisting of 11 transistors for IMC-based image restoration (IR) and RP. The proposed CRAM supports image storage in SRAM and DRAM modes, denoise and region filling in diffusion mode and RP algorithm in projection mode.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-02-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116671932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-18DOI: 10.1109/CICC53496.2022.9772870
Qiang Liu, Zishen Wan, Bo Yu, Weizhuang Liu, Shaoshan Liu, A. Raychowdhury
A robot usually localizes itself in an environment by estimating the collection of its position and rotation states, while constructing a map of unknown surroundings, giving rise to the notion of Simultaneous Localization and Mapping (SLAM). SLAM is a fundamental kernel in autonomous machines at all computing scales, from drones, AR, VR to self-driving cars. Principled mathematical solutions for SLAM involve filtering-based or non-linear optimization-based (Fig. 1a), where the latter recently shows higher robustness but with intensive computation. Prior ASICs [1], [2] and FPGAs [3], [4], [5] have accelerated SLAM on hardware, but they usually target one specific design. In this work, we present a runtime-reconfigurable FPGA accelerator for robotic localization tasks. We exploit SLAM-specific data locality, sparsity, reuse, and parallelism, and achieve >5x performance improvement over the state-of-the-art. Especially, our design is reconfigurable at runtime according to the environment and platform to save power while sustaining accuracy and performance.
{"title":"An Energy-Efficient and Runtime-Reconfigurable FPGA-Based Accelerator for Robotic Localization Systems","authors":"Qiang Liu, Zishen Wan, Bo Yu, Weizhuang Liu, Shaoshan Liu, A. Raychowdhury","doi":"10.1109/CICC53496.2022.9772870","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772870","url":null,"abstract":"A robot usually localizes itself in an environment by estimating the collection of its position and rotation states, while constructing a map of unknown surroundings, giving rise to the notion of Simultaneous Localization and Mapping (SLAM). SLAM is a fundamental kernel in autonomous machines at all computing scales, from drones, AR, VR to self-driving cars. Principled mathematical solutions for SLAM involve filtering-based or non-linear optimization-based (Fig. 1a), where the latter recently shows higher robustness but with intensive computation. Prior ASICs [1], [2] and FPGAs [3], [4], [5] have accelerated SLAM on hardware, but they usually target one specific design. In this work, we present a runtime-reconfigurable FPGA accelerator for robotic localization tasks. We exploit SLAM-specific data locality, sparsity, reuse, and parallelism, and achieve >5x performance improvement over the state-of-the-art. Especially, our design is reconfigurable at runtime according to the environment and platform to save power while sustaining accuracy and performance.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":" 47","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-02-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113951528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-01-19DOI: 10.1109/CICC53496.2022.9772859
A. Ghosh, J. M. B. Mera, A. Karmakar, D. Das, Santosh K. Ghosh, I. Verbauwhede, Shreyas Sen
The arrival of large-scale quantum computers will break the security assurances of our current public-key cryptography. National Institute of Standard & Technology (NIST) is currently running a multi-year-long standardization procedure to select quantum-safe or postquantum cryptographic schemes to be used in the future. Energy efficiency is an important criterion in the selection process. This paper presents the first Silicon verified ASIC implementation for Saber (LWR algorithm as proposed in [1], [2]), a NIST PQC Round 3 finalist candidate in the key-encapsulation mechanism (KEM) category. Fig. 1 briefly describes the learning with rounding (LWR) problem, which is hard to solve even in the presence of large quantum computers due to the noise generated from rounding. IC features are tabulated in Fig. 1. which also shows a simplified version of the Saber KEM scheme to establish a secret key between two communicating parties Alice and Bob. Due to learning with rounding, secret $s$ is hard to guess based on publicly available data as shown in Fig. 1.
{"title":"A 334uW 0.158mm2 Saber Learning with Rounding based Post-Quantum Crypto Accelerator","authors":"A. Ghosh, J. M. B. Mera, A. Karmakar, D. Das, Santosh K. Ghosh, I. Verbauwhede, Shreyas Sen","doi":"10.1109/CICC53496.2022.9772859","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772859","url":null,"abstract":"The arrival of large-scale quantum computers will break the security assurances of our current public-key cryptography. National Institute of Standard & Technology (NIST) is currently running a multi-year-long standardization procedure to select quantum-safe or postquantum cryptographic schemes to be used in the future. Energy efficiency is an important criterion in the selection process. This paper presents the first Silicon verified ASIC implementation for Saber (LWR algorithm as proposed in [1], [2]), a NIST PQC Round 3 finalist candidate in the key-encapsulation mechanism (KEM) category. Fig. 1 briefly describes the learning with rounding (LWR) problem, which is hard to solve even in the presence of large quantum computers due to the noise generated from rounding. IC features are tabulated in Fig. 1. which also shows a simplified version of the Saber KEM scheme to establish a secret key between two communicating parties Alice and Bob. Due to learning with rounding, secret $s$ is hard to guess based on publicly available data as shown in Fig. 1.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116295886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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