Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772797
M. Beikmirza, Yiyu Shen, L. D. Vreede, M. Alavi
To support wideband complex modulated signals and comply with the stringent requirements of modern communication standards in an energy-efficient manner, recently, digital transmitters (DTXs) have been explored to fully benefit from the high-speed switching and integration capabilities of nanoscale CMOS technologies [1]–[5]. These DTXs are primarily exploiting a polar or Cartesian architecture. In a polar DTX [1], [2], two eigenvectors of amplitude (p) and phase $(phi)$ are generated from the in-phase (I) and quadrature (Q) baseband signals using non-linear coordinate rotation transformations (i.e., CORDIC). Provided that $rho$ is constant, the achievable drain efficiency (DE) is constant (Fig. 1 top). However, polar $text{DTXs}$ cannot manage large modulation bandwidth due to their non-linear $mathrm{I}/mathrm{Q}$ to $rho/phi$ conversion. Moreover, their phase and amplitude paths must recombine at the output stage without any delay mismatch to maintain linear operation. In contrast, Cartesian DTX variants can handle signals with large modulation bandwidth [3]. Nevertheless, their DE is lower than their polar counterparts owing to the linear combination of orthogonal I/Q vectors, yielding a 3-dB worst-case output power loss at the orthogonal (I/Q) axes. Alternatively, a multi-phase operation can be utilized that compromises polar and Cartesian features by mapping the I/Q signals into two non-orthogonal basis vectors with 45° relative phase difference and magnitudes of $mathrm{I}_{text{MP}}=mathrm{I}-mathrm{Q}$, QMP $=sqrt{2}mathrm{Q}$ [4]. This architecture inherits the advantages of the cartesian DTX, such as wideband operation, symmetrical, and synchronized $mathrm{I} /mathrm{Q}$ paths along with a DE behavior that imitates the polar case. This paper presents a multi-mode DTX that uses both Cartesian and multi-phase operation modes to target applications requiring large modulation bandwidth, decent spectral purity and average efficiency.
{"title":"A 1-to-4GHz Multi-Mode Digital Transmitter in 40nm CMOS Supporting 200MHz 1024-QAM OFDM signals with more than 23dBm/66% Peak Power/Drain Efficiency","authors":"M. Beikmirza, Yiyu Shen, L. D. Vreede, M. Alavi","doi":"10.1109/CICC53496.2022.9772797","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772797","url":null,"abstract":"To support wideband complex modulated signals and comply with the stringent requirements of modern communication standards in an energy-efficient manner, recently, digital transmitters (DTXs) have been explored to fully benefit from the high-speed switching and integration capabilities of nanoscale CMOS technologies [1]–[5]. These DTXs are primarily exploiting a polar or Cartesian architecture. In a polar DTX [1], [2], two eigenvectors of amplitude (p) and phase $(phi)$ are generated from the in-phase (I) and quadrature (Q) baseband signals using non-linear coordinate rotation transformations (i.e., CORDIC). Provided that $rho$ is constant, the achievable drain efficiency (DE) is constant (Fig. 1 top). However, polar $text{DTXs}$ cannot manage large modulation bandwidth due to their non-linear $mathrm{I}/mathrm{Q}$ to $rho/phi$ conversion. Moreover, their phase and amplitude paths must recombine at the output stage without any delay mismatch to maintain linear operation. In contrast, Cartesian DTX variants can handle signals with large modulation bandwidth [3]. Nevertheless, their DE is lower than their polar counterparts owing to the linear combination of orthogonal I/Q vectors, yielding a 3-dB worst-case output power loss at the orthogonal (I/Q) axes. Alternatively, a multi-phase operation can be utilized that compromises polar and Cartesian features by mapping the I/Q signals into two non-orthogonal basis vectors with 45° relative phase difference and magnitudes of $mathrm{I}_{text{MP}}=mathrm{I}-mathrm{Q}$, QMP $=sqrt{2}mathrm{Q}$ [4]. This architecture inherits the advantages of the cartesian DTX, such as wideband operation, symmetrical, and synchronized $mathrm{I} /mathrm{Q}$ paths along with a DE behavior that imitates the polar case. This paper presents a multi-mode DTX that uses both Cartesian and multi-phase operation modes to target applications requiring large modulation bandwidth, decent spectral purity and average efficiency.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134577059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772869
Xin Ming, Zhikang Lin, Tian-yi Sun, Yao Qin, Yuan-Yuan Liu, Chun-wang Zhuang, Zhaoji Li, Bo Zhang
For future automotive applications, the growing demand for tiny, high power density and fast dynamic response is putting more pressure on power converters, where Gallium nitride FETs have proven to be promising devices [1]. However, for high conversion-ratio GaN power converters, the floating power rail control of half-bridge gate driver and low FOM/high-reliability level shifter (LS) pose a big challenge when increasing switching speed dV/dt and frequency (smaller Ton, min and Toff, min). Charging saturation and over-voltage protection of the bootstrap power supply, as well as common-mode transient immunity (CMTI)/transmission delay/power consumption of LS may introduce efficiency degradation and significant reliability issues.
{"title":"An Up to 10MHz 6.8% Minimum Duty Ratio GaN Driver with Dual-MOS-Switches Bootstrap and Adaptive Short-Pulse Based High-CMTI Level Shifter Achieving 6.05% Efficiency Improvement","authors":"Xin Ming, Zhikang Lin, Tian-yi Sun, Yao Qin, Yuan-Yuan Liu, Chun-wang Zhuang, Zhaoji Li, Bo Zhang","doi":"10.1109/CICC53496.2022.9772869","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772869","url":null,"abstract":"For future automotive applications, the growing demand for tiny, high power density and fast dynamic response is putting more pressure on power converters, where Gallium nitride FETs have proven to be promising devices [1]. However, for high conversion-ratio GaN power converters, the floating power rail control of half-bridge gate driver and low FOM/high-reliability level shifter (LS) pose a big challenge when increasing switching speed dV/dt and frequency (smaller Ton, min and Toff, min). Charging saturation and over-voltage protection of the bootstrap power supply, as well as common-mode transient immunity (CMTI)/transmission delay/power consumption of LS may introduce efficiency degradation and significant reliability issues.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133380916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772843
Mingqiang Guo, Sai-Weng Sin, Liang Qi, Gang Xiao, R. Martins
A SAR ADC comprises only a T/H, a comparator, SAR logics, and a capacitive DAC, thus exhibiting a power-efficient topology with low complexity, low power consumption, and friendly process technology scaling down. Consequently, it has a wide utilization in high-speed applications (like in time-interleaved SARs). Previous works improved the 1b/cycle topology to speed up SAR ADC conversions, leading to multi-bit/cycle [1] and N-bits N-comparators [2] structures. Compared with the above architectures, the conventional 1b/cycle topology still has apparent advantages related to low complexity, less parasitic, and less offset problems. Therefore, currently, the 1b/cycle is still the first choice for the majority of high-speed TI SAR ADCs [3]. The popularization of the high-speed SAR ADC with redundant bit structures can lead to a very short settling time required for the DACs [4]. However, the speed of the SAR is still a bottleneck, especially limited by the digital SAR logic [2].
SAR ADC仅由T/H、比较器、SAR逻辑和电容式DAC组成，因此具有低复杂度、低功耗和友好的工艺技术。因此，它在高速应用(如时间交错sar)中有广泛的应用。先前的工作改进了1b/周期拓扑以加快SAR ADC转换，从而产生了多位/周期[1]和n位n比较器[2]结构。与上述架构相比，传统的1b/cycle拓扑结构在低复杂度、少寄生、少偏移等方面仍然具有明显的优势。因此，目前，1b/周期仍然是大多数高速TI SAR adc的首选[3]。具有冗余位结构的高速SAR ADC的普及可以使dac的建立时间非常短[4]。然而，SAR的速度仍然是一个瓶颈，特别是受到数字SAR逻辑的限制[2]。
{"title":"A 10b 700MS/s single-channel 1b/cycle SAR ADC using a monotonic-specific feedback SAR logic with power-delay-optimized unbalanced N/P-MOS sizing","authors":"Mingqiang Guo, Sai-Weng Sin, Liang Qi, Gang Xiao, R. Martins","doi":"10.1109/CICC53496.2022.9772843","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772843","url":null,"abstract":"A SAR ADC comprises only a T/H, a comparator, SAR logics, and a capacitive DAC, thus exhibiting a power-efficient topology with low complexity, low power consumption, and friendly process technology scaling down. Consequently, it has a wide utilization in high-speed applications (like in time-interleaved SARs). Previous works improved the 1b/cycle topology to speed up SAR ADC conversions, leading to multi-bit/cycle [1] and N-bits N-comparators [2] structures. Compared with the above architectures, the conventional 1b/cycle topology still has apparent advantages related to low complexity, less parasitic, and less offset problems. Therefore, currently, the 1b/cycle is still the first choice for the majority of high-speed TI SAR ADCs [3]. The popularization of the high-speed SAR ADC with redundant bit structures can lead to a very short settling time required for the DACs [4]. However, the speed of the SAR is still a bottleneck, especially limited by the digital SAR logic [2].","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125206584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772833
Kyeongho Eom, Hanyeop Lee, Mi-Hyun Park, Hyung-Min Lee, S. Yang, Jong-chan Choe, Suk-Won Hwang, Young-Woo Suh
Implantable medical devices (IMD) with stimulation system-on-chip (SoC) have been essential techniques for disease treatments and rehabilitations. As neuromuscular stimulation injects a large amount of stimulus energy into the body, its energy efficiency and safety should be carefully considered, which otherwise damages cellular tissues. Conventional current stimulation suffers from large power losses across current sources. Even adopting the adaptive supply voltage, the stimulator efficiency is still limited below 60% [1]. The switched capacitor stimulation (SCS) system charges the capacitor and transfer its charges to the tissue, achieving stimulator efficiency up to 84% [2]–[4]. However, previous SCS systems only operate with AC input voltages directly from wireless power, which can be interrupted in loosely-coupled inductive links. To take advantages of using a rechargeable battery or a supercapacitor for reliable IMD operation, the SCS system that can efficiently operate with both DC and AC inputs is required. Also, more aggressive techniques to further improve stimulator efficiency and efficacy are highly needed.
{"title":"A 92%-Efficiency Inductor-Charging Switched-Capacitor Stimulation System with Level-Adaptive Duty Modulation and Offset Charge Balancing for Muscular Stimulation","authors":"Kyeongho Eom, Hanyeop Lee, Mi-Hyun Park, Hyung-Min Lee, S. Yang, Jong-chan Choe, Suk-Won Hwang, Young-Woo Suh","doi":"10.1109/CICC53496.2022.9772833","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772833","url":null,"abstract":"Implantable medical devices (IMD) with stimulation system-on-chip (SoC) have been essential techniques for disease treatments and rehabilitations. As neuromuscular stimulation injects a large amount of stimulus energy into the body, its energy efficiency and safety should be carefully considered, which otherwise damages cellular tissues. Conventional current stimulation suffers from large power losses across current sources. Even adopting the adaptive supply voltage, the stimulator efficiency is still limited below 60% [1]. The switched capacitor stimulation (SCS) system charges the capacitor and transfer its charges to the tissue, achieving stimulator efficiency up to 84% [2]–[4]. However, previous SCS systems only operate with AC input voltages directly from wireless power, which can be interrupted in loosely-coupled inductive links. To take advantages of using a rechargeable battery or a supercapacitor for reliable IMD operation, the SCS system that can efficiently operate with both DC and AC inputs is required. Also, more aggressive techniques to further improve stimulator efficiency and efficacy are highly needed.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134223201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772803
Jieyu Li, Weifeng He, Bo Zhang, Guanghui He, Jun Yang, Mingoo Seok
Energy-efficient bitcoin mining cores have gained significant attention since the energy cost for computing dominates the mining expenses [1]. Ultra-low-voltage (ULV) digital circuits have emerged as an attractive approach to improve the energy-efficiency. However, they demand a large timing margin for the worst-case process, voltage, and temperature (PVT) variations, undermining a significant portion of energy savings. Recent works, including multi-phase latch pipeline [1], tunable replica circuits [2]–[3], in-situ error detection and correction (EDAC) [4]–[6], and dynamic timing enhancement [7], can reduce the pessimistic margin. However, it is not straightforward to adopt those techniques in mining cores due to their deeply-pipelined architecture (up to 128 stages [1]). For example, to adopt EDAC, the deep pipeline requires inserting many bulky error detectors as it has many critical paths. Our experiment with a 0.3V 28-nm mining core shows >18.9% registers need to be replaced with error detectors, considering 6σ local process variation only. Also, multiple stages can have timing errors simultaneously, making an error correction process (e.g., clock gating [5], VDD boosting [6]) complex and costly.
{"title":"TICA: A 0.3V, Variation-Resilient 64-Stage Deeply-Pipelined Bitcoin Mining Core with Timing Slack Inference and Clock Frequency Adaption","authors":"Jieyu Li, Weifeng He, Bo Zhang, Guanghui He, Jun Yang, Mingoo Seok","doi":"10.1109/CICC53496.2022.9772803","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772803","url":null,"abstract":"Energy-efficient bitcoin mining cores have gained significant attention since the energy cost for computing dominates the mining expenses [1]. Ultra-low-voltage (ULV) digital circuits have emerged as an attractive approach to improve the energy-efficiency. However, they demand a large timing margin for the worst-case process, voltage, and temperature (PVT) variations, undermining a significant portion of energy savings. Recent works, including multi-phase latch pipeline [1], tunable replica circuits [2]–[3], in-situ error detection and correction (EDAC) [4]–[6], and dynamic timing enhancement [7], can reduce the pessimistic margin. However, it is not straightforward to adopt those techniques in mining cores due to their deeply-pipelined architecture (up to 128 stages [1]). For example, to adopt EDAC, the deep pipeline requires inserting many bulky error detectors as it has many critical paths. Our experiment with a 0.3V 28-nm mining core shows >18.9% registers need to be replaced with error detectors, considering 6σ local process variation only. Also, multiple stages can have timing errors simultaneously, making an error correction process (e.g., clock gating [5], VDD boosting [6]) complex and costly.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132379694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772817
Naresh R Shanbhag, Saion K. Roy
Since its inception in 2014 [1], the modern version of in-memory computing (IMC) has become an active area of research in integrated circuit design globally for realizing artificial intelligence and machine learning workloads. Since 2018, > 40 IMC-related papers have been published in top circuit design conferences demonstrating significant reductions (>20X) in energy over their digital counterparts especially at the bank-level. Today, bank-level IMC designs have matured but it is not clear what the limiting factors are. This lack of clarity is due to multiple reasons including: 1) the conceptual complexity of IMCs due to its full-stack (devices-to-systems) nature, 2) the presence of a fundamental energy-efficiency vs. compute SNR trade-off due to its analog computations, and 3) the statistical nature of machine learning workloads. The absence of a rigorous benchmarking methodology for IMCs - a problem facing machine learning ICs in general [2] - further obfuscates the underlying trade-offs. As a result, it has become difficult to evaluate the novelty of IMC-related ideas being proposed and therefore gauge the true progress in this exciting field.
{"title":"Comprehending In-memory Computing Trends via Proper Benchmarking","authors":"Naresh R Shanbhag, Saion K. Roy","doi":"10.1109/CICC53496.2022.9772817","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772817","url":null,"abstract":"Since its inception in 2014 [1], the modern version of in-memory computing (IMC) has become an active area of research in integrated circuit design globally for realizing artificial intelligence and machine learning workloads. Since 2018, > 40 IMC-related papers have been published in top circuit design conferences demonstrating significant reductions (>20X) in energy over their digital counterparts especially at the bank-level. Today, bank-level IMC designs have matured but it is not clear what the limiting factors are. This lack of clarity is due to multiple reasons including: 1) the conceptual complexity of IMCs due to its full-stack (devices-to-systems) nature, 2) the presence of a fundamental energy-efficiency vs. compute SNR trade-off due to its analog computations, and 3) the statistical nature of machine learning workloads. The absence of a rigorous benchmarking methodology for IMCs - a problem facing machine learning ICs in general [2] - further obfuscates the underlying trade-offs. As a result, it has become difficult to evaluate the novelty of IMC-related ideas being proposed and therefore gauge the true progress in this exciting field.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132421412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772844
M. Rodwell, Ahmed S. H. Ahmed, M. Seo, Utku Soylu, A. Alizadeh, Navid Hosseinzadeh
100–300 GHz wireless systems can provide very high data rates per signal beam, and, given the short wavelengths, even compact arrays can contain many elements, and hence can simultaneously transmit, in the same frequency band, many simultaneous independent signal beams to further greatly increase capacity. We will describe representative system designs, including wireless hubs and backhaul links using massive spatial multiplexing, plus imaging radar systems, evaluate their feasible performance, and identify the key challenges in implementation, including transistor and IC performance, array physical design, digital beam former complexity, and systems cost.
{"title":"IC and Array Technologies for 100-300GHz Wireless","authors":"M. Rodwell, Ahmed S. H. Ahmed, M. Seo, Utku Soylu, A. Alizadeh, Navid Hosseinzadeh","doi":"10.1109/CICC53496.2022.9772844","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772844","url":null,"abstract":"100–300 GHz wireless systems can provide very high data rates per signal beam, and, given the short wavelengths, even compact arrays can contain many elements, and hence can simultaneously transmit, in the same frequency band, many simultaneous independent signal beams to further greatly increase capacity. We will describe representative system designs, including wireless hubs and backhaul links using massive spatial multiplexing, plus imaging radar systems, evaluate their feasible performance, and identify the key challenges in implementation, including transistor and IC performance, array physical design, digital beam former complexity, and systems cost.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121459644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
High-speed time-interleaved ADCs are becoming more common in wireline receiver front-ends due to the enabling of subsequent digital processing for equalization and easier support of higher-order modulation schemes [1]. As technology nodes scale, ADCs based on the digital-intensive SAR architecture are more pervasive. However, implementations with the most common SAR algorithm that has sequential single-bit conversion cycles can result in large time-interleaving factors. Also, the sampling of wideband analog signals associated with higher data rates is difficult for conventional bootstrapped switch (BS) T/H circuits that have not adequately scaled in performance. One reason for this is that the low-duty-cycle sampling clocks, which are utilized for avoiding sampling crosstalk between time-interleaved sub-ADCs, shorten the tracking time and requires improvements in T/H circuit startup time. This motivates the use of simple NMOS switches in high-speed ADCs [2], [3]. However, this can negatively impact the high-speed linearity and ADC front-end bandwidth and also require higher supply voltages. This paper presents an ADC that utilizes both a high-bandwidth interleaver architecture based on a speed-enhanced bootstrapped switch and a pipelined-SAR unit ADC with output level shifting (OLS) settling [4] to enable low-power high-speed operation. At 38GS/s, the 7b ADC achieves 41.9fJ/conv.-step at low input frequencies, 64.1fJ/conv.-step at Nyquist, and has 20GHz 3dB bandwidth.
{"title":"A 38GS/s 7b Time-Interleaved Pipelined-SAR ADC with Speed-Enhanced Bootstrapped Switch in 22nm FinFET","authors":"Yuanming Zhu, Tong Liu, Srujan Kumar Kaile, Shiva Kiran, II-Min Yi, Ruida Liu, Julian Camilo Gomez Diaz, S. Hoyos, S. Palermo","doi":"10.1109/CICC53496.2022.9772785","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772785","url":null,"abstract":"High-speed time-interleaved ADCs are becoming more common in wireline receiver front-ends due to the enabling of subsequent digital processing for equalization and easier support of higher-order modulation schemes [1]. As technology nodes scale, ADCs based on the digital-intensive SAR architecture are more pervasive. However, implementations with the most common SAR algorithm that has sequential single-bit conversion cycles can result in large time-interleaving factors. Also, the sampling of wideband analog signals associated with higher data rates is difficult for conventional bootstrapped switch (BS) T/H circuits that have not adequately scaled in performance. One reason for this is that the low-duty-cycle sampling clocks, which are utilized for avoiding sampling crosstalk between time-interleaved sub-ADCs, shorten the tracking time and requires improvements in T/H circuit startup time. This motivates the use of simple NMOS switches in high-speed ADCs [2], [3]. However, this can negatively impact the high-speed linearity and ADC front-end bandwidth and also require higher supply voltages. This paper presents an ADC that utilizes both a high-bandwidth interleaver architecture based on a speed-enhanced bootstrapped switch and a pipelined-SAR unit ADC with output level shifting (OLS) settling [4] to enable low-power high-speed operation. At 38GS/s, the 7b ADC achieves 41.9fJ/conv.-step at low input frequencies, 64.1fJ/conv.-step at Nyquist, and has 20GHz 3dB bandwidth.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128629604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772820
Shenggao Li, M. Lin, Wei-Chih Chen, Chien-Chun Tsai
Since the invention of MOSFET in 1959, and CMOS in 1963, CMOS circuits emerged as the preferred technology for low power battery powered applications such as digital watches and portable instruments. Lithography scaling enabled CMOS to compete in high-performance computing subsequently. Dennard's 1974 summary on CMOS scaling principle further offered the microelectronics industry a scientific scaling direction according to Moore's Law. By 2005, Dennard scaling principle, however, largely broke down due to the subthreshold leakage on planar MOSFET which prevented the Vth, Vdd, and frequency to scale. Double-gate (SOI), and tri-gate (FinFET) were invented to allow the channel to be better controlled so carriers won't escape to the substrate. A gate-all-around (e.g.: nano-wire and nano-sheet) MOSFET has the channel surrounded by gate electrode with even better electrostatic control, leading to leakage reduction and improved carrier mobility. With multi nano-sheets, the effective W (W_eff) in a unit area is also improved, allowing moderate density scaling compared to FinFet devices. More improvement for CMOS scaling is on the horizon by the industry. ForkFET, which uses a barrier layer between PMOS and NMOS, allows the PMOS and NMOS to be placed closer to each other, thus improving transistor density and reducing interconnect RC between PMOS and NMOS. Complementary FET (CFET), which has PMOS and NMOS stacked on top of each other, reduces the interconnect between PMOS and NMOS significantly as the interconnect on vertical stacking is much shorter than horizontal wiring. Future technology advancement may allow more layers of MOSFETs to be manufactured monolithically (Monolithic 3D integration), when thermal and testability challenges are better solved [1]–[9].
{"title":"Interconnect in the Era of 3DIC","authors":"Shenggao Li, M. Lin, Wei-Chih Chen, Chien-Chun Tsai","doi":"10.1109/CICC53496.2022.9772820","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772820","url":null,"abstract":"Since the invention of MOSFET in 1959, and CMOS in 1963, CMOS circuits emerged as the preferred technology for low power battery powered applications such as digital watches and portable instruments. Lithography scaling enabled CMOS to compete in high-performance computing subsequently. Dennard's 1974 summary on CMOS scaling principle further offered the microelectronics industry a scientific scaling direction according to Moore's Law. By 2005, Dennard scaling principle, however, largely broke down due to the subthreshold leakage on planar MOSFET which prevented the Vth, Vdd, and frequency to scale. Double-gate (SOI), and tri-gate (FinFET) were invented to allow the channel to be better controlled so carriers won't escape to the substrate. A gate-all-around (e.g.: nano-wire and nano-sheet) MOSFET has the channel surrounded by gate electrode with even better electrostatic control, leading to leakage reduction and improved carrier mobility. With multi nano-sheets, the effective W (W_eff) in a unit area is also improved, allowing moderate density scaling compared to FinFet devices. More improvement for CMOS scaling is on the horizon by the industry. ForkFET, which uses a barrier layer between PMOS and NMOS, allows the PMOS and NMOS to be placed closer to each other, thus improving transistor density and reducing interconnect RC between PMOS and NMOS. Complementary FET (CFET), which has PMOS and NMOS stacked on top of each other, reduces the interconnect between PMOS and NMOS significantly as the interconnect on vertical stacking is much shorter than horizontal wiring. Future technology advancement may allow more layers of MOSFETs to be manufactured monolithically (Monolithic 3D integration), when thermal and testability challenges are better solved [1]–[9].","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130698579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772827
Dhruv Rajendra Patel, A. Sharif-Bakhtiar, A. C. Carusone
Low-cost optical receivers (RX) operating at 100+ Gb/s 4-PAM with low power are in high demand to support 400GBASE-DR4/FR4 links in data centers. Existing pluggable solutions generally realize the RX front-end in BiCMOS. However, a more integrated solution, with the RX front-ends integrated onto a CMOS host IC and co-packaged alongside the photodiodes (PDs), offers the potential for smaller size, lower cost, and lower power [1], [2]. This work demonstrates a 112 Gb/s 4-PAM linear TIA in CMOS flip-chip co-packaged with commercial PDs and different PD-to-RX interconnect lengths (Fig. 1a).
{"title":"A 112 Gb/s -8.2 dBm Sensitivity 4-PAM Linear TIA in 16nm CMOS with Co-Packaged Photodiodes","authors":"Dhruv Rajendra Patel, A. Sharif-Bakhtiar, A. C. Carusone","doi":"10.1109/CICC53496.2022.9772827","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772827","url":null,"abstract":"Low-cost optical receivers (RX) operating at 100+ Gb/s 4-PAM with low power are in high demand to support 400GBASE-DR4/FR4 links in data centers. Existing pluggable solutions generally realize the RX front-end in BiCMOS. However, a more integrated solution, with the RX front-ends integrated onto a CMOS host IC and co-packaged alongside the photodiodes (PDs), offers the potential for smaller size, lower cost, and lower power [1], [2]. This work demonstrates a 112 Gb/s 4-PAM linear TIA in CMOS flip-chip co-packaged with commercial PDs and different PD-to-RX interconnect lengths (Fig. 1a).","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131099833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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