Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772828
Sandeep Reddy Kukunuru, Loai G. Salem
Ambient light can enable near-perpetual operation of sensing and internet of everything (loE) nodes. A step-up DC-DC converter with a large off-chip inductor (L) [1] or area-consuming on-chip capacitors (C) [2], [3] is typically used to upconvert the low output voltage of a photovoltaic (PV) cell to the required supply level. Instead of using area-consuming energy storage elements (i.e., L or C) to step up the PV voltage, the number of PV cells connected in series can be reconfigured using a switch matrix (SM) to match the maximum power point (MPP) voltage of the cells with the battery voltage (VBAT) under varying light intensity [4]. Unfortunately, manufacturing tolerances, aging, and environmental factors (e.g., shading, dust, and debris) introduce practical mismatches among the PV cells that limit the current, and hence the output power, of a series string to its worst-performing cell, as exemplified in Fig. 1 (top left). In this case, the voltage across the strong cells increases above the MPP value while the weak cells voltages decrease until all PV currents reach the same value, lowering the harvesting efficiency (e.g., by 20% for $Deltamathrm{l}$= 23% in Fig. 1 which is a typical $3sigma$ PV-manufacturing tolerance).
环境光可以使传感和万物互联(loE)节点实现近乎永久的运行。通常采用带有大型片外电感(L)[1]或片上电容(C)[2]，[3]的升压DC-DC变换器，将光伏电池的低输出电压上变频到所需的供电水平。代替使用消耗面积的储能元件(即L或C)来提高PV电压，可以使用开关矩阵(SM)重新配置串联的PV电池的数量，以使电池的最大功率点(MPP)电压与不同光强下的电池电压(VBAT)相匹配[4]。不幸的是，制造公差、老化和环境因素(例如，阴影、灰尘和碎片)会导致PV电池之间的实际不匹配，从而限制了电流，从而限制了串联串的输出功率，从而限制了性能最差的电池，如图1(左上)所示。在这种情况下，强电池之间的电压增加到MPP值以上，而弱电池之间的电压降低，直到所有PV电流达到相同的值，从而降低了收集效率(例如降低20％)% for $Deltamathrm{l}$= 23% in Fig. 1 which is a typical $3sigma$ PV-manufacturing tolerance).
{"title":"A 93.7%-Efficiency 5-Ratio Switched-Photovoltaic DC-DC Converter","authors":"Sandeep Reddy Kukunuru, Loai G. Salem","doi":"10.1109/CICC53496.2022.9772828","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772828","url":null,"abstract":"Ambient light can enable near-perpetual operation of sensing and internet of everything (loE) nodes. A step-up DC-DC converter with a large off-chip inductor (L) [1] or area-consuming on-chip capacitors (C) [2], [3] is typically used to upconvert the low output voltage of a photovoltaic (PV) cell to the required supply level. Instead of using area-consuming energy storage elements (i.e., L or C) to step up the PV voltage, the number of PV cells connected in series can be reconfigured using a switch matrix (SM) to match the maximum power point (MPP) voltage of the cells with the battery voltage (VBAT) under varying light intensity [4]. Unfortunately, manufacturing tolerances, aging, and environmental factors (e.g., shading, dust, and debris) introduce practical mismatches among the PV cells that limit the current, and hence the output power, of a series string to its worst-performing cell, as exemplified in Fig. 1 (top left). In this case, the voltage across the strong cells increases above the MPP value while the weak cells voltages decrease until all PV currents reach the same value, lowering the harvesting efficiency (e.g., by 20% for $Deltamathrm{l}$= 23% in Fig. 1 which is a typical $3sigma$ PV-manufacturing tolerance).","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114679796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772830
Hongyu Wang, Weiti Zhou, Xiangyu Zhang, Xin Lou
Depth is a fundamental information for lots of computer vision applications. Stereo matching is a commonly used depth estimation method that mimics the human binocular vision system. Most stereo matching systems suffer when attempt to strike a balance between accuracy and computational complexity because of two reasons: 1) It is usually assumed that all the surfaces are fronto-parallel, meaning that neighbors share the same disparity. But a lot of real-world situations are slant surfaces like roads and walls. 2) Conventional methods usually utilize winner takes all (WTA) strategy [1]–[4], where aggregated costs in all disparity levels (usually 128 or 256) must be calculated. But there is only one true guess for each pixel position, such that most of the calculated costs are meaningless. To solve the above issues, in this work, a block PatchMatch-based FPGA accelerator for stereo matching is proposed. PatchMatch introduces random search strategy and slant label, where rectangle superpixels called blocks are used as the basic computing element. Main improvements of this work are: 1) Utilized random search strategy and block level computation can save massive computation. 2) Closer-to-reality slant label improves accuracy. Moreover, plane slant is also helpful for following tasks like 3D reconstruction [5], but none of the existing hardware accelerators can provide this information. 3) Algorithm-hardware co-optimized 6-points Census feature and multi-scale propagation (MSP) are proposed. 4) Based on the testing results on industrial-level KITTI dataset, the real-time performance and energy efficiency of the proposed design outperform state-of-the-art FPGA and ASIC designs, with comparable accuracy.
{"title":"A 39pJ/label 1920x1080 165.7 FPS Block PatchMatch Based Stereo Matching Processor on FPGA","authors":"Hongyu Wang, Weiti Zhou, Xiangyu Zhang, Xin Lou","doi":"10.1109/CICC53496.2022.9772830","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772830","url":null,"abstract":"Depth is a fundamental information for lots of computer vision applications. Stereo matching is a commonly used depth estimation method that mimics the human binocular vision system. Most stereo matching systems suffer when attempt to strike a balance between accuracy and computational complexity because of two reasons: 1) It is usually assumed that all the surfaces are fronto-parallel, meaning that neighbors share the same disparity. But a lot of real-world situations are slant surfaces like roads and walls. 2) Conventional methods usually utilize winner takes all (WTA) strategy [1]–[4], where aggregated costs in all disparity levels (usually 128 or 256) must be calculated. But there is only one true guess for each pixel position, such that most of the calculated costs are meaningless. To solve the above issues, in this work, a block PatchMatch-based FPGA accelerator for stereo matching is proposed. PatchMatch introduces random search strategy and slant label, where rectangle superpixels called blocks are used as the basic computing element. Main improvements of this work are: 1) Utilized random search strategy and block level computation can save massive computation. 2) Closer-to-reality slant label improves accuracy. Moreover, plane slant is also helpful for following tasks like 3D reconstruction [5], but none of the existing hardware accelerators can provide this information. 3) Algorithm-hardware co-optimized 6-points Census feature and multi-scale propagation (MSP) are proposed. 4) Based on the testing results on industrial-level KITTI dataset, the real-time performance and energy efficiency of the proposed design outperform state-of-the-art FPGA and ASIC designs, with comparable accuracy.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133154562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772823
Shenglong Zhuo, Lei Zhao, Tao Xia, Lei Wang, Shi-min Shi, Yifan Wu, Chang Liu, Chill Wang, Yuwei Wang, Yuan Li, Hengwei Yu, Jiqing Xu, Aaron Wang, Zhihong Lin, Yun Chen, Rui Bai, Xuefeng Chen, Patrick Chiang
The ability to capture the spatial dimensions of the world around us is growing in importance, with the widespread adoption of 3D-sensing used today for secure facial authentication, AR occlusion, robotic vision and SLAM, autonomous driving, and 3D-reconstruction. Most state-of-the-art light detection and ranging (LiDAR) systems mainly focus on the sensor design [1]–[4]. However, the optical-electrical system of LiDAR is complex, requiring hardware and software co-optimization across the entire signal chain: high-power sub-1ns pulsed laser drivers, high-efficiency lasers, class-1 laser eye-safety, optical lens for focusing or diffusion, high-SNR single-photon detection receiver arrays, and machine learning (ML) based computational photography.
{"title":"Solid-State dToF LiDAR System Using an Eight-Channel Addressable, 20W/Ch Transmitter, and a 128x128 SPAD Receiver with SNR-Based Pixel Binning and Resolution Upscaling","authors":"Shenglong Zhuo, Lei Zhao, Tao Xia, Lei Wang, Shi-min Shi, Yifan Wu, Chang Liu, Chill Wang, Yuwei Wang, Yuan Li, Hengwei Yu, Jiqing Xu, Aaron Wang, Zhihong Lin, Yun Chen, Rui Bai, Xuefeng Chen, Patrick Chiang","doi":"10.1109/CICC53496.2022.9772823","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772823","url":null,"abstract":"The ability to capture the spatial dimensions of the world around us is growing in importance, with the widespread adoption of 3D-sensing used today for secure facial authentication, AR occlusion, robotic vision and SLAM, autonomous driving, and 3D-reconstruction. Most state-of-the-art light detection and ranging (LiDAR) systems mainly focus on the sensor design [1]–[4]. However, the optical-electrical system of LiDAR is complex, requiring hardware and software co-optimization across the entire signal chain: high-power sub-1ns pulsed laser drivers, high-efficiency lasers, class-1 laser eye-safety, optical lens for focusing or diffusion, high-SNR single-photon detection receiver arrays, and machine learning (ML) based computational photography.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133389937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772829
Bill Y. Lin, Tzu-Yuan Huang, Amr Ahmed, Min-Yu Huang, Hua Wang
Due to the rapid growth in wireless mobile devices use (e.g., autonomous vehicles and unmanned aircraft systems), there is a rising demand for high-speed/Multiple-Input-Multiple-Output (MIMO) wireless links to navigate the increasingly dynamic environments. Current mm-Wave links rely on large transmitting/receiving (Tx/Rx) digital arrays to support the required mm-Wave link budget at the cost of narrower communication beamwidth, which demands fine beam alignment over the entire field-of-view (FoV), increases the number of iterations required to establish a reliable link, and worsens the overall array's response time. Agile and rapid spectral-spatial front-end filtering/beamforming is required to facilitate wideband mm-Wave digital arrays to handle varying strong blocker signals with unknown frequency/angle-of-arrival (AoA) in practical EM scenarios. Most existing front-end spatial filtering methods in digital arrays use open-loop analog beamformers [1]–[3], which have limited FoV, require previous knowledge (frequency/AoA) of the signals/blockers or perform on-the-fly beam-space computations using digital backends which is not suitable for mobile applications. An alternative to FoV-limited analog front-end beamforming is utilizing the digital backend to identify the blockers'/signals' AoA and applying the optimum spatial filtering and beamforming in response [4]. The presence of multiple strong signals/blockers imposes high linearity and high dynamic range requirements on the receiver front-end and ADC; otherwise, strong signals/blockers may saturate the front-end, and exceed the ADC dynamic range. A DLL-like autonomous beamformers using phase-domain negative feedback is reported in [5] which rapidly suppresses multiple unknown strong signals or blockers and support wideband Gbit/s signals/blockers [5]. However, its array architecture only demonstrates 1–D array operation and cannot handle practical applications in a planar 2-D array.
{"title":"A 23-37GHz Autonomous Two-Dimensional MIMO Receiver Array with Rapid Full-FoV Spatial Filtering for Unknown Interference Suppression","authors":"Bill Y. Lin, Tzu-Yuan Huang, Amr Ahmed, Min-Yu Huang, Hua Wang","doi":"10.1109/CICC53496.2022.9772829","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772829","url":null,"abstract":"Due to the rapid growth in wireless mobile devices use (e.g., autonomous vehicles and unmanned aircraft systems), there is a rising demand for high-speed/Multiple-Input-Multiple-Output (MIMO) wireless links to navigate the increasingly dynamic environments. Current mm-Wave links rely on large transmitting/receiving (Tx/Rx) digital arrays to support the required mm-Wave link budget at the cost of narrower communication beamwidth, which demands fine beam alignment over the entire field-of-view (FoV), increases the number of iterations required to establish a reliable link, and worsens the overall array's response time. Agile and rapid spectral-spatial front-end filtering/beamforming is required to facilitate wideband mm-Wave digital arrays to handle varying strong blocker signals with unknown frequency/angle-of-arrival (AoA) in practical EM scenarios. Most existing front-end spatial filtering methods in digital arrays use open-loop analog beamformers [1]–[3], which have limited FoV, require previous knowledge (frequency/AoA) of the signals/blockers or perform on-the-fly beam-space computations using digital backends which is not suitable for mobile applications. An alternative to FoV-limited analog front-end beamforming is utilizing the digital backend to identify the blockers'/signals' AoA and applying the optimum spatial filtering and beamforming in response [4]. The presence of multiple strong signals/blockers imposes high linearity and high dynamic range requirements on the receiver front-end and ADC; otherwise, strong signals/blockers may saturate the front-end, and exceed the ADC dynamic range. A DLL-like autonomous beamformers using phase-domain negative feedback is reported in [5] which rapidly suppresses multiple unknown strong signals or blockers and support wideband Gbit/s signals/blockers [5]. However, its array architecture only demonstrates 1–D array operation and cannot handle practical applications in a planar 2-D array.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125087456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772853
A. Ghosh, Dong-Hyun Seo, D. Das, Santosh K. Ghosh, Shreyas Sen
Computationally secure cryptographic algorithm leaks meaningful side-channel information which can be exploited to extract confidential data. Circuit level countermeasures against power/ EM side channel attack (SCA) like current equalizer [1], series LDO with randomization [2], integrated buck regulator (IBR) [3] had been demonstrated recently providing moderate security (~10M) against Correlational Power/EM attack (CPA/CEMA). Current domain signature attenuation (CDSA) [4] achieved >1B minimum-traces-to-disclosure (MTD) with a single analog technique. Randomized non-linear LDO cascaded with arithmetic countermeasure achieves similar security [5], albeit with combination of two techniques. A process-scalable version of [4] achieved ~250M MTD [6] with bleed-RO randomization, and ~20M MTD without it [7]. Cascading this solution with TVTF [6] provided highest security till date. On the other hand, digital friendly NL-DLDO suffers from higher overhead. Arithmetic countermeasure is fully synthesizable, but algorithm specific, cannot be easily ported to another encryption algorithm. In [6], the digital friendly current source (CS) brings the benefit of signature attenuation in digital domain, however, lacks the high attenuation and MTD from Analog Cascode CS in [4]. Most importantly, a dedicated attack on the state-of-the-art (SoA) countermeasures is still left unexplored. This work for the first time explores the possibility of an attack on signature attenuation hardwares using malicious reduction of voltage and utilizes an intelligent attack detector circuit to detect such attacks and adapt to it to guarantee the efficacy of such signature attenuation-based countermeasures. Moreover, an improved digital-friendly cascoded CS is implemented achieving the highest signature attenuation with digital-friendly technique till date, i.e. a ~10x improvement without RO-bleed randomization. A detailed progress of countermeasure along with motivation is presented in Fig. 1. The 65nm CMOS test chip (side figure) consists of a parallel AES-256 encryption engine along with an Intelligent Digital Cascoded Signature Attenuation Circuit (i-DCSAC) as countermeasure and malicious attack detector.
{"title":"A Digital Cascoded Signature Attenuation Countermeasure with Intelligent Malicious Voltage Drop Attack Detector for EM/Power SCA Resilient Parallel AES-256","authors":"A. Ghosh, Dong-Hyun Seo, D. Das, Santosh K. Ghosh, Shreyas Sen","doi":"10.1109/CICC53496.2022.9772853","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772853","url":null,"abstract":"Computationally secure cryptographic algorithm leaks meaningful side-channel information which can be exploited to extract confidential data. Circuit level countermeasures against power/ EM side channel attack (SCA) like current equalizer [1], series LDO with randomization [2], integrated buck regulator (IBR) [3] had been demonstrated recently providing moderate security (~10M) against Correlational Power/EM attack (CPA/CEMA). Current domain signature attenuation (CDSA) [4] achieved >1B minimum-traces-to-disclosure (MTD) with a single analog technique. Randomized non-linear LDO cascaded with arithmetic countermeasure achieves similar security [5], albeit with combination of two techniques. A process-scalable version of [4] achieved ~250M MTD [6] with bleed-RO randomization, and ~20M MTD without it [7]. Cascading this solution with TVTF [6] provided highest security till date. On the other hand, digital friendly NL-DLDO suffers from higher overhead. Arithmetic countermeasure is fully synthesizable, but algorithm specific, cannot be easily ported to another encryption algorithm. In [6], the digital friendly current source (CS) brings the benefit of signature attenuation in digital domain, however, lacks the high attenuation and MTD from Analog Cascode CS in [4]. Most importantly, a dedicated attack on the state-of-the-art (SoA) countermeasures is still left unexplored. This work for the first time explores the possibility of an attack on signature attenuation hardwares using malicious reduction of voltage and utilizes an intelligent attack detector circuit to detect such attacks and adapt to it to guarantee the efficacy of such signature attenuation-based countermeasures. Moreover, an improved digital-friendly cascoded CS is implemented achieving the highest signature attenuation with digital-friendly technique till date, i.e. a ~10x improvement without RO-bleed randomization. A detailed progress of countermeasure along with motivation is presented in Fig. 1. The 65nm CMOS test chip (side figure) consists of a parallel AES-256 encryption engine along with an Intelligent Digital Cascoded Signature Attenuation Circuit (i-DCSAC) as countermeasure and malicious attack detector.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125928885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772825
Ruichang Ma, Haikun Jia, W. Deng, Zhihua Wang, B. Chi
In recent years, common-mode resonance at twice the oscillation frequency has been proven to be an effective method to improve the FoM and phase noise performance of LC VCOs [1]–[4]. In [2], the implicit common-mode is proposed to merge the common-mode resonance tank into the VCO's main tank to save the chip area as shown in the left of Fig. 1. The VCO in [3] boosts both the common-mode impedance at 2ND harmonic and differential-mode impedance at 3RD harmonic frequency to improve the FoM as shown in the middle of Fig. 1. However, manual harmonic tuning to align those harmonic resonance frequencies is needed in both VCOs in [2] and [3] to uphold an optimal performance over the tuning range. To avoid the manual harmonic tuning, an extra resonator is added to the main tank in [4], improving phase noise over a wide bandwidth. However, the extra head resonator inevitably increases the VCO's chip area.
{"title":"A 12.5-to-15.4GHz, -118.9dBc/Hz PN at 1MHz offset, and 191.0dBc/Hz FoM VCO with Common-Mode Resonance Expansion and Simultaneous Differential 2ND-Harmonic Output using a Single Three-Coil Transformer in 65nm CMOS","authors":"Ruichang Ma, Haikun Jia, W. Deng, Zhihua Wang, B. Chi","doi":"10.1109/CICC53496.2022.9772825","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772825","url":null,"abstract":"In recent years, common-mode resonance at twice the oscillation frequency has been proven to be an effective method to improve the FoM and phase noise performance of LC VCOs [1]–[4]. In [2], the implicit common-mode is proposed to merge the common-mode resonance tank into the VCO's main tank to save the chip area as shown in the left of Fig. 1. The VCO in [3] boosts both the common-mode impedance at 2ND harmonic and differential-mode impedance at 3RD harmonic frequency to improve the FoM as shown in the middle of Fig. 1. However, manual harmonic tuning to align those harmonic resonance frequencies is needed in both VCOs in [2] and [3] to uphold an optimal performance over the tuning range. To avoid the manual harmonic tuning, an extra resonator is added to the main tank in [4], improving phase noise over a wide bandwidth. However, the extra head resonator inevitably increases the VCO's chip area.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115195551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772867
Woojoong Jung, Minsu Kim, Hyun-Il Park, Sungmin Yoo, Tae-Hwang Kong, Jun-Hyeok Yang, Michael Choi, Jongshin Shin, Hyung-Min Lee
Supply voltages of mobile systems have been gradually scaled down, requiring step-down converters with a low voltage conversion ratio (VCR) that can convert a Li-ion battery voltage of 2.8-4.2V to a lower supply voltage around 1V [1]–[4]. Also, the sizes of mobile device are getting smaller, limiting the volume of output components, especially inductors. Smaller-volume inductors suffer from larger DC resistance (DCR), increasing conduction power loss. To address these issues, hybrid topologies, which transfer load currents through both inductor and capacitor in parallel to reduce DCR losses, have been proposed [5], but more aggressive techniques to further improve efficiencies are required. The proposed converter not only reduces the inductor current, $I_{L}$, with an always-dual-path topology, but also minimizes $Delta I_{L}$ using recursive switching level control that can reduce the switching voltage difference across the inductor in a build-up phase.
{"title":"A Hybrid Always-Dual-Path Recursive Step-Down Converter Using Adaptive Switching Level Control Achieving 95.4% Efficiency with 288mΩ Large-DCR Inductor","authors":"Woojoong Jung, Minsu Kim, Hyun-Il Park, Sungmin Yoo, Tae-Hwang Kong, Jun-Hyeok Yang, Michael Choi, Jongshin Shin, Hyung-Min Lee","doi":"10.1109/CICC53496.2022.9772867","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772867","url":null,"abstract":"Supply voltages of mobile systems have been gradually scaled down, requiring step-down converters with a low voltage conversion ratio (VCR) that can convert a Li-ion battery voltage of 2.8-4.2V to a lower supply voltage around 1V [1]–[4]. Also, the sizes of mobile device are getting smaller, limiting the volume of output components, especially inductors. Smaller-volume inductors suffer from larger DC resistance (DCR), increasing conduction power loss. To address these issues, hybrid topologies, which transfer load currents through both inductor and capacitor in parallel to reduce DCR losses, have been proposed [5], but more aggressive techniques to further improve efficiencies are required. The proposed converter not only reduces the inductor current, $I_{L}$, with an always-dual-path topology, but also minimizes $Delta I_{L}$ using recursive switching level control that can reduce the switching voltage difference across the inductor in a build-up phase.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115848570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772834
Christoph Rindfleisch, Jens Otten, B. Wicht
There is a growing need for compact and energy efficient high-voltage (HV) DCDC converters with input voltages >100V for low-power applications up to 500mW. This includes loT and smart-home, supplied from the ac mains, as well as auxiliary supplies for power converters in electrical vehicles and in the field of renewable energy that operate from HV DC-link. Discrete state-of-the-art power supplies are not efficient at light loads below 500mW and are relatively large in size, Fig. 1. They typically use a passive-clamp flyback (PCF) topology (Fig. 1 bottom right) with large external components, such as power switches (QM), HV capacitors $(Cc)$, the output diode $mathrm{D}_{text{out}}$, and a transformer $top$ with up to several millihenries of inductance. The passive clamp topology also suffers from losses due to the leakage inductance $L_{text{lk}}$ and the hard switching of $mathrm{Q}_{mathrm{M}}$. Non-isolated HV DCDC converters with dedicated power topologies [1] achieve good power densities but are not suitable for applications that require galvanic HV isolation. Active clamp flyback (ACF) converters (Fig. 1 bottom left) allow for galvanic isolation while keeping switching losses low. However, ACF designs [2], [3] are usually optimized for high output power and still require large external components. Further, their complex control limits the light-load efficiency. This paper presents a low-power-optimized ACF IC that benefits from integration in a 180nm HV SOI technology. It offers a fully integrated power stage and provides a robust and time-precise control at faster switching speed and more compact size. This way, high light-load efficiency and good power density are achieved.
{"title":"A Highly-Integrated 20-300V 0.5W Active-Clamp Flyback DCDC Converter with 76.7% Peak Efficiency","authors":"Christoph Rindfleisch, Jens Otten, B. Wicht","doi":"10.1109/CICC53496.2022.9772834","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772834","url":null,"abstract":"There is a growing need for compact and energy efficient high-voltage (HV) DCDC converters with input voltages >100V for low-power applications up to 500mW. This includes loT and smart-home, supplied from the ac mains, as well as auxiliary supplies for power converters in electrical vehicles and in the field of renewable energy that operate from HV DC-link. Discrete state-of-the-art power supplies are not efficient at light loads below 500mW and are relatively large in size, Fig. 1. They typically use a passive-clamp flyback (PCF) topology (Fig. 1 bottom right) with large external components, such as power switches (QM), HV capacitors $(Cc)$, the output diode $mathrm{D}_{text{out}}$, and a transformer $top$ with up to several millihenries of inductance. The passive clamp topology also suffers from losses due to the leakage inductance $L_{text{lk}}$ and the hard switching of $mathrm{Q}_{mathrm{M}}$. Non-isolated HV DCDC converters with dedicated power topologies [1] achieve good power densities but are not suitable for applications that require galvanic HV isolation. Active clamp flyback (ACF) converters (Fig. 1 bottom left) allow for galvanic isolation while keeping switching losses low. However, ACF designs [2], [3] are usually optimized for high output power and still require large external components. Further, their complex control limits the light-load efficiency. This paper presents a low-power-optimized ACF IC that benefits from integration in a 180nm HV SOI technology. It offers a fully integrated power stage and provides a robust and time-precise control at faster switching speed and more compact size. This way, high light-load efficiency and good power density are achieved.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131693462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772868
Yuanming Zhu, Julian Camilo Gomez Diaz, Srujan Kumar Kaile, II-Min Yi, Tong Liu, S. Hoyos, S. Palermo
Demand for increased data-rates in serial link transceivers calls for innovative architectures capable of overcoming communications impairments such as limited channel bandwidth and stringent jitter specifications. While mixed-signal and ADC-based receiver architectures that utilize simple pulse amplitude modulation (PAM) can take advantage of technology scaling, it is becoming increasingly difficult to deal with the extremely short baseband pulse widths. This paper presents a wireline receiver front-end (RXFE) architecture that supports multicarrier signaling to provide a ~3X relaxation in clock jitter requirements.
{"title":"A Jitter-Robust 40Gb/s ADC-Based Multicarrier Receiver Front End in 22nm FinFET","authors":"Yuanming Zhu, Julian Camilo Gomez Diaz, Srujan Kumar Kaile, II-Min Yi, Tong Liu, S. Hoyos, S. Palermo","doi":"10.1109/CICC53496.2022.9772868","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772868","url":null,"abstract":"Demand for increased data-rates in serial link transceivers calls for innovative architectures capable of overcoming communications impairments such as limited channel bandwidth and stringent jitter specifications. While mixed-signal and ADC-based receiver architectures that utilize simple pulse amplitude modulation (PAM) can take advantage of technology scaling, it is becoming increasingly difficult to deal with the extremely short baseband pulse widths. This paper presents a wireline receiver front-end (RXFE) architecture that supports multicarrier signaling to provide a ~3X relaxation in clock jitter requirements.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125675213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772836
J. Y. Kim, A. Liscidini
The removal of the surface acoustic wave (SAW) filter in front of the receiver, in favour of less expensive and less filtering solutions, demands large input signals to be handled (sometimes above OdBm) without degrading the noise floor. Such requirements lead to an increment of power consumption in both the signal and the local oscillator (LO) paths. In the former, larger input compression points (CP) are typically obtained by limiting the voltage gain at RF with the use of current-passive mixer architectures followed by power hungry trans-impedance amplifiers (TIA) [1]–[5]. In the LO path, large input signals demand power hungry buffers (with phase noise (PN) even below -170dBc/Hz) to deal with reciprocal mixing phenomena [6].
{"title":"A 2GHz voltage mode power scalable RF-Front-End with 2.5dB-NF and 0.5dBm-1dBCP","authors":"J. Y. Kim, A. Liscidini","doi":"10.1109/CICC53496.2022.9772836","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772836","url":null,"abstract":"The removal of the surface acoustic wave (SAW) filter in front of the receiver, in favour of less expensive and less filtering solutions, demands large input signals to be handled (sometimes above OdBm) without degrading the noise floor. Such requirements lead to an increment of power consumption in both the signal and the local oscillator (LO) paths. In the former, larger input compression points (CP) are typically obtained by limiting the voltage gain at RF with the use of current-passive mixer architectures followed by power hungry trans-impedance amplifiers (TIA) [1]–[5]. In the LO path, large input signals demand power hungry buffers (with phase noise (PN) even below -170dBc/Hz) to deal with reciprocal mixing phenomena [6].","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114327965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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