Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772820
Shenggao Li, M. Lin, Wei-Chih Chen, Chien-Chun Tsai
Since the invention of MOSFET in 1959, and CMOS in 1963, CMOS circuits emerged as the preferred technology for low power battery powered applications such as digital watches and portable instruments. Lithography scaling enabled CMOS to compete in high-performance computing subsequently. Dennard's 1974 summary on CMOS scaling principle further offered the microelectronics industry a scientific scaling direction according to Moore's Law. By 2005, Dennard scaling principle, however, largely broke down due to the subthreshold leakage on planar MOSFET which prevented the Vth, Vdd, and frequency to scale. Double-gate (SOI), and tri-gate (FinFET) were invented to allow the channel to be better controlled so carriers won't escape to the substrate. A gate-all-around (e.g.: nano-wire and nano-sheet) MOSFET has the channel surrounded by gate electrode with even better electrostatic control, leading to leakage reduction and improved carrier mobility. With multi nano-sheets, the effective W (W_eff) in a unit area is also improved, allowing moderate density scaling compared to FinFet devices. More improvement for CMOS scaling is on the horizon by the industry. ForkFET, which uses a barrier layer between PMOS and NMOS, allows the PMOS and NMOS to be placed closer to each other, thus improving transistor density and reducing interconnect RC between PMOS and NMOS. Complementary FET (CFET), which has PMOS and NMOS stacked on top of each other, reduces the interconnect between PMOS and NMOS significantly as the interconnect on vertical stacking is much shorter than horizontal wiring. Future technology advancement may allow more layers of MOSFETs to be manufactured monolithically (Monolithic 3D integration), when thermal and testability challenges are better solved [1]–[9].
{"title":"Interconnect in the Era of 3DIC","authors":"Shenggao Li, M. Lin, Wei-Chih Chen, Chien-Chun Tsai","doi":"10.1109/CICC53496.2022.9772820","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772820","url":null,"abstract":"Since the invention of MOSFET in 1959, and CMOS in 1963, CMOS circuits emerged as the preferred technology for low power battery powered applications such as digital watches and portable instruments. Lithography scaling enabled CMOS to compete in high-performance computing subsequently. Dennard's 1974 summary on CMOS scaling principle further offered the microelectronics industry a scientific scaling direction according to Moore's Law. By 2005, Dennard scaling principle, however, largely broke down due to the subthreshold leakage on planar MOSFET which prevented the Vth, Vdd, and frequency to scale. Double-gate (SOI), and tri-gate (FinFET) were invented to allow the channel to be better controlled so carriers won't escape to the substrate. A gate-all-around (e.g.: nano-wire and nano-sheet) MOSFET has the channel surrounded by gate electrode with even better electrostatic control, leading to leakage reduction and improved carrier mobility. With multi nano-sheets, the effective W (W_eff) in a unit area is also improved, allowing moderate density scaling compared to FinFet devices. More improvement for CMOS scaling is on the horizon by the industry. ForkFET, which uses a barrier layer between PMOS and NMOS, allows the PMOS and NMOS to be placed closer to each other, thus improving transistor density and reducing interconnect RC between PMOS and NMOS. Complementary FET (CFET), which has PMOS and NMOS stacked on top of each other, reduces the interconnect between PMOS and NMOS significantly as the interconnect on vertical stacking is much shorter than horizontal wiring. Future technology advancement may allow more layers of MOSFETs to be manufactured monolithically (Monolithic 3D integration), when thermal and testability challenges are better solved [1]–[9].","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130698579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772803
Jieyu Li, Weifeng He, Bo Zhang, Guanghui He, Jun Yang, Mingoo Seok
Energy-efficient bitcoin mining cores have gained significant attention since the energy cost for computing dominates the mining expenses [1]. Ultra-low-voltage (ULV) digital circuits have emerged as an attractive approach to improve the energy-efficiency. However, they demand a large timing margin for the worst-case process, voltage, and temperature (PVT) variations, undermining a significant portion of energy savings. Recent works, including multi-phase latch pipeline [1], tunable replica circuits [2]–[3], in-situ error detection and correction (EDAC) [4]–[6], and dynamic timing enhancement [7], can reduce the pessimistic margin. However, it is not straightforward to adopt those techniques in mining cores due to their deeply-pipelined architecture (up to 128 stages [1]). For example, to adopt EDAC, the deep pipeline requires inserting many bulky error detectors as it has many critical paths. Our experiment with a 0.3V 28-nm mining core shows >18.9% registers need to be replaced with error detectors, considering 6σ local process variation only. Also, multiple stages can have timing errors simultaneously, making an error correction process (e.g., clock gating [5], VDD boosting [6]) complex and costly.
{"title":"TICA: A 0.3V, Variation-Resilient 64-Stage Deeply-Pipelined Bitcoin Mining Core with Timing Slack Inference and Clock Frequency Adaption","authors":"Jieyu Li, Weifeng He, Bo Zhang, Guanghui He, Jun Yang, Mingoo Seok","doi":"10.1109/CICC53496.2022.9772803","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772803","url":null,"abstract":"Energy-efficient bitcoin mining cores have gained significant attention since the energy cost for computing dominates the mining expenses [1]. Ultra-low-voltage (ULV) digital circuits have emerged as an attractive approach to improve the energy-efficiency. However, they demand a large timing margin for the worst-case process, voltage, and temperature (PVT) variations, undermining a significant portion of energy savings. Recent works, including multi-phase latch pipeline [1], tunable replica circuits [2]–[3], in-situ error detection and correction (EDAC) [4]–[6], and dynamic timing enhancement [7], can reduce the pessimistic margin. However, it is not straightforward to adopt those techniques in mining cores due to their deeply-pipelined architecture (up to 128 stages [1]). For example, to adopt EDAC, the deep pipeline requires inserting many bulky error detectors as it has many critical paths. Our experiment with a 0.3V 28-nm mining core shows >18.9% registers need to be replaced with error detectors, considering 6σ local process variation only. Also, multiple stages can have timing errors simultaneously, making an error correction process (e.g., clock gating [5], VDD boosting [6]) complex and costly.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132379694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772833
Kyeongho Eom, Hanyeop Lee, Mi-Hyun Park, Hyung-Min Lee, S. Yang, Jong-chan Choe, Suk-Won Hwang, Young-Woo Suh
Implantable medical devices (IMD) with stimulation system-on-chip (SoC) have been essential techniques for disease treatments and rehabilitations. As neuromuscular stimulation injects a large amount of stimulus energy into the body, its energy efficiency and safety should be carefully considered, which otherwise damages cellular tissues. Conventional current stimulation suffers from large power losses across current sources. Even adopting the adaptive supply voltage, the stimulator efficiency is still limited below 60% [1]. The switched capacitor stimulation (SCS) system charges the capacitor and transfer its charges to the tissue, achieving stimulator efficiency up to 84% [2]–[4]. However, previous SCS systems only operate with AC input voltages directly from wireless power, which can be interrupted in loosely-coupled inductive links. To take advantages of using a rechargeable battery or a supercapacitor for reliable IMD operation, the SCS system that can efficiently operate with both DC and AC inputs is required. Also, more aggressive techniques to further improve stimulator efficiency and efficacy are highly needed.
{"title":"A 92%-Efficiency Inductor-Charging Switched-Capacitor Stimulation System with Level-Adaptive Duty Modulation and Offset Charge Balancing for Muscular Stimulation","authors":"Kyeongho Eom, Hanyeop Lee, Mi-Hyun Park, Hyung-Min Lee, S. Yang, Jong-chan Choe, Suk-Won Hwang, Young-Woo Suh","doi":"10.1109/CICC53496.2022.9772833","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772833","url":null,"abstract":"Implantable medical devices (IMD) with stimulation system-on-chip (SoC) have been essential techniques for disease treatments and rehabilitations. As neuromuscular stimulation injects a large amount of stimulus energy into the body, its energy efficiency and safety should be carefully considered, which otherwise damages cellular tissues. Conventional current stimulation suffers from large power losses across current sources. Even adopting the adaptive supply voltage, the stimulator efficiency is still limited below 60% [1]. The switched capacitor stimulation (SCS) system charges the capacitor and transfer its charges to the tissue, achieving stimulator efficiency up to 84% [2]–[4]. However, previous SCS systems only operate with AC input voltages directly from wireless power, which can be interrupted in loosely-coupled inductive links. To take advantages of using a rechargeable battery or a supercapacitor for reliable IMD operation, the SCS system that can efficiently operate with both DC and AC inputs is required. Also, more aggressive techniques to further improve stimulator efficiency and efficacy are highly needed.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134223201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772796
Francesco Buccoleri, S. M. Dartizio, F. Tesolin, Luca Avallone, Alessio Santiccioli, Agata Lesurum, Giovanni Steffan, A. Bevilacqua, L. Bertulessi, Dmytro Cherniak, C. Samori, A. Lacaita, S. Levantino
Sub-100fs fractional-N PLLs in the tens of GHz range are required by modern wireless standards such as 5G [1]. The main factors limiting jitter and spot-noise in a digital PLL (DPLL) are on one hand the phase noise of the digitally controlled oscillator (DCO) and, on the other hand, the quantization noise (QN) introduced by the DCO frequency granularity. Though several approaches, such as multi-core oscillators [2], [3] or multi-core PLLs [4] have been explored to trade power consumption against phase noise, the theoretical phase-noise reduction of 3dB per each doubling of the number of cores is never fully obtained in practice. The second issue of the QN introduced at the DCO analog/digital domain crossing could be in principle solved by increasing DCO resolution, but this comes at the cost of a larger number of DCO bits which entails higher design complexity and larger area occupation. Alternatively, a $DeltaSigma$ modulator driving the DCO can be used to high-pass-shape the QN and its clock oversampled with respect to the reference frequency to move the QN bump in the spectrum to higher frequency. Prior solutions to generate the $DeltaSigma$ clock are based either on an auxiliary PLL which multiplies the reference clock frequency or a high-speed frequency divider that divides the DCO output [3]. While in the first case pulling phenomena between auxiliary and main PLL are observed to worsen performance, in the second case, the frequency divider may consume large power and metastability in the crossing between the two non-synchronous clock domains has to be addressed. This work presents a 9GHz fractional-N digital bang-bang PLL (BBPLL) achieving 72fs rms total integrated jitter (including spurs) at near-integer channels and -140.7dBc/Hz spot phase-noise level at 10MHz offset. The PLL relies on a low-power quadrupler calibrated by a background digital-period-averaging (DPA) algorithm to reduce the QN of the $DeltaSigma$ DCO, and on a low-noise true-in-phase combiner (TIPC) which combines two PLL cores to reduce phase noise.
{"title":"A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler","authors":"Francesco Buccoleri, S. M. Dartizio, F. Tesolin, Luca Avallone, Alessio Santiccioli, Agata Lesurum, Giovanni Steffan, A. Bevilacqua, L. Bertulessi, Dmytro Cherniak, C. Samori, A. Lacaita, S. Levantino","doi":"10.1109/CICC53496.2022.9772796","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772796","url":null,"abstract":"Sub-100fs fractional-N PLLs in the tens of GHz range are required by modern wireless standards such as 5G [1]. The main factors limiting jitter and spot-noise in a digital PLL (DPLL) are on one hand the phase noise of the digitally controlled oscillator (DCO) and, on the other hand, the quantization noise (QN) introduced by the DCO frequency granularity. Though several approaches, such as multi-core oscillators [2], [3] or multi-core PLLs [4] have been explored to trade power consumption against phase noise, the theoretical phase-noise reduction of 3dB per each doubling of the number of cores is never fully obtained in practice. The second issue of the QN introduced at the DCO analog/digital domain crossing could be in principle solved by increasing DCO resolution, but this comes at the cost of a larger number of DCO bits which entails higher design complexity and larger area occupation. Alternatively, a $DeltaSigma$ modulator driving the DCO can be used to high-pass-shape the QN and its clock oversampled with respect to the reference frequency to move the QN bump in the spectrum to higher frequency. Prior solutions to generate the $DeltaSigma$ clock are based either on an auxiliary PLL which multiplies the reference clock frequency or a high-speed frequency divider that divides the DCO output [3]. While in the first case pulling phenomena between auxiliary and main PLL are observed to worsen performance, in the second case, the frequency divider may consume large power and metastability in the crossing between the two non-synchronous clock domains has to be addressed. This work presents a 9GHz fractional-N digital bang-bang PLL (BBPLL) achieving 72fs rms total integrated jitter (including spurs) at near-integer channels and -140.7dBc/Hz spot phase-noise level at 10MHz offset. The PLL relies on a low-power quadrupler calibrated by a background digital-period-averaging (DPA) algorithm to reduce the QN of the $DeltaSigma$ DCO, and on a low-noise true-in-phase combiner (TIPC) which combines two PLL cores to reduce phase noise.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114669357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772822
Nimesh Nadishka Miral, Karan Sohal, D. Manstretta, R. Castello
Trans-impedance amplifiers (TIAs) are used as building blocks in many applications: from wireless transceivers to qubit manipulation and readout in quantum computing [1] or as amplifying circuits in fiber optics receivers [2].
{"title":"Filtering Trans-Impedance Amplifiers: from mW of Power to GHz of Bandwidth","authors":"Nimesh Nadishka Miral, Karan Sohal, D. Manstretta, R. Castello","doi":"10.1109/CICC53496.2022.9772822","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772822","url":null,"abstract":"Trans-impedance amplifiers (TIAs) are used as building blocks in many applications: from wireless transceivers to qubit manipulation and readout in quantum computing [1] or as amplifying circuits in fiber optics receivers [2].","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126336607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772848
Chen Tan, Wei Huang, Yonghui Fan, Jing Li, Chuanhao Yu, Wenbo Shi, Shiti Huang, Zhenyu Yin, Chenfan Cao, Lei Jing, Zhixiong Ren, Xiaoyan Gui, Bing Zhang, Dan Li, Li Geng
The surge of internet bandwidth recently has accelerated the upgrade of the Passive Optical Network (PON) from 1.25Gb/s GPON to 10Gb/s class XGS-PON with massive volume. As a key component, the burst-mode transimpedance amplifier (BM-TIA) is required to cope with the BM data from multiple users. Previously, high performance BM-TIAs were made mostly by SiGe [1]–[3], contrasting the prospect of economics. At least three issues have hindered CMOS from being widely employed in BM-TIA compared with SiGe. 1) Noise: the relatively poor analog performance as well as limited power supply voltage from CMOS makes low noise difficult to achieve. 2) Breakdown protection: the low breakdown voltage makes CMOS much more fragile to loud bursts. 3) Fast BM response: the low supply voltage renders the CMOS biasing point delicate, which increases the complexity and duration for the circuit to recover from a burst event. Previous CMOS-TIAs [4], [5] have achieved fast BM response, but their topologies are incompatible with current TOCAN based commercial applications which can only house the analog front-end. In this work, we address the noise, breakdown, and fast BM response altogether, paving the way for CMOS to be used in commercial BM application in 10Gb/s class PON and beyond.
{"title":"A 10/2.5-Gb/s Hyper-Supplied CMOS Low-Noise Burst-Mode TIA with Loud Burst Protection and Gearbox Automatic Offset Cancellation for XGS-PON","authors":"Chen Tan, Wei Huang, Yonghui Fan, Jing Li, Chuanhao Yu, Wenbo Shi, Shiti Huang, Zhenyu Yin, Chenfan Cao, Lei Jing, Zhixiong Ren, Xiaoyan Gui, Bing Zhang, Dan Li, Li Geng","doi":"10.1109/CICC53496.2022.9772848","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772848","url":null,"abstract":"The surge of internet bandwidth recently has accelerated the upgrade of the Passive Optical Network (PON) from 1.25Gb/s GPON to 10Gb/s class XGS-PON with massive volume. As a key component, the burst-mode transimpedance amplifier (BM-TIA) is required to cope with the BM data from multiple users. Previously, high performance BM-TIAs were made mostly by SiGe [1]–[3], contrasting the prospect of economics. At least three issues have hindered CMOS from being widely employed in BM-TIA compared with SiGe. 1) Noise: the relatively poor analog performance as well as limited power supply voltage from CMOS makes low noise difficult to achieve. 2) Breakdown protection: the low breakdown voltage makes CMOS much more fragile to loud bursts. 3) Fast BM response: the low supply voltage renders the CMOS biasing point delicate, which increases the complexity and duration for the circuit to recover from a burst event. Previous CMOS-TIAs [4], [5] have achieved fast BM response, but their topologies are incompatible with current TOCAN based commercial applications which can only house the analog front-end. In this work, we address the noise, breakdown, and fast BM response altogether, paving the way for CMOS to be used in commercial BM application in 10Gb/s class PON and beyond.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131527494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772851
Qiuyang Lin, Christina Avidikou, F. Tavernier, N. V. Helleputte
The wearable healthcare market is rapidly growing as fitness and wellness monitoring can significantly improve quality of life. Optical Photoplethysmography (PPG) is a vital monitoring modality and has gained tremendous interest in recent years since it can provide many biomedical parameters with good user comfort. This paper serves as a basic tutorial and reviews recent developments in PPG monitoring, especially the design techniques on building low-power and high dynamic range (DR) readout integrated circuits (ICs). The future development trends are provided as well.
{"title":"Photoplethysmography (PPG) Sensor Circuit Design Techniques","authors":"Qiuyang Lin, Christina Avidikou, F. Tavernier, N. V. Helleputte","doi":"10.1109/CICC53496.2022.9772851","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772851","url":null,"abstract":"The wearable healthcare market is rapidly growing as fitness and wellness monitoring can significantly improve quality of life. Optical Photoplethysmography (PPG) is a vital monitoring modality and has gained tremendous interest in recent years since it can provide many biomedical parameters with good user comfort. This paper serves as a basic tutorial and reviews recent developments in PPG monitoring, especially the design techniques on building low-power and high dynamic range (DR) readout integrated circuits (ICs). The future development trends are provided as well.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122255289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772835
Seungsik Moon, N. Lee, Youngjoo Lee
In 5G networks, as growing data usage exponentially, mobile operators need to increase network capacity. To increase the spectral efficiency of massive multiple-input multiple-output (MIMO) system, it is essential to enlarge the number of co-scheduled user equipments (UEs). As increasing the number of co-scheduled UEs up to the number of base station (BS) antennas, the conventional linear precoding schemes such as zero-forcing and maximum ratio transmission show poor capacity, as shown in Fig. 1. As a result, joint user selection, power allocation, and beamforming schemes, including the rank-adaptation zero-forcing (RA-ZF) and generalized power iteration precoding (GPIP) algorithms, are proposed for large-scale massive MIMO systems. However, the prior works on massive MIMO baseband architectures [1]–[4] are no longer suitable for these advanced algorithms; because they do not consider user selection or power allocation. Consequently, it is crucial to develop energy-and computationally efficient BS architecture that realizes the advanced algorithms to achieve a high spectral efficiency gain.
{"title":"A 2.86Gb/s Fully-Flexible MU-MIMO Processor for Jointly Optimizing User Selection, Power Allocation, and Precoding in 28nm CMOS Technology","authors":"Seungsik Moon, N. Lee, Youngjoo Lee","doi":"10.1109/CICC53496.2022.9772835","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772835","url":null,"abstract":"In 5G networks, as growing data usage exponentially, mobile operators need to increase network capacity. To increase the spectral efficiency of massive multiple-input multiple-output (MIMO) system, it is essential to enlarge the number of co-scheduled user equipments (UEs). As increasing the number of co-scheduled UEs up to the number of base station (BS) antennas, the conventional linear precoding schemes such as zero-forcing and maximum ratio transmission show poor capacity, as shown in Fig. 1. As a result, joint user selection, power allocation, and beamforming schemes, including the rank-adaptation zero-forcing (RA-ZF) and generalized power iteration precoding (GPIP) algorithms, are proposed for large-scale massive MIMO systems. However, the prior works on massive MIMO baseband architectures [1]–[4] are no longer suitable for these advanced algorithms; because they do not consider user selection or power allocation. Consequently, it is crucial to develop energy-and computationally efficient BS architecture that realizes the advanced algorithms to achieve a high spectral efficiency gain.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132408040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772805
Tuur Van Daele, F. Tavernier
High-voltage power sources, such as the mains (up to 240 VRMS) and high-voltage batteries in electric cars (e.g., 400 V), are omnipresent. In contrast, low-power applications like loT, smart homes, and control in electric vehicles need low supply voltages [1]. Bridging this voltage gap requires power converters with high input voltages and large conversion steps. Furthermore, complete integration of these converters enables significant cost reduction and makes the system more reliable and compact. Recent developments confirm this integration trend for large conversion steps, as bulky transformers in power modules are replaced by smaller and fewer external components [1], [2]. However, complete integration of their large off-chip inductors would suffer from a low quality factor, and for large conversions steps, these converters depend on very low duty cycles. The switched-capacitor converter (SCC) is a better candidate since it is easily integrated while operating at a 50 % duty cycle regardless of the conversion step. In addition, it is often used as the second stage in fully integrated AC-DC converters to improve performance [3]. However, state-of-the-art fully integrated SCCs only handle input voltages up to 42 V [3], [4]. In addition, they lack performance due to increased parasitics and component degradation at high voltages.
{"title":"A 400-to-12 V Fully Integrated Switched-Capacitor DC-DC Converter Achieving 119 mW/mm2 at 63.6 % Efficiency","authors":"Tuur Van Daele, F. Tavernier","doi":"10.1109/CICC53496.2022.9772805","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772805","url":null,"abstract":"High-voltage power sources, such as the mains (up to 240 VRMS) and high-voltage batteries in electric cars (e.g., 400 V), are omnipresent. In contrast, low-power applications like loT, smart homes, and control in electric vehicles need low supply voltages [1]. Bridging this voltage gap requires power converters with high input voltages and large conversion steps. Furthermore, complete integration of these converters enables significant cost reduction and makes the system more reliable and compact. Recent developments confirm this integration trend for large conversion steps, as bulky transformers in power modules are replaced by smaller and fewer external components [1], [2]. However, complete integration of their large off-chip inductors would suffer from a low quality factor, and for large conversions steps, these converters depend on very low duty cycles. The switched-capacitor converter (SCC) is a better candidate since it is easily integrated while operating at a 50 % duty cycle regardless of the conversion step. In addition, it is often used as the second stage in fully integrated AC-DC converters to improve performance [3]. However, state-of-the-art fully integrated SCCs only handle input voltages up to 42 V [3], [4]. In addition, they lack performance due to increased parasitics and component degradation at high voltages.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114153895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772793
Kuo-Ken Huang, Jonathan K. Brown, Richard K. Sawyer, Christopher J. Lukas, Farah B. Yahya, Alice Wang, N. Roberts, B. Calhoun, D. Wentzloff
Self-powered systems (SPSs) that harvest energy from the ambient environment, eliminating the battery, are gaining traction due to the increasing need for large-scale data collection in the Industrial Internet of Things (IIoT) space. The ultra-low-power receiver (ULP RX) is one promising solution for this application space that provides benefits from its energy-efficient operation. This paper discusses the requirements of self-powered wireless systems for IIoT applications and the challenges of designing ULP RXs for real-world deployments. Circuit design techniques to address the issues are summarized, and an ULP RX design with a proprietary protocol that is being adopted by commercialized SPSs is presented. Finally, the prospects and future trends for ULP receivers are summarized.
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