Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772864
Jeongseok Lee, Doohwan Jung, D. Munzer, Hua Wang
Spectrally efficient complex modulation schemes are widely employed to support the exponential growth in data traffic. However, this places stringent requirements on the RF electronic frontends, including stringent linearity, high Peak-to-Average-Power-Ratio (PAPR), large modulation bandwidth, and energy efficiency, which poses major challenges in traditional analog RF design. On the other hand, continuous device scaling enables energy-efficient device switching at RF frequencies, which has opened the door to growing research efforts towards digital transmitter (Tx) and receiver (Rx) frontends. Notably, the past few years have witnessed the demonstration of a wide variety of digital power amplifiers with multi-mode operations and back-off efficiency/linearity enhancement [1]–[3]. N-path mixer-first digital receivers remain a popular topic due to their inherent capabilities of high linearity, tunable frontend filtering, and wideband operations [4]. While digital RF frontends naturally offer excellent RF performance and extensive reconfigurability, they commonly rely on architectures based on binary and/or unary arrays of sliced active and passive devices, which inevitably results in substantial area overhead compared to their analog RF counterparts. In particular, capacitor banks are widely used in various digital RF frontends, i.e., switched-capacitor PAs and N-path receivers, which often occupy a majority of the chip area. However, numerous commercial applications, e.g., IOT devices, require extremely compact RF frontends to fit within the application formfactor and cost budget.
{"title":"A Compact Wideband Joint Bidirectional Class-G Digital Doherty Switched-Capacitor Transmitter and N-Path Quadrature Receiver through Capacitor Bank Sharing","authors":"Jeongseok Lee, Doohwan Jung, D. Munzer, Hua Wang","doi":"10.1109/CICC53496.2022.9772864","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772864","url":null,"abstract":"Spectrally efficient complex modulation schemes are widely employed to support the exponential growth in data traffic. However, this places stringent requirements on the RF electronic frontends, including stringent linearity, high Peak-to-Average-Power-Ratio (PAPR), large modulation bandwidth, and energy efficiency, which poses major challenges in traditional analog RF design. On the other hand, continuous device scaling enables energy-efficient device switching at RF frequencies, which has opened the door to growing research efforts towards digital transmitter (Tx) and receiver (Rx) frontends. Notably, the past few years have witnessed the demonstration of a wide variety of digital power amplifiers with multi-mode operations and back-off efficiency/linearity enhancement [1]–[3]. N-path mixer-first digital receivers remain a popular topic due to their inherent capabilities of high linearity, tunable frontend filtering, and wideband operations [4]. While digital RF frontends naturally offer excellent RF performance and extensive reconfigurability, they commonly rely on architectures based on binary and/or unary arrays of sliced active and passive devices, which inevitably results in substantial area overhead compared to their analog RF counterparts. In particular, capacitor banks are widely used in various digital RF frontends, i.e., switched-capacitor PAs and N-path receivers, which often occupy a majority of the chip area. However, numerous commercial applications, e.g., IOT devices, require extremely compact RF frontends to fit within the application formfactor and cost budget.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129305642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Implantable biomedical devices (IMDs) capable of recording electrophysiological signals effectively facilitate medical treatment, but they also face strict volume requirements [1]–[6]. An effective way to miniaturize the IMDs is to eliminate the bulky components such as battery and crystal. Wireless power transfer (WPT) helps to remove the battery [1]–[5], while a bulky crystal is still required to provide a precise clock to ensure the performance of signal-acquisition and communication blocks (Fig. 1 left, top). To eliminate the crystal, prior work [1] uses an on-chip oscillator as the clock generator (Fig. 1 left, middle), while suffering from off-chip tuning and SNR degradation of analog front-end (AFE), ADC, and wireless transmission. Recently, clock recovering from power-harvesting tone has become a promising solution to further reduce the volume of battery-less systems (Fig. 1 left, bottom) [2]–[5]. However, it's difficult to deal with a trade-off: A high power-harvesting frequency leads to power-hungry clock-recovery circuits [4], while a low frequency requires a large-size antenna [5].
{"title":"A Battery-Less Crystal-Less 49.8µW Neural-Recording Chip Featuring Two-Tone RF Power Harvesting","authors":"Ziyi Chang, Changgui Yang, Yunshan Zhang, Zhuhao Li, Tianyu Zheng, Yuxuan Luo, Shaomin Zhang, Kedi Xu, Gang Pan, Bo Zhao, Yong Chen","doi":"10.1109/CICC53496.2022.9772792","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772792","url":null,"abstract":"Implantable biomedical devices (IMDs) capable of recording electrophysiological signals effectively facilitate medical treatment, but they also face strict volume requirements [1]–[6]. An effective way to miniaturize the IMDs is to eliminate the bulky components such as battery and crystal. Wireless power transfer (WPT) helps to remove the battery [1]–[5], while a bulky crystal is still required to provide a precise clock to ensure the performance of signal-acquisition and communication blocks (Fig. 1 left, top). To eliminate the crystal, prior work [1] uses an on-chip oscillator as the clock generator (Fig. 1 left, middle), while suffering from off-chip tuning and SNR degradation of analog front-end (AFE), ADC, and wireless transmission. Recently, clock recovering from power-harvesting tone has become a promising solution to further reduce the volume of battery-less systems (Fig. 1 left, bottom) [2]–[5]. However, it's difficult to deal with a trade-off: A high power-harvesting frequency leads to power-hungry clock-recovery circuits [4], while a low frequency requires a large-size antenna [5].","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127961850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772840
R. Mathur, M. Kumar, V. Asthana, S. Aggarwal, S. Gupta, D. Wanjul, A. Baradia, S. Thota, P. Jain, B. Zheng, A. Cubeta, S. Thyagarajan, A. Chen, Y. Chong
Advances in 7nm and 5nm silicon process nodes push high-performance compute (HPC) to a new era of technological capabilities and unprecedented performance levels. This paper showcases the development of SRAM macros for a flagship HPC platform core targeted towards the infrastructure market (figure 1). A test vehicle in the 5nm FinFET process demonstrates L1 SRAM macro frequency of 5GHz with sub-120ps access times and a high bit density of L2 SRAM macro of 33.20 Mbit/mm2.
{"title":"5GHz SRAM for High-Performance Compute Platform in 5nm CMOS","authors":"R. Mathur, M. Kumar, V. Asthana, S. Aggarwal, S. Gupta, D. Wanjul, A. Baradia, S. Thota, P. Jain, B. Zheng, A. Cubeta, S. Thyagarajan, A. Chen, Y. Chong","doi":"10.1109/CICC53496.2022.9772840","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772840","url":null,"abstract":"Advances in 7nm and 5nm silicon process nodes push high-performance compute (HPC) to a new era of technological capabilities and unprecedented performance levels. This paper showcases the development of SRAM macros for a flagship HPC platform core targeted towards the infrastructure market (figure 1). A test vehicle in the 5nm FinFET process demonstrates L1 SRAM macro frequency of 5GHz with sub-120ps access times and a high bit density of L2 SRAM macro of 33.20 Mbit/mm2.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133293300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772815
Mohamed R. Abdelhamid, U. Ha, Utsav Banerjee, Fadel M. Adib, A. Chandrakasan
There is a growing interest in wireless and batteryless implants for long-term sensing of organ movements, core pressure, glucose levels, or other biometrics [1]. Most research on such implants has focused on ultrasonic [2] and nearfield inductive [3]–[4] methods for power and communication, which require direct contact or close proximity (<1-5cm) to the human body. Recently, RF backscatter has emerged as a promising alternative due to its ability to communicate with far-field (> 10cm) wireless devices at ultra-low-power [5]. While multiple proposals have demonstrated far-field RF backscatter in deep tissues, these proposals have been limited to tag identification and could neither perform biometric sensing nor secure the wireless communication links, which is critical for ensuring the confidentiality of the sensed biometrics and for responding to commands only from authorized users [6]. Moreover, such far-field RF implants are susceptible to tissue variations which impact their resonance and hence their efficiency in RF backscatter and energy harvesting.
{"title":"Wireless, Batteryless, and Secure Implantable System-on-a-Chip for 1.37mmHg Strain Sensing with Bandwidth Reconfigurability for Cross-Tissue Adaptation","authors":"Mohamed R. Abdelhamid, U. Ha, Utsav Banerjee, Fadel M. Adib, A. Chandrakasan","doi":"10.1109/CICC53496.2022.9772815","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772815","url":null,"abstract":"There is a growing interest in wireless and batteryless implants for long-term sensing of organ movements, core pressure, glucose levels, or other biometrics [1]. Most research on such implants has focused on ultrasonic [2] and nearfield inductive [3]–[4] methods for power and communication, which require direct contact or close proximity (<1-5cm) to the human body. Recently, RF backscatter has emerged as a promising alternative due to its ability to communicate with far-field (> 10cm) wireless devices at ultra-low-power [5]. While multiple proposals have demonstrated far-field RF backscatter in deep tissues, these proposals have been limited to tag identification and could neither perform biometric sensing nor secure the wireless communication links, which is critical for ensuring the confidentiality of the sensed biometrics and for responding to commands only from authorized users [6]. Moreover, such far-field RF implants are susceptible to tissue variations which impact their resonance and hence their efficiency in RF backscatter and energy harvesting.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122241823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772873
Zekun Li, Jixin Chen, Jiayang Yu, Huanbo Li, Zichun Zheng, Rui Zhou, Peigen Zhou, Zhe Chen, W. Hong
Due to the increasing demand for high-data-rate transmission in wireless communication, the terahertz (THz) and sub-terahertz (sub-THz) frequency bands have attracted great attention for their rich spectrum resources. Silicon-based technologies with high $f_{T}/f_{max}$ provide a low-cost solution to integrate the transmitters and receivers for sub-THz communication systems [1]–[4].
{"title":"A 220 GHz Sliding-IF Quadrature Transmitter With 38-dB Conversion Gain and 8-dBm Psat in 0.13-µm SiGe BiCMOS","authors":"Zekun Li, Jixin Chen, Jiayang Yu, Huanbo Li, Zichun Zheng, Rui Zhou, Peigen Zhou, Zhe Chen, W. Hong","doi":"10.1109/CICC53496.2022.9772873","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772873","url":null,"abstract":"Due to the increasing demand for high-data-rate transmission in wireless communication, the terahertz (THz) and sub-terahertz (sub-THz) frequency bands have attracted great attention for their rich spectrum resources. Silicon-based technologies with high $f_{T}/f_{max}$ provide a low-cost solution to integrate the transmitters and receivers for sub-THz communication systems [1]–[4].","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127471442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772839
Aviral Pandey, Sina Faraji Alamouti, Justin Doong, Ryan Kaveh, Cem Yalcin, M. M. Ghanbari, R. Muller
Wearable electroencephalography (EEG) systems can monitor neurological activity, enable new brain-computer interfaces and help users communicate with assistive devices. To facilitate ambulatory EEG recording, recent work has incorporated dry electrodes into wearable headsets and earbuds [1], [2]. Dry electrodes have superior ease-of-use over wet electrodes that require abrasive skin preparation. However, due to their high electrode-skin impedance (ESI), dry electrode wearables are susceptible to motion artifacts.
{"title":"A 6.8µW AFE for Ear EEG Recording with Simultaneous Impedance Measurement for Motion Artifact Cancellation","authors":"Aviral Pandey, Sina Faraji Alamouti, Justin Doong, Ryan Kaveh, Cem Yalcin, M. M. Ghanbari, R. Muller","doi":"10.1109/CICC53496.2022.9772839","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772839","url":null,"abstract":"Wearable electroencephalography (EEG) systems can monitor neurological activity, enable new brain-computer interfaces and help users communicate with assistive devices. To facilitate ambulatory EEG recording, recent work has incorporated dry electrodes into wearable headsets and earbuds [1], [2]. Dry electrodes have superior ease-of-use over wet electrodes that require abrasive skin preparation. However, due to their high electrode-skin impedance (ESI), dry electrode wearables are susceptible to motion artifacts.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115697635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772837
Maitreyi Ashok, E. Levine, A. Chandrakasan
Analog to digital converters (ADCs) are necessary in most Internet of Things (loT) devices, to link the physical analog world to digital computation. Physical side channel attacks (SCAs) have been used to reconstruct information processed within digital integrated circuits in a variety of applications, through power or electromagnetic (EM) traces [1]. Furthermore, power SCAs have successfully decoded the analog information converted within Successive Approximation Register (SAR) ADCs [2], [3]. Previous works have proposed initial protections, such as switched-capacitor current equalization for power SCAs [2], random dithering for the reference charge [3], or general power side channel security using a stacked digital low dropout array and random noise injection [4]. Whereas power SCAs require cutting the power trace and introducing a shunt resistor for measurement, EM SCAs can effectively perform non-invasive measurements external to packaging (Fig. 1). However, supply current equalization is not effective against localized EM SCAs, which can probe currents directly above the ADC circuitry.
{"title":"Randomized Switching SAR (RS-SAR) ADC Protections for Power and Electromagnetic Side Channel Security","authors":"Maitreyi Ashok, E. Levine, A. Chandrakasan","doi":"10.1109/CICC53496.2022.9772837","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772837","url":null,"abstract":"Analog to digital converters (ADCs) are necessary in most Internet of Things (loT) devices, to link the physical analog world to digital computation. Physical side channel attacks (SCAs) have been used to reconstruct information processed within digital integrated circuits in a variety of applications, through power or electromagnetic (EM) traces [1]. Furthermore, power SCAs have successfully decoded the analog information converted within Successive Approximation Register (SAR) ADCs [2], [3]. Previous works have proposed initial protections, such as switched-capacitor current equalization for power SCAs [2], random dithering for the reference charge [3], or general power side channel security using a stacked digital low dropout array and random noise injection [4]. Whereas power SCAs require cutting the power trace and introducing a shunt resistor for measurement, EM SCAs can effectively perform non-invasive measurements external to packaging (Fig. 1). However, supply current equalization is not effective against localized EM SCAs, which can probe currents directly above the ADC circuitry.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129971857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772857
Bowen Wang, Haixin Song, W. Rhee, Zhihua Wang
The ultra-wideband (UWB) has recently been recognized as a revived wireless technology for short-range communication and fine ranging [1]–[3]. Even though the coherent UWB receiver achieves good sensitivity and high immunity against the narrowband interference (NBI), it suffers from high power and complex design for receiver synchronization. With a simple architecture and intermittent operation, the noncoherent UWB receiver achieves high energy efficiency [3], but the performance is vulnerable to the NBI. Because of new wireless standards such as 5G NR and Wi-Fi 6, having good NBI tolerance at 5-6GHz range becomes critical for UWB transceiver systems. The NBI tolerance of only -45dBm at 6GHz is reported in a recent noncoherent transceiver [4]. In this paper, we propose a 7.25-7.75GHz UWB transceiver that achieves good NBI tolerance as well as fine ranging with following features. Firstly, the uncertain-IF architecture is employed for the UWB receiver for the first time to achieve an optimum performance between energy efficiency and NBI tolerance. Unlike the uncertain-IF wake-up receiver (WuRX) for narrowband wireless standards [5], the quality (Q) factor requirement and the design complexity for the RF filter or IF filter could be significantly relaxed. To have good image rejection, a high LO frequency of 9GHz is chosen for down conversion, so that the image frequency can be beyond 10GHz. Secondly, the transceiver employs the synchronized on-off keying (S-OOK) modulation to mitigate the baseband synchronization issue [6]. Based on the S-OOK modulation, a pulse-triggered envelope/energy detector (PT-EVED) is designed in the receiver not only to automatically define an optimum integration window for good sensitivity during the communication mode but also to provide a fine ranging resolution during the ranging mode. Thirdly, a ΔΣ time-to-digital converter (TDC) is employed to have a digital-intensive ranging demodulation with a 1b oversampled output.
{"title":"A 7.25-7.75GHz 5.9mW UWB Transceiver with -23.8dBm NBI Tolerance and 1.5cm Ranging Accuracy Using Uncertain IF and Pulse-Triggered Envelope/Energy Detection","authors":"Bowen Wang, Haixin Song, W. Rhee, Zhihua Wang","doi":"10.1109/CICC53496.2022.9772857","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772857","url":null,"abstract":"The ultra-wideband (UWB) has recently been recognized as a revived wireless technology for short-range communication and fine ranging [1]–[3]. Even though the coherent UWB receiver achieves good sensitivity and high immunity against the narrowband interference (NBI), it suffers from high power and complex design for receiver synchronization. With a simple architecture and intermittent operation, the noncoherent UWB receiver achieves high energy efficiency [3], but the performance is vulnerable to the NBI. Because of new wireless standards such as 5G NR and Wi-Fi 6, having good NBI tolerance at 5-6GHz range becomes critical for UWB transceiver systems. The NBI tolerance of only -45dBm at 6GHz is reported in a recent noncoherent transceiver [4]. In this paper, we propose a 7.25-7.75GHz UWB transceiver that achieves good NBI tolerance as well as fine ranging with following features. Firstly, the uncertain-IF architecture is employed for the UWB receiver for the first time to achieve an optimum performance between energy efficiency and NBI tolerance. Unlike the uncertain-IF wake-up receiver (WuRX) for narrowband wireless standards [5], the quality (Q) factor requirement and the design complexity for the RF filter or IF filter could be significantly relaxed. To have good image rejection, a high LO frequency of 9GHz is chosen for down conversion, so that the image frequency can be beyond 10GHz. Secondly, the transceiver employs the synchronized on-off keying (S-OOK) modulation to mitigate the baseband synchronization issue [6]. Based on the S-OOK modulation, a pulse-triggered envelope/energy detector (PT-EVED) is designed in the receiver not only to automatically define an optimum integration window for good sensitivity during the communication mode but also to provide a fine ranging resolution during the ranging mode. Thirdly, a ΔΣ time-to-digital converter (TDC) is employed to have a digital-intensive ranging demodulation with a 1b oversampled output.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130390562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772789
Avishek Biswas, Hetul Sanghvi, M. Mehendale, G. Preet
Compute-In-Memory (CIM) is a promising approach to enable low power Machine Learning (ML) based applications on edge devices, since it significantly reduces data movement by embedding computations inside or near the memory, unlike traditional all-digital implementations. Conventional 6-transistor (6T) SRAM bit-cell based CIM approaches [1]–[3] suffer from bit-cell disturb issue due to accessing multiple cells in a column, limiting the dynamic voltage range allowed for analog dot-product (DP) computations. They are also highly prone to bit-cell discharge current (Icell) variation, degrading the overall accuracy of the neural network (NN) inference. Alternate approaches e.g. [4] requires a custom-designed 10T bitcell which consumes 2-3x larger cell area. To address these challenges, we present an area-efficient CIM approach (CIM-D6T) which uses compact 6T foundry bit-cells while achieving robustness to bit-cell Vt variations and eliminates any read disturb issues, improving the dynamic voltage range for DP. This is achieved by decoupling the 6T cell read from the analog DP computation. As shown in Fig. 1, a pair of extra metal capacitors (Cm) connected to the lines XAp, XAn are added over the SRAM column to store and process the analog voltages for the DP's. The 6T cells in a row are read locally and the read data values are used in the local LRW+MAVa circuit to discharge the analog voltage on the XAp/XAn capacitor to ground. These extra capacitors do not consume additional silicon area since they are implemented as metal comb capacitors over the existing SRAM array using higher metal layers. Fig. 1 shows the overall architecture of the proposed CIM half-array with 256x64 6T bit-cells, split into 16 sub-arrays each with 16 rows and 64 columns. Weights for different 3D filters in a given NN layer (output channel dimension) are mapped to a different sub-array. A group of 2 local columns with 16 rows in each form 1 mux-ed local column (LCOLmx) and hence, each sub-array has 32 parallel ports for input feature map (IFMP) values and the weights. Each LCOLmx along the vertical dimension share a single DAC, which converts a 6-b unsigned digital input (XIN[5:0]) to an analog voltage (0 to Vref). The same analog voltage (Va) is shared across all sub-arrays along a column.
{"title":"An area-efficient 6T-SRAM based Compute-In-Memory architecture with reconfigurable SAR ADCs for energy-efficient deep neural networks in edge ML applications","authors":"Avishek Biswas, Hetul Sanghvi, M. Mehendale, G. Preet","doi":"10.1109/CICC53496.2022.9772789","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772789","url":null,"abstract":"Compute-In-Memory (CIM) is a promising approach to enable low power Machine Learning (ML) based applications on edge devices, since it significantly reduces data movement by embedding computations inside or near the memory, unlike traditional all-digital implementations. Conventional 6-transistor (6T) SRAM bit-cell based CIM approaches [1]–[3] suffer from bit-cell disturb issue due to accessing multiple cells in a column, limiting the dynamic voltage range allowed for analog dot-product (DP) computations. They are also highly prone to bit-cell discharge current (Icell) variation, degrading the overall accuracy of the neural network (NN) inference. Alternate approaches e.g. [4] requires a custom-designed 10T bitcell which consumes 2-3x larger cell area. To address these challenges, we present an area-efficient CIM approach (CIM-D6T) which uses compact 6T foundry bit-cells while achieving robustness to bit-cell Vt variations and eliminates any read disturb issues, improving the dynamic voltage range for DP. This is achieved by decoupling the 6T cell read from the analog DP computation. As shown in Fig. 1, a pair of extra metal capacitors (Cm) connected to the lines XAp, XAn are added over the SRAM column to store and process the analog voltages for the DP's. The 6T cells in a row are read locally and the read data values are used in the local LRW+MAVa circuit to discharge the analog voltage on the XAp/XAn capacitor to ground. These extra capacitors do not consume additional silicon area since they are implemented as metal comb capacitors over the existing SRAM array using higher metal layers. Fig. 1 shows the overall architecture of the proposed CIM half-array with 256x64 6T bit-cells, split into 16 sub-arrays each with 16 rows and 64 columns. Weights for different 3D filters in a given NN layer (output channel dimension) are mapped to a different sub-array. A group of 2 local columns with 16 rows in each form 1 mux-ed local column (LCOLmx) and hence, each sub-array has 32 parallel ports for input feature map (IFMP) values and the weights. Each LCOLmx along the vertical dimension share a single DAC, which converts a 6-b unsigned digital input (XIN[5:0]) to an analog voltage (0 to Vref). The same analog voltage (Va) is shared across all sub-arrays along a column.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124065269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/CICC53496.2022.9772831
Supreet Jeloka, B. Cline, Shidhartha Das, Benoît Labbé, Alejandro Rico, R. Herberholz, Javier A. DeLaCruz, R. Mathur, S. Hung
As Moore's law fades and scaling of logic, memory and interconnects diverge, 3D integration technologies have become one of the primary approaches to maintaining performance gains in SoCs and SiPs. To fully exploit the system-level performance gains from 3D, we need to co-optimize the 3D system design for the 3D integration technology used, as well as solve the major physical design challenges of system partitioning, power delivery, thermals, and timing for 3D ICs. In this paper we will cover the system technology co-optimization and design challenges for 3D ICs from high-performance 3D CPU to many-core 3D system design.
{"title":"System technology co-optimization and design challenges for 3D IC","authors":"Supreet Jeloka, B. Cline, Shidhartha Das, Benoît Labbé, Alejandro Rico, R. Herberholz, Javier A. DeLaCruz, R. Mathur, S. Hung","doi":"10.1109/CICC53496.2022.9772831","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772831","url":null,"abstract":"As Moore's law fades and scaling of logic, memory and interconnects diverge, 3D integration technologies have become one of the primary approaches to maintaining performance gains in SoCs and SiPs. To fully exploit the system-level performance gains from 3D, we need to co-optimize the 3D system design for the 3D integration technology used, as well as solve the major physical design challenges of system partitioning, power delivery, thermals, and timing for 3D ICs. In this paper we will cover the system technology co-optimization and design challenges for 3D ICs from high-performance 3D CPU to many-core 3D system design.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117089401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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