Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155666
J. Reinert, M. Glazer
A 32-WORD BY 9-BIT Dual Address Register Stack (DAS) which uses an interleaving ECL cell technique to achieve address access speeds comparable to previously-reported speeds for single port ECL memories' will be described. The ECL LSI device has two independent memory ports, each having full data, read/write capability, parity function and-output storage register. In addition, as shown in the functional block diagram, Figure 1, an error circuit signals when operations defined as system errors; e.g., simultaneous write to the same address, are performed. The parallel word, dual port, organization, requiring 18 input/output ports with individual data paths and a large amount of support error detection circuitry necessitated a compact storage cell to achieve a reasonable die size. At the same time ECL memory access speeds had to be maintained to fit the primary application as a register file in the "I0800 bit slize processor family. An ECL memory cell approach looked attractive in that high density and fast read/write performance could be achieved. However, because of the RAM voltage shift addressing mode and the small ECL cell voltage differential, the effect of cross port address and bit line changes on data integrity was feared. The dual cell approach adopted avoids these problems by essentially interleaving two independent memories, with an addressing activated write over capability. The interleaving technique provides the advantages of high port-to-port disturb isolation, a proven memory cell for the basic element and small cell size by utilization of integrated device techniques and minimization of isolation areas. Figure 2 illustrates the merged nature of an ECL memory cell, with load resistor, Schottky diode and two transistors in one isolation region. In the dual cell all emitter followers are placed in a common N region to further reduce array area.
{"title":"A 32 x 9 ECL dual address register using an interleaving cell technique","authors":"J. Reinert, M. Glazer","doi":"10.1109/ISSCC.1977.1155666","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155666","url":null,"abstract":"A 32-WORD BY 9-BIT Dual Address Register Stack (DAS) which uses an interleaving ECL cell technique to achieve address access speeds comparable to previously-reported speeds for single port ECL memories' will be described. The ECL LSI device has two independent memory ports, each having full data, read/write capability, parity function and-output storage register. In addition, as shown in the functional block diagram, Figure 1, an error circuit signals when operations defined as system errors; e.g., simultaneous write to the same address, are performed. The parallel word, dual port, organization, requiring 18 input/output ports with individual data paths and a large amount of support error detection circuitry necessitated a compact storage cell to achieve a reasonable die size. At the same time ECL memory access speeds had to be maintained to fit the primary application as a register file in the \"I0800 bit slize processor family. An ECL memory cell approach looked attractive in that high density and fast read/write performance could be achieved. However, because of the RAM voltage shift addressing mode and the small ECL cell voltage differential, the effect of cross port address and bit line changes on data integrity was feared. The dual cell approach adopted avoids these problems by essentially interleaving two independent memories, with an addressing activated write over capability. The interleaving technique provides the advantages of high port-to-port disturb isolation, a proven memory cell for the basic element and small cell size by utilization of integrated device techniques and minimization of isolation areas. Figure 2 illustrates the merged nature of an ECL memory cell, with load resistor, Schottky diode and two transistors in one isolation region. In the dual cell all emitter followers are placed in a common N region to further reduce array area.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114278792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155635
D. Stamm, D. Budde, B. Morgan
{"title":"A single chip, highly integrated, user programmable microcomputer","authors":"D. Stamm, D. Budde, B. Morgan","doi":"10.1109/ISSCC.1977.1155635","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155635","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122009998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155691
Tich Dao, L. Russell, D. Preedy, E. McCluskey
THE USE OF THRESHOLD FUNCTIONS in logic circuits has been under investigation for some time. In fact several practical ECL implementations1 ,2,3 have been proposed in the past. Threshold functions are rarely used in practice. They appear only where conventional logic implementation is unfeasible; e.g., partially or totally symmetric functions of many variables. The threshold gate has binary inputs and binary outputs. Its internal parameters are input weights w1 . . . . wn and threshold T. The gate forms the linear weighted sum of inputs and compares it to the threshold. The resulting output is “1” if the sum exceeds the threshold, and “0” otherwise. With a wide range of weights and thresholds possible, many functions can be realized by a single threshold gate. The class of functions realizable is the well known linearly separable functions . 12L/MTL is in essence a current-mode direct-coupled transistor logic. Like ECL, 12L can implement the following functions which are essential to the threshold gates: (1) input repzication create replicas of an input through current-mirror imaging; (2) input weighting predetermine weights to replicas; (3) weighted sums form arithmetic sum of several weighted replicas; and (4) threshold detection determine if sum cxceeds a predetermined threshold. 12L implementation can be sufficiently insensitive to power source variations for practical use. The 12L current-mirror5constitutes the main building block. Figure 1 (a) shows the circuit diagram of a currentmirror producing 3 replicas of an input; ( b ) shows top view of the device. It is known that since all 12L NPN collectors operate in the inverted mode, they are independent of each other in the sense that any of them may be saturated without affecting the others. The inaccuracy of the mirror due to the low beta can be sufficiently corrected by undersizing the feedback collector with respect to the others. Limited input weighting is obtained 4
{"title":"Multilevel I2L with threshold gates","authors":"Tich Dao, L. Russell, D. Preedy, E. McCluskey","doi":"10.1109/ISSCC.1977.1155691","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155691","url":null,"abstract":"THE USE OF THRESHOLD FUNCTIONS in logic circuits has been under investigation for some time. In fact several practical ECL implementations1 ,2,3 have been proposed in the past. Threshold functions are rarely used in practice. They appear only where conventional logic implementation is unfeasible; e.g., partially or totally symmetric functions of many variables. The threshold gate has binary inputs and binary outputs. Its internal parameters are input weights w1 . . . . wn and threshold T. The gate forms the linear weighted sum of inputs and compares it to the threshold. The resulting output is “1” if the sum exceeds the threshold, and “0” otherwise. With a wide range of weights and thresholds possible, many functions can be realized by a single threshold gate. The class of functions realizable is the well known linearly separable functions . 12L/MTL is in essence a current-mode direct-coupled transistor logic. Like ECL, 12L can implement the following functions which are essential to the threshold gates: (1) input repzication create replicas of an input through current-mirror imaging; (2) input weighting predetermine weights to replicas; (3) weighted sums form arithmetic sum of several weighted replicas; and (4) threshold detection determine if sum cxceeds a predetermined threshold. 12L implementation can be sufficiently insensitive to power source variations for practical use. The 12L current-mirror5constitutes the main building block. Figure 1 (a) shows the circuit diagram of a currentmirror producing 3 replicas of an input; ( b ) shows top view of the device. It is known that since all 12L NPN collectors operate in the inverted mode, they are independent of each other in the sense that any of them may be saturated without affecting the others. The inaccuracy of the mirror due to the low beta can be sufficiently corrected by undersizing the feedback collector with respect to the others. Limited input weighting is obtained 4","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"283 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123268419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155636
R. Plassche, R. Grift
{"title":"A five digit A/D converter","authors":"R. Plassche, R. Grift","doi":"10.1109/ISSCC.1977.1155636","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155636","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"13 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120834921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155676
G. Heilmeier
AN ATTEMPT will not be made to outline in detail where solidstate technology is headed, rather to explore some trends and formulate some questions. These questions, whose answers are deeply rooted in technology, could, in my opinion, become the national security issues of the 1980’s. Solid-state technology will play a major role in answering these questions as they relate to the implications of technological breakthroughs in space, under the sea, and on the battlefield. The common denominator of such questions in the seemingly diverse areas as space-based high energy lasers, infrared satellite reconnaissance, anti-submarine warfare, really smart weapons, and command and control can be found in two areas to which the solid-state device community has made major contributions: infrared detection and computational plenty.
{"title":"Emerging opportunities to convert innovations into future D o D markets","authors":"G. Heilmeier","doi":"10.1109/ISSCC.1977.1155676","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155676","url":null,"abstract":"AN ATTEMPT will not be made to outline in detail where solidstate technology is headed, rather to explore some trends and formulate some questions. These questions, whose answers are deeply rooted in technology, could, in my opinion, become the national security issues of the 1980’s. Solid-state technology will play a major role in answering these questions as they relate to the implications of technological breakthroughs in space, under the sea, and on the battlefield. The common denominator of such questions in the seemingly diverse areas as space-based high energy lasers, infrared satellite reconnaissance, anti-submarine warfare, really smart weapons, and command and control can be found in two areas to which the solid-state device community has made major contributions: infrared detection and computational plenty.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"51 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129764592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155713
F. Sechi, Ho Huang, V. Riginos
being developed are: 0.5W of output power with a two-carrier intermodulation ratio (C/I) of 40 dB, 8% efficiency and 20-dB gain over the 3.7 to 4.2-GHz frequency range. Presently, only one of the two power amplifiers composing the power stage of the multistage amplifier has been completed and will be described. The power amplifier provides approximately an output power of 300mW with a C/I of 40 dB, an efficiency of 14% and a gain of 13 dB over the 3.7 to 4.2-GHz frequency range. The MESFETs are five-cell devices featuring a gatelength of 1.2 pm and a total gate width of 3000 pm'. The saturated output power at 4.2 GHz is about 1.1W with an associated gain of 10 dB and a small-signal gain of 13 dB. The output tuning for lowest intermodulation distortion differs from the tuning for either maximum saturated output power or for maximum gain; thus a systematic characterization of the active device in terms of constant C/I and constant output power contours was needed. This characterization, the key for the design of highperformance broadband linear amplifiers, was obtained with the aid of a computer-controlled tuner and a spectrum analyzer both connected at the output of the device under test. An example of these data is shown in Figure 1. For any value of C/I there exists a value of load impedance (closest to the center of the contours) that provides the maximum output power. Similar data, obtained at various frequencies and at various RF input powers, made it possible to define the load impedance as a function of frequency for best intermodulation performance. The chosen load impedance for optimum intermodulation performance varies from lO+jO 0 at 3.7 GHz to 10+j2.5 0 at 4.2 GHz. The output circuit, shown in Figure 2, was designed as a double h/4 transformer. It was computer optimized so that its impedance follows closely the optimum load impedance over the operating bandwidth. The circuit was then realized with microstrip lines on a 25-mil thick A1203 substrate. The input tuning circuit matches the low input impedance of the device, approximately 3 a, to the 50 0 of the generator. The The major design goals of a multistage MESFET amplifier
{"title":"High-efficiency MESFET linear amplifier operating at 4 GHz","authors":"F. Sechi, Ho Huang, V. Riginos","doi":"10.1109/ISSCC.1977.1155713","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155713","url":null,"abstract":"being developed are: 0.5W of output power with a two-carrier intermodulation ratio (C/I) of 40 dB, 8% efficiency and 20-dB gain over the 3.7 to 4.2-GHz frequency range. Presently, only one of the two power amplifiers composing the power stage of the multistage amplifier has been completed and will be described. The power amplifier provides approximately an output power of 300mW with a C/I of 40 dB, an efficiency of 14% and a gain of 13 dB over the 3.7 to 4.2-GHz frequency range. The MESFETs are five-cell devices featuring a gatelength of 1.2 pm and a total gate width of 3000 pm'. The saturated output power at 4.2 GHz is about 1.1W with an associated gain of 10 dB and a small-signal gain of 13 dB. The output tuning for lowest intermodulation distortion differs from the tuning for either maximum saturated output power or for maximum gain; thus a systematic characterization of the active device in terms of constant C/I and constant output power contours was needed. This characterization, the key for the design of highperformance broadband linear amplifiers, was obtained with the aid of a computer-controlled tuner and a spectrum analyzer both connected at the output of the device under test. An example of these data is shown in Figure 1. For any value of C/I there exists a value of load impedance (closest to the center of the contours) that provides the maximum output power. Similar data, obtained at various frequencies and at various RF input powers, made it possible to define the load impedance as a function of frequency for best intermodulation performance. The chosen load impedance for optimum intermodulation performance varies from lO+jO 0 at 3.7 GHz to 10+j2.5 0 at 4.2 GHz. The output circuit, shown in Figure 2, was designed as a double h/4 transformer. It was computer optimized so that its impedance follows closely the optimum load impedance over the operating bandwidth. The circuit was then realized with microstrip lines on a 25-mil thick A1203 substrate. The input tuning circuit matches the low input impedance of the device, approximately 3 a, to the 50 0 of the generator. The The major design goals of a multistage MESFET amplifier","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132762037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155656
C. Hewes, M. De Wit
{"title":"NMOS Tone Generator","authors":"C. Hewes, M. De Wit","doi":"10.1109/ISSCC.1977.1155656","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155656","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"457 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116503293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155629
W. Herndon, W. Ho, R. Ramirez
is shown in Figure 1. By eliminatingemitter base spacing, device size is significantly reduced, resulting in a memory cell size of only three square mils per cell, and a 4K RAM chip of 23,650 square mils. A photomicrograph of the chip appears in Figure 2. The small size compares very favorably with the state-ofthe-art MOS static RAM cell size. Furthermore, parasitic capacitances are reduced, improving memory performance. The cell has an emitter base capacitance of 0.05 pF, collector base capacitance of 0.09pF and collector substrate capacitance of 0.255pF. The architecture is conventional. A block diagram of the chip is shown in Figure 4. A chip select input is provided for logic flexibility. The read and write operat ics are controlled by the state of the active low write enable, WE. With R7E held low and the chip selected, the data at Din is written into the addressed location To read, WE is held high and the chip selected. Data in the specified location are presented at the data output. ECL design techniques are used throughout the internal circuitry for better speed power product. Design features are shown in Figure 5. Word line discharge circuitry provides fast word line switching. Each bit line current sink is shared by 4 bit line pairs to reduce power. Performance and power allocation of developmental samples manufactured to date are summarized in Table I and Table 11. With typical address access time of around 35 ns, these devices should find application in high performance main memory in addition to the more traditional role of scratch pad memories. Cross section of a typical walled emitter Isoplanar transistor
{"title":"A 4096 x 1 static bipolar RAM","authors":"W. Herndon, W. Ho, R. Ramirez","doi":"10.1109/ISSCC.1977.1155629","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155629","url":null,"abstract":"is shown in Figure 1. By eliminatingemitter base spacing, device size is significantly reduced, resulting in a memory cell size of only three square mils per cell, and a 4K RAM chip of 23,650 square mils. A photomicrograph of the chip appears in Figure 2. The small size compares very favorably with the state-ofthe-art MOS static RAM cell size. Furthermore, parasitic capacitances are reduced, improving memory performance. The cell has an emitter base capacitance of 0.05 pF, collector base capacitance of 0.09pF and collector substrate capacitance of 0.255pF. The architecture is conventional. A block diagram of the chip is shown in Figure 4. A chip select input is provided for logic flexibility. The read and write operat ics are controlled by the state of the active low write enable, WE. With R7E held low and the chip selected, the data at Din is written into the addressed location To read, WE is held high and the chip selected. Data in the specified location are presented at the data output. ECL design techniques are used throughout the internal circuitry for better speed power product. Design features are shown in Figure 5. Word line discharge circuitry provides fast word line switching. Each bit line current sink is shared by 4 bit line pairs to reduce power. Performance and power allocation of developmental samples manufactured to date are summarized in Table I and Table 11. With typical address access time of around 35 ns, these devices should find application in high performance main memory in addition to the more traditional role of scratch pad memories. Cross section of a typical walled emitter Isoplanar transistor","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134498432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155725
J. Cooper, J. Copeland, R. Krambeck, D. Stanzione, L. Thomas
THIS REPORT will cover an 8-bit microprocessorX fabricated with a silicon-gate CMOS technology and packaged in a 40-pin DIP. It embodies several architectural innovations and an extended instruction set affording exceptional computing power. Although the fabrication technology is CMOS, it was found that the use of non-complementary structures for certain portions of the logic resulted in a device with the functional density of NMOS, but with power dissipation and internal noise margins approaching that of CMOS. It was recognized early in the development program that an important measure of the computing power of a microprocessor is its efficiency in accessing memory. Accordingly, emphasis was placed on the efficient use of memory. A 16-bit address arithmetic unit (AAU) was provided on-chip to allow address calculations to take place in parallel with data manipulations. To further enhance the computing power, it was decided that the area limitation on the number of user registers which could be implemented on-chip should be avoided by placing all user registers in external RAM, as illustrated in Figure 1. One register set consists of 1 6 16-bit registers. Each register can be used as a 16-bit memory addressing register, a 16-bit accumulator, or an 8-bit accumulator. The source and destination operands of dyadic instructions are pointed to within the register set by an 8-bit DS pointer supplied. as the second byte of the instruction. The DS pointer contains a 4-bit D nibble identifying the destination operand within the register set and a 4-bit S nibble identifying the source operand. The location of the current rcgister set in external RAM is identified by a 16-bit register pointer (RP) maintained on-chip. Since the register pointer is under software control, the location of the register set in external RAM can be changcd on the fly. This makes it possible to form a stack of register sets in RAM, thus saving the current program arguments when executing single or nested subroutine calls. A special instruction allows the programmer to overlap successive rcgister sets by 4,8, or 12 words, thus effecting automatic sharing of 4, 8, or 1 2 arguments between a calling routine and its subroutine. To make efficient use of the large number of user registers available in the external register space, the instruction set provides eight addressing modes for each dyadic instruction and four addressing modes for each monadic instruction. In addition, a novel extension of the instruction set allows up to four distinct sub-modes within each addressing mode, bringing the total number of useablc dyadic modes to 21. Counting the various modes and sub-modes, the processor executes more than 400 unique instructions, some of which require up to 21 successive machine states to complete. Notable among these is a branchon-bit instruction which allows conditional branching on any
{"title":"A CMOS microprocessor for telecommunications applications","authors":"J. Cooper, J. Copeland, R. Krambeck, D. Stanzione, L. Thomas","doi":"10.1109/ISSCC.1977.1155725","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155725","url":null,"abstract":"THIS REPORT will cover an 8-bit microprocessorX fabricated with a silicon-gate CMOS technology and packaged in a 40-pin DIP. It embodies several architectural innovations and an extended instruction set affording exceptional computing power. Although the fabrication technology is CMOS, it was found that the use of non-complementary structures for certain portions of the logic resulted in a device with the functional density of NMOS, but with power dissipation and internal noise margins approaching that of CMOS. It was recognized early in the development program that an important measure of the computing power of a microprocessor is its efficiency in accessing memory. Accordingly, emphasis was placed on the efficient use of memory. A 16-bit address arithmetic unit (AAU) was provided on-chip to allow address calculations to take place in parallel with data manipulations. To further enhance the computing power, it was decided that the area limitation on the number of user registers which could be implemented on-chip should be avoided by placing all user registers in external RAM, as illustrated in Figure 1. One register set consists of 1 6 16-bit registers. Each register can be used as a 16-bit memory addressing register, a 16-bit accumulator, or an 8-bit accumulator. The source and destination operands of dyadic instructions are pointed to within the register set by an 8-bit DS pointer supplied. as the second byte of the instruction. The DS pointer contains a 4-bit D nibble identifying the destination operand within the register set and a 4-bit S nibble identifying the source operand. The location of the current rcgister set in external RAM is identified by a 16-bit register pointer (RP) maintained on-chip. Since the register pointer is under software control, the location of the register set in external RAM can be changcd on the fly. This makes it possible to form a stack of register sets in RAM, thus saving the current program arguments when executing single or nested subroutine calls. A special instruction allows the programmer to overlap successive rcgister sets by 4,8, or 12 words, thus effecting automatic sharing of 4, 8, or 1 2 arguments between a calling routine and its subroutine. To make efficient use of the large number of user registers available in the external register space, the instruction set provides eight addressing modes for each dyadic instruction and four addressing modes for each monadic instruction. In addition, a novel extension of the instruction set allows up to four distinct sub-modes within each addressing mode, bringing the total number of useablc dyadic modes to 21. Counting the various modes and sub-modes, the processor executes more than 400 unique instructions, some of which require up to 21 successive machine states to complete. Notable among these is a branchon-bit instruction which allows conditional branching on any","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121991760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155684
W. Engl, H. Lehning
THE DEVELOPMENT of a junction isolated thyristor for analog speech path switching has resulted in a novel conception of monolithic integration of large crosspoint arrays for Private Branch Exchange (PBX) application. Despite stringent technical requirements such as excellent transmission properties and system characteristics, the demand for an extremely economical solution have been fulfilled. This has been achieved by using a standard low-cost bipolar technology with conventional junction isolation and a conception based on LSI principles. The thyristor to be described (Figure l/Table 1 ) is a switching element in a crosspoint circuit comprising a 5 x 5 ~ 2 switching matrix and an on-chip selection control logic in 12L.
{"title":"Junction isolated thyristors for PBX switching","authors":"W. Engl, H. Lehning","doi":"10.1109/ISSCC.1977.1155684","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155684","url":null,"abstract":"THE DEVELOPMENT of a junction isolated thyristor for analog speech path switching has resulted in a novel conception of monolithic integration of large crosspoint arrays for Private Branch Exchange (PBX) application. Despite stringent technical requirements such as excellent transmission properties and system characteristics, the demand for an extremely economical solution have been fulfilled. This has been achieved by using a standard low-cost bipolar technology with conventional junction isolation and a conception based on LSI principles. The thyristor to be described (Figure l/Table 1 ) is a switching element in a crosspoint circuit comprising a 5 x 5 ~ 2 switching matrix and an on-chip selection control logic in 12L.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124670305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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