Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155719
J. Gewartowski
High-efficiency diodes of early design were relatively noisy, wi th noise measures in excess of 50 dB. Recent designs have achieved noise measures about 10 dB lower. Unlike the uniformly-doped IMPATT diodes, the noise measure a t low R F levels does not improve very much, and hence, the high-efficiency diode may not be suitable for an application where the noise performance is critical. This has resulted in amplifier designs where flat-profile diodes are used for the first stages and high-efficiency diodes are used for the power stages.
{"title":"Progress with high efficiency IMPATT diodes","authors":"J. Gewartowski","doi":"10.1109/ISSCC.1977.1155719","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155719","url":null,"abstract":"High-efficiency diodes of early design were relatively noisy, wi th noise measures in excess of 50 dB. Recent designs have achieved noise measures about 10 dB lower. Unlike the uniformly-doped IMPATT diodes, the noise measure a t low R F levels does not improve very much, and hence, the high-efficiency diode may not be suitable for an application where the noise performance is critical. This has resulted in amplifier designs where flat-profile diodes are used for the first stages and high-efficiency diodes are used for the power stages.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125212688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155680
W. Mattheus, R. Mertens
r VlODE ,LS WHICH characterize 12L inverters have been presented, as well as methods to determine the model parameters’ >’. Since these models rely on the charge control principles, a quasi-static charge distribution is assumed during transient analysis. This reflectsessentially in a one-pole approximation for the small signal input impedance of the device. The deviation of this approximation from reality is a valid measure for the applicability of the charge control model, even though the latter will be used in switching problem. Measurements of the small signal input impedance of an 12L inverter a t medium and high power levels, result in curves which strongly deviate from the -20 dB/decade rolloff of the one pole approximation; Figure 1. This indicates that the chargecontrol principles are not a priori valid. It has been reported that the charge distribution in the Y direction (perpendicular to the surface) is in principle non quasi-static in the epitaxial layer3. However, straightforward analysis proves that for realistic values of the epitaxial width W and of the NN’ interface recombination velocity s, such that the product sW is much smaller than the diffusion constant of holes in the epitaxial region, the one pole model remains a good approximation in the measured frequency range4. The influence of the distributed nature of the base resistance in the X direction constitutes a second source of non quasi-static behavior; Figure 2. The general distributed network (Figure 3 insert) can be analysed by introducing the following assumptions. ( I ) The overall impedance RB and the overall small signal admittance r, and C, are uniform over the length L of the distributed network. This implies that lateral variations are ruled out by adopting mean values for RB, r, and C,. (2) The voltage dependence of r and C, along the base is neglected for the ac analysis. Computer simulations have shown that this condition limits the applicability of the results t o moderate dc biasing, such that r, < RB. ?
{"title":"Modeling the dynamic behavior of the I2L inverter","authors":"W. Mattheus, R. Mertens","doi":"10.1109/ISSCC.1977.1155680","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155680","url":null,"abstract":"r VlODE ,LS WHICH characterize 12L inverters have been presented, as well as methods to determine the model parameters’ >’. Since these models rely on the charge control principles, a quasi-static charge distribution is assumed during transient analysis. This reflectsessentially in a one-pole approximation for the small signal input impedance of the device. The deviation of this approximation from reality is a valid measure for the applicability of the charge control model, even though the latter will be used in switching problem. Measurements of the small signal input impedance of an 12L inverter a t medium and high power levels, result in curves which strongly deviate from the -20 dB/decade rolloff of the one pole approximation; Figure 1. This indicates that the chargecontrol principles are not a priori valid. It has been reported that the charge distribution in the Y direction (perpendicular to the surface) is in principle non quasi-static in the epitaxial layer3. However, straightforward analysis proves that for realistic values of the epitaxial width W and of the NN’ interface recombination velocity s, such that the product sW is much smaller than the diffusion constant of holes in the epitaxial region, the one pole model remains a good approximation in the measured frequency range4. The influence of the distributed nature of the base resistance in the X direction constitutes a second source of non quasi-static behavior; Figure 2. The general distributed network (Figure 3 insert) can be analysed by introducing the following assumptions. ( I ) The overall impedance RB and the overall small signal admittance r, and C, are uniform over the length L of the distributed network. This implies that lateral variations are ruled out by adopting mean values for RB, r, and C,. (2) The voltage dependence of r and C, along the base is neglected for the ac analysis. Computer simulations have shown that this condition limits the applicability of the results t o moderate dc biasing, such that r, < RB. ?","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126127684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155733
E. Belohoubek
Power levels in excess of 2 W a t X-band, 1/2 W a t Ku-band and 1/5 W a t 22 GHz have been reported. Additionally, various research efforts currently under way have goals of 5 W, 1 W and 1/2 W a t these frequencies, respectively. These goals are entirely realistic and will offer the circuit designer a low voltage, 3-terminal source o f microwave power from a relatively simple solid-state device. Although one of.the chief pacing items in this area is the ability to handle ever-increasing power levels, the GaAs FET has a number of other very desirable system incentives. Typical power added efficiencies of 30% at X-band down to 9% a t 22 GHz have been demonstrated. The FET exhibits fairly linear operation t o within 1 dB of i ts saturation level, with two-signal carrierlintermodulation ratios of 20 to 30 dB. They also offer low AM/PM conversion and ease of temperature stabilization. Finally, the old gremlin, narrow bandwidth, associated with many other solid state power devices, is absent. Octave bandwidth performance has been readily demonstrated at moderately high power levels.
据报道，功率水平超过2w / t x波段，1/ 2w / t ku波段和1/ 5w / t 22ghz。此外，目前正在进行的各种研究工作的目标分别是这些频率的5w, 1w和1/ 2w。这些目标是完全现实的，将为电路设计者提供一个低电压，三端微波功率源从一个相对简单的固态器件。虽然其中之一。在这一领域的主要步伐项目是处理不断增加的功率水平的能力，GaAs FET还有许多其他非常理想的系统激励。典型的功率增加效率在x波段为30%，在22ghz下为9%。FET在其饱和电平的1 dB范围内表现出相当的线性工作，双信号载波互调比为20至30 dB。它们还提供低AM/PM转换和易于温度稳定。最后，与许多其他固态功率器件相关的窄带宽这一老难题也不复存在了。在中等高功率水平下，八度频宽性能已经得到了很好的证明。
{"title":"Microwave GaAs power FETs","authors":"E. Belohoubek","doi":"10.1109/ISSCC.1977.1155733","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155733","url":null,"abstract":"Power levels in excess of 2 W a t X-band, 1/2 W a t Ku-band and 1/5 W a t 22 GHz have been reported. Additionally, various research efforts currently under way have goals of 5 W, 1 W and 1/2 W a t these frequencies, respectively. These goals are entirely realistic and will offer the circuit designer a low voltage, 3-terminal source o f microwave power from a relatively simple solid-state device. Although one of.the chief pacing items in this area is the ability to handle ever-increasing power levels, the GaAs FET has a number of other very desirable system incentives. Typical power added efficiencies of 30% at X-band down to 9% a t 22 GHz have been demonstrated. The FET exhibits fairly linear operation t o within 1 dB of i ts saturation level, with two-signal carrierlintermodulation ratios of 20 to 30 dB. They also offer low AM/PM conversion and ease of temperature stabilization. Finally, the old gremlin, narrow bandwidth, associated with many other solid state power devices, is absent. Octave bandwidth performance has been readily demonstrated at moderately high power levels.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127501282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155688
M. Declerco, T. Laurent
The authors discuss two problems which arise in the practical implementation of DMOS to enhancement-depletion (E/D) logic. The first problem relates the optimum design of DMOS logic gates, for which some particular features of the devices must be taken into account. First, the fact that typical short-channel characteristics are obtained from a full-size device deeply modifies the relation existing between electrical characteristics of a gate and its real estate. Second, some deviations from the simplified theory, such as carrier velocity saturation occurring mainly in the driver transistor, must be taken into account when computing the inverter characteristics. Starting from simple mathematical expressions, design rules have been developed and compared to conventional E/D logic. Two design regions, corresponding to two different options in the technology, may be distinguished for DMOS logic.
{"title":"Design and technology for DMOS E/D logic","authors":"M. Declerco, T. Laurent","doi":"10.1109/ISSCC.1977.1155688","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155688","url":null,"abstract":"The authors discuss two problems which arise in the practical implementation of DMOS to enhancement-depletion (E/D) logic. The first problem relates the optimum design of DMOS logic gates, for which some particular features of the devices must be taken into account. First, the fact that typical short-channel characteristics are obtained from a full-size device deeply modifies the relation existing between electrical characteristics of a gate and its real estate. Second, some deviations from the simplified theory, such as carrier velocity saturation occurring mainly in the driver transistor, must be taken into account when computing the inverter characteristics. Starting from simple mathematical expressions, design rules have been developed and compared to conventional E/D logic. Two design regions, corresponding to two different options in the technology, may be distinguished for DMOS logic.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128191597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155728
J. Nishizawa, B. Wilamowski
SOLID-STATE CIRCUITS are designed to minimize both delay time and operational power. The product of these is thought t o be constant, represented by a specific figure for each type of integrated circuit. The 12L structure has been shown to operate with the lowest switching energy’. The power efficiency of the Vertical Injection Logic (VIL) structure shows a further improvement, by a factor of two. However, its fabrication requires the use of 7-8 masks’. A new logic circuit structure is proposed Static Induction Transistor Logic (SITL) utilizing the static induction transistor ( SIT)3. This logic circuit permits a further reduction in the power-delay time product (theoretically 6 x and experimentally, one order of magnitude). In the case of 12L, it is made by a 3 or 4-mask technology. The packing density can be as high as 1000 gates/cm2. In this logic structure, the SITS are used as the output transistors and the lateral bipolar PNP transistor is used as the injector, as usual, as shown in Figure 1. The SIT consists of Nt drains on the top surface of the Nepitaxial layer, a Pt gate configured on both sides of the drain on the same surface and the space charge layer formed surrounding the drain regions, Nchannels penetrating the gate region below the drains and the N+ source substrate. The channels are about 2-3 p m in diamcter and are formed by lateral P-type diffusion. The fabrication process in this case is as follows. The Nepitaxial layer is grown on the N+ substrate, having a carrier concentration of 2-3 x 1013 cm-3 and a thickness of 4-5 pm. After oxidation and photolithography, B-diffused layers were formed as the gate regions of the SIT and the emitter of the injector (the lateral transistor), followed by the second oxidation. Then, the Nf -diffusion layers are formed as drain regions, followed by the opening of contact holes in the Si02 film, using the third photolithography. After A1 evaporation, the A1 film is selectively etched, and the ring oscillator formed, as shown in Figure 2.
{"title":"Integrated logic - Static induction transistor logic","authors":"J. Nishizawa, B. Wilamowski","doi":"10.1109/ISSCC.1977.1155728","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155728","url":null,"abstract":"SOLID-STATE CIRCUITS are designed to minimize both delay time and operational power. The product of these is thought t o be constant, represented by a specific figure for each type of integrated circuit. The 12L structure has been shown to operate with the lowest switching energy’. The power efficiency of the Vertical Injection Logic (VIL) structure shows a further improvement, by a factor of two. However, its fabrication requires the use of 7-8 masks’. A new logic circuit structure is proposed Static Induction Transistor Logic (SITL) utilizing the static induction transistor ( SIT)3. This logic circuit permits a further reduction in the power-delay time product (theoretically 6 x and experimentally, one order of magnitude). In the case of 12L, it is made by a 3 or 4-mask technology. The packing density can be as high as 1000 gates/cm2. In this logic structure, the SITS are used as the output transistors and the lateral bipolar PNP transistor is used as the injector, as usual, as shown in Figure 1. The SIT consists of Nt drains on the top surface of the Nepitaxial layer, a Pt gate configured on both sides of the drain on the same surface and the space charge layer formed surrounding the drain regions, Nchannels penetrating the gate region below the drains and the N+ source substrate. The channels are about 2-3 p m in diamcter and are formed by lateral P-type diffusion. The fabrication process in this case is as follows. The Nepitaxial layer is grown on the N+ substrate, having a carrier concentration of 2-3 x 1013 cm-3 and a thickness of 4-5 pm. After oxidation and photolithography, B-diffused layers were formed as the gate regions of the SIT and the emitter of the injector (the lateral transistor), followed by the second oxidation. Then, the Nf -diffusion layers are formed as drain regions, followed by the opening of contact holes in the Si02 film, using the third photolithography. After A1 evaporation, the A1 film is selectively etched, and the ring oscillator formed, as shown in Figure 2.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122176763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155659
J. Amoss, W. Cox, L. Lopez
MANY IMPROVEMENTS have been made in the instantaneous and tuning bandwidths o f certain microwave components in the past few years. In general, these improvements can bc directly attributed to circuit simplifications involving: elimination of dispersive transmission media, whenever possible, climination of distributed components of dimcnsions that arc appreciable fractions of a wavclcngth, and replacement of thcsc: elements with lumped or nearly lumped tuning and matching elements. This paper will describe a varactor-tuned Gunn oscillator which was designed with these factors considered of utmost importance in the overall design.
{"title":"A multiband lumped-element varactor-tuned Gunn oscillator","authors":"J. Amoss, W. Cox, L. Lopez","doi":"10.1109/ISSCC.1977.1155659","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155659","url":null,"abstract":"MANY IMPROVEMENTS have been made in the instantaneous and tuning bandwidths o f certain microwave components in the past few years. In general, these improvements can bc directly attributed to circuit simplifications involving: elimination of dispersive transmission media, whenever possible, climination of distributed components of dimcnsions that arc appreciable fractions of a wavclcngth, and replacement of thcsc: elements with lumped or nearly lumped tuning and matching elements. This paper will describe a varactor-tuned Gunn oscillator which was designed with these factors considered of utmost importance in the overall design.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115713426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155663
R. Pashley, W. Owen, K. Kokkonen, R. Jecmen, A. Ebel, C. Ahlquist, P. Schoen
combining MOS device scaling’ with on chip substrate bias generation’. By reducing the physical parameters of the MOS device by a fixed scaling factor, circuit density and performance were increased while decreasing active circuit power. The advanced technology uses polysilicon ate lengths under 4 p and a gate oxide thickness less than 1000 R . Shallow junctions ( < l p ) are obtained by using arsenic as the source-drain diffusant. In addition, oxide isolation and depletion load processing are employed to improve further circuit performance and density. Substrate bias is used to reduce device body effect The high performance of the MOS memory was achieved by circuit is a simple differential amplifier with dc feedback to provide for process and temperature compensation. The powerdown mode is controlled by chip enable. During powerdown (CE high), the memory array is completely deselected and the column and I/O buss is reset to a threshold below supply voltage. By balancing the internal circuitry during powerdown, it is possible to overcome the additional chip enable powerup delay and obtain a powerup access time equal to the address access time; Figure 3. Typically, the RAM accesses in 45ns and has an active power dissipation of 500mW. Powerup does not display current spikes typical of dynamic circuitry and powerdown takes less than 3011s. A summary of the device characteristics is presented in Table 1.
将MOS器件缩放与片上衬底偏置相结合。通过以固定的比例因子减小MOS器件的物理参数，在降低有源电路功率的同时提高了电路密度和性能。这项先进的技术使用了长度小于4p的多晶硅和厚度小于1000r的栅极氧化物。用砷作为源-漏扩散剂可得到浅结(< l p)。此外，采用氧化物隔离和耗尽负载处理进一步提高电路性能和密度。利用衬底偏压减小器件体效应，实现了MOS存储器的高性能，电路是一个简单的差分放大器，具有直流反馈，以提供过程和温度补偿。下电模式由芯片使能控制。在下电(CE高)期间，存储器阵列被完全取消选择，列和I/O总线被重置为低于电源电压的阈值。通过在下电期间平衡内部电路，可以克服附加芯片使能上电延迟并获得等于地址访问时间的上电访问时间;图3。通常，RAM存取时间为45ns，有源功耗为500mW。上电不显示电流尖峰的典型动态电路和下电需要少于3011秒。表1给出了设备特性的总结。
{"title":"A high performance 4K static RAM fabricated with an advanced MOS technology","authors":"R. Pashley, W. Owen, K. Kokkonen, R. Jecmen, A. Ebel, C. Ahlquist, P. Schoen","doi":"10.1109/ISSCC.1977.1155663","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155663","url":null,"abstract":"combining MOS device scaling’ with on chip substrate bias generation’. By reducing the physical parameters of the MOS device by a fixed scaling factor, circuit density and performance were increased while decreasing active circuit power. The advanced technology uses polysilicon ate lengths under 4 p and a gate oxide thickness less than 1000 R . Shallow junctions ( < l p ) are obtained by using arsenic as the source-drain diffusant. In addition, oxide isolation and depletion load processing are employed to improve further circuit performance and density. Substrate bias is used to reduce device body effect The high performance of the MOS memory was achieved by circuit is a simple differential amplifier with dc feedback to provide for process and temperature compensation. The powerdown mode is controlled by chip enable. During powerdown (CE high), the memory array is completely deselected and the column and I/O buss is reset to a threshold below supply voltage. By balancing the internal circuitry during powerdown, it is possible to overcome the additional chip enable powerup delay and obtain a powerup access time equal to the address access time; Figure 3. Typically, the RAM accesses in 45ns and has an active power dissipation of 500mW. Powerup does not display current spikes typical of dynamic circuitry and powerdown takes less than 3011s. A summary of the device characteristics is presented in Table 1.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122418126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155716
R. Wong, J. Chen
{"title":"A power bipolar transistor optimized for linear performance with octave capability","authors":"R. Wong, J. Chen","doi":"10.1109/ISSCC.1977.1155716","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155716","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116391470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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