Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155732
W. Lattin
{"title":"Low end microprocessors: Will there be an industry standard?","authors":"W. Lattin","doi":"10.1109/ISSCC.1977.1155732","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155732","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121559629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155638
C. Erickson, H. Hingarh, R. Moeckel, D. Wilnai
A SINGLE-CHIP 16-BIT MICROPROCESSOR with fixed point arithmetic using 2’s complement notation will be described. It executes the same instruction set as the NOVA line of minicomputers and has comparable performance and is packaged in a 40-pin DIP. Figure 1 is the logic symbol of the processor and shows various data and control lines noted below. (1)lnformation Bus IBo-IB15 is a 16-bit bidirectional 3-state bus used to transfer address, data, and instruction information between the processor and main memory, and to transfer data to and from I/O devices. (2)S ta tus Lines RUN, CARRY and INT.ON are used to convey the status information of the processor mainly for display on an operator console. (3) Operator Console Control Co-C3, RESET. Operator can control the operation of the processor by means of 4 coded lines (Co-3) and a RESET line. (4)lnput/Output Control 00.01, INT. REQ., DCH. REQ. Processor controls 1/0 devices by means of two coded control lines (00,Ol)I/O devices can interrupt the normal program flow by activating the INT. REQ. line and they can gain direct access to main memory bv activating the DCII. REQ. line. (5)!kmory Control Mo-M~, MBSY. Processor controls thc main memory by means o f 3 open collcctor control lines (Mo, M1, M2). It synchronizes itself to the memory cycle time indicated by the MBSY signal. ( 6 ) Timing SYN, CP, XTL, CIKOUT. Processor can operate with an on-chip oscillator when a crystal is tied between (CP) and (XTL,) or i t can operatc from an external clock (CP). Processor generates a synchronization signal (SYN) for all external devices. The internal clock is available to the outside world on (CLKOUT).
{"title":"A 16-bit monolithic I3L processor","authors":"C. Erickson, H. Hingarh, R. Moeckel, D. Wilnai","doi":"10.1109/ISSCC.1977.1155638","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155638","url":null,"abstract":"A SINGLE-CHIP 16-BIT MICROPROCESSOR with fixed point arithmetic using 2’s complement notation will be described. It executes the same instruction set as the NOVA line of minicomputers and has comparable performance and is packaged in a 40-pin DIP. Figure 1 is the logic symbol of the processor and shows various data and control lines noted below. (1)lnformation Bus IBo-IB15 is a 16-bit bidirectional 3-state bus used to transfer address, data, and instruction information between the processor and main memory, and to transfer data to and from I/O devices. (2)S ta tus Lines RUN, CARRY and INT.ON are used to convey the status information of the processor mainly for display on an operator console. (3) Operator Console Control Co-C3, RESET. Operator can control the operation of the processor by means of 4 coded lines (Co-3) and a RESET line. (4)lnput/Output Control 00.01, INT. REQ., DCH. REQ. Processor controls 1/0 devices by means of two coded control lines (00,Ol)I/O devices can interrupt the normal program flow by activating the INT. REQ. line and they can gain direct access to main memory bv activating the DCII. REQ. line. (5)!kmory Control Mo-M~, MBSY. Processor controls thc main memory by means o f 3 open collcctor control lines (Mo, M1, M2). It synchronizes itself to the memory cycle time indicated by the MBSY signal. ( 6 ) Timing SYN, CP, XTL, CIKOUT. Processor can operate with an on-chip oscillator when a crystal is tied between (CP) and (XTL,) or i t can operatc from an external clock (CP). Processor generates a synchronization signal (SYN) for all external devices. The internal clock is available to the outside world on (CLKOUT).","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114579298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155682
H. Kotecha, F. De La Moneda, K. Beilstein
{"title":"Characterization of short and narrow channel effects for CAD-IGFET model","authors":"H. Kotecha, F. De La Moneda, K. Beilstein","doi":"10.1109/ISSCC.1977.1155682","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155682","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115431633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155701
R. McCharles, V. Saletore, W. Black, D. Hodges
ANALOG TO DIGITAL CONVERTERS perform digital logic, analog comparison and analog arithmetic. While digital logic and analog comparison are readily performed in LSI form, analog arithmetic has been largely excluded. For this reason, most single chip A/D converters use counting algorithms (such as dual slope) which are slow but which require only modest analog capability. .4 cyclic A/D converter’ can provide both a means of implcmenting successive approximation A/D converters and a means of performing general purpose analog arithmetic. This type of converter is ideal for realization using precision-ratioed capacitors A prototy e circuit using an analog CMOS process has been fabricated . The circuit features A/D conversion rates of 5 ps per bit, infinite resolution, 10 bits accuracy, and programmability, on a 3200 square mil die area. A simplified schematic of the A/D converter is shown in Figure 1. Two amplifiers, five ratio-matched capacitors ( 5 1 C ~ ) and two switches form a recirculating analog shift register wlth a gain of two. Three switches permit loading the register with an analog input and adding or subtracting the reference. A comparator to test the sign of output V, completes the circuit. A timing diagram showing the circuit in operation is shown in Figure 2. To start conversion the register is cleared by bringing both V1 and V2 high while the input is sampled by connecting C1 to Vin. This forces both V, and Yy to zero. During the second half of the initial cycle, C1 is connected t9 the analog ground and VI is brought low. This causes a charge of Cl*VIN to flow from C1 to C2. Since C1 and C2 are equal in value this will cause V, to be equal to the sampled value of VIN, and the comparator will indicate the sign of the sampled voltage. To determine the next bit V2 is brought low and VI is raised, while C1 is connected to ground (if the sign was positive) or to VREF (if the sign was negative). This causes the voltage Vx to be transferred to Vy, while 17, is forced to zero. At this point the charge in C1 is k CL*VREF, and the charge in Cg is C~*VIN. 2
模数转换器执行数字逻辑、模拟比较和模拟运算。虽然数字逻辑和模拟比较很容易在大规模集成电路形式中进行，但模拟运算在很大程度上被排除在外。出于这个原因，大多数单芯片A/D转换器使用计数算法(如双斜率)，这是缓慢的，但只需要适度的模拟能力。0.4循环A/D转换器可以提供一种实现连续逼近A/D转换器的方法和一种执行通用模拟算法的方法。这种类型的转换器是理想的实现使用精密比电容器。一个原型电路使用模拟CMOS工艺已经制作。该电路的特点是A/D转换速率为5ps / bit，无限分辨率，10位精度和可编程性，在3200平方毫米的芯片面积上。A/D转换器的简化原理图如图1所示。两个放大器，五个比率匹配电容器(51 C ~)和两个开关构成一个增益为2的循环模拟移位寄存器。三个开关允许加载寄存器与模拟输入和增加或减少参考。一个比较器来测试输出V的符号，完成电路。图2显示了电路运行的时序图。为了开始转换，通过将V1和V2都调高来清除寄存器，同时通过将C1连接到Vin来对输入进行采样。这使得V和Yy都趋近于零。在初始周期的后半段，C1连接到模拟地，将VI调低。这导致Cl*VIN电荷从C1流向C2。由于C1和C2的值相等，这将导致V等于VIN的采样值，比较器将指示采样电压的符号。为了确定下一个位，V2被调低，VI升高，而C1连接到地(如果符号为正)或VREF(如果符号为负)。这导致电压Vx被转移到Vy，而17，被强制为零。此时，C1中的电荷为k CL*VREF，而Cg中的电荷为C~*VIN。2
{"title":"An algorithmic analog-to-digital converter","authors":"R. McCharles, V. Saletore, W. Black, D. Hodges","doi":"10.1109/ISSCC.1977.1155701","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155701","url":null,"abstract":"ANALOG TO DIGITAL CONVERTERS perform digital logic, analog comparison and analog arithmetic. While digital logic and analog comparison are readily performed in LSI form, analog arithmetic has been largely excluded. For this reason, most single chip A/D converters use counting algorithms (such as dual slope) which are slow but which require only modest analog capability. .4 cyclic A/D converter’ can provide both a means of implcmenting successive approximation A/D converters and a means of performing general purpose analog arithmetic. This type of converter is ideal for realization using precision-ratioed capacitors A prototy e circuit using an analog CMOS process has been fabricated . The circuit features A/D conversion rates of 5 ps per bit, infinite resolution, 10 bits accuracy, and programmability, on a 3200 square mil die area. A simplified schematic of the A/D converter is shown in Figure 1. Two amplifiers, five ratio-matched capacitors ( 5 1 C ~ ) and two switches form a recirculating analog shift register wlth a gain of two. Three switches permit loading the register with an analog input and adding or subtracting the reference. A comparator to test the sign of output V, completes the circuit. A timing diagram showing the circuit in operation is shown in Figure 2. To start conversion the register is cleared by bringing both V1 and V2 high while the input is sampled by connecting C1 to Vin. This forces both V, and Yy to zero. During the second half of the initial cycle, C1 is connected t9 the analog ground and VI is brought low. This causes a charge of Cl*VIN to flow from C1 to C2. Since C1 and C2 are equal in value this will cause V, to be equal to the sampled value of VIN, and the comparator will indicate the sign of the sampled voltage. To determine the next bit V2 is brought low and VI is raised, while C1 is connected to ground (if the sign was positive) or to VREF (if the sign was negative). This causes the voltage Vx to be transferred to Vy, while 17, is forced to zero. At this point the charge in C1 is k CL*VREF, and the charge in Cg is C~*VIN. 2","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117060491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155642
H. Ishikawa, H. Kusakawa, K. Suyama, M. Fukuta
wave amplifiers, but for high speed switching circuits’. Some of the logic using normally-on type GaAs MESFETs have large power dissipation and complicated circuit construction. The normally-off type GaAs MESFET logic has not as yet been reported, even though it is expected to have some attractive features such as low power dissipation and simple circuit configuration. Figure 1 is a microphotograph of the buffered output 13-stage ring oscillator consisting of normally-off type GaAs MESFETs and epitaxial resistors. A cutaway view of the inverter used in the ring oscillator is shown in Figure 2. The devices were fabricated on a sulfur-doped N-type epitaxial layer grown by VPE onto a semi-insulating Cr-doped substrate. The do ing density and thickness of the epitaxial layer was 1 x 101’cm-3 and 0.1 pm, respectively. The N-type layer outside the active area was etched down to the semiinsulating substrate to isolate inverters from each other. A dual-metal system was used. 0.04-pm thick Au-Ge eutectic alloy and 0.4-pm thick Au were continuously deposited as the first metal layer and were alloyed at 450’C for 120 seconds to make ohmic contact. Next, O.5pm-thick Si02 film which was used for the isolation of the dual metal layers was deposited by Chemical Vapor Deposition (CVD). This film was etched selectively to open the gate windows and the contact holes to the first metal layer. The second metal layer made with Cr-Pt-Au was used for the Schottky gate and crossing over or connecting to the GaAs MESFETs are substantially useful not only for micro-
{"title":"Normally-off type GaAs MESFET for low power, high speed logic circuits","authors":"H. Ishikawa, H. Kusakawa, K. Suyama, M. Fukuta","doi":"10.1109/ISSCC.1977.1155642","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155642","url":null,"abstract":"wave amplifiers, but for high speed switching circuits’. Some of the logic using normally-on type GaAs MESFETs have large power dissipation and complicated circuit construction. The normally-off type GaAs MESFET logic has not as yet been reported, even though it is expected to have some attractive features such as low power dissipation and simple circuit configuration. Figure 1 is a microphotograph of the buffered output 13-stage ring oscillator consisting of normally-off type GaAs MESFETs and epitaxial resistors. A cutaway view of the inverter used in the ring oscillator is shown in Figure 2. The devices were fabricated on a sulfur-doped N-type epitaxial layer grown by VPE onto a semi-insulating Cr-doped substrate. The do ing density and thickness of the epitaxial layer was 1 x 101’cm-3 and 0.1 pm, respectively. The N-type layer outside the active area was etched down to the semiinsulating substrate to isolate inverters from each other. A dual-metal system was used. 0.04-pm thick Au-Ge eutectic alloy and 0.4-pm thick Au were continuously deposited as the first metal layer and were alloyed at 450’C for 120 seconds to make ohmic contact. Next, O.5pm-thick Si02 film which was used for the isolation of the dual metal layers was deposited by Chemical Vapor Deposition (CVD). This film was etched selectively to open the gate windows and the contact holes to the first metal layer. The second metal layer made with Cr-Pt-Au was used for the Schottky gate and crossing over or connecting to the GaAs MESFETs are substantially useful not only for micro-","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133564318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155678
K. Shimotori, K. Anami, Y. Nagayama, I. Okhura, M. Ohmori, T. Nakano, Y. Hayashi, Y. Tarui
DIFFUSION-SELF-ALIGNED (DM) M O S I C ~ ' , or D M O S ~ have received attention as subnanosecond and high density devices. In this paper, the experimental results of a DSA MOS memory fabricated by full ion implantation techniques to achieve better threshold voltage controllability will be dcscribed. Access time is 60 ns; power consumed is 950mW. Figure 1 shows cross section of the DSA E-D inverter. It is apparent from the figure, that the effective channel region of the DSA transistor is determined by the diffusion length difference between boron and arsenic layer. All dopants were deposited by ion implantatio-n method on P(71) Si substrate; resistivity was 100 "200 Q-cm, crystal orientation (loo), respectively. The threshold voltage of the device was controlled within 1.20 ? 0.15V and the effective channel length was 0.4 pm. The gain factor was 5 times larger than that of the conventional NMOS3. Features of the DSA MOS process are: 1 ) E-D gate achieved by N-channel 71 planar technique; 2 ) selective oxidation process (SOP) adapted to obtain high packing density and to reduce surface steps; 3) Si gate also used for a smaller feedback capacitance and higher packing density; and 4) all dopants deposited by ion implantation method to improve control of threshold voltage. To evaluate the basic electrical characteristics of these devices, 1 9 stag: ring oscillators have been fabricated by varing process parameters. Figure 2 shows the propagation delay time versus power dissipation, where the parameters were varied for the amount of channel dope to the depletion FET and power supply voltages. In the unhatched region, the driving capability of the DSA MOS FET is smaller than that of the load FET, thus the inverter does not operate. The minimum power delay product (0.05 pJ) and the minimum propagation delay time (0.32 ns) are shown in the ploy. Using this process, a 4096-bit fully decoded dynamic R/W random access memory was developed (Figure 3) using a 5 p m minimum as a base. The memory cell uses a 1 Tr/cell structure to avoid Vth to minimize inverse connection effects due to high __
扩散自对准(DM) M O SI C ~’或DM O S ~作为亚纳秒和高密度器件受到了广泛的关注。本文描述了采用全离子注入技术制备的DSA MOS存储器的实验结果，以获得更好的阈值电压可控性。访问时间为60ns;耗电量为950mW。图1为DSA E-D逆变器的横截面。从图中可以明显看出，DSA晶体管的有效通道区域是由硼层和砷层之间的扩散长度差决定的。采用离子注入法在P(71) Si衬底上沉积各掺杂剂;电阻率分别为100“200 Q-cm，晶体取向(loo)。设备阈值电压控制在1.20 ?0.15V，有效通道长度为0.4 pm。增益系数是传统NMOS3的5倍。DSA MOS工艺的特点是:1)采用n通道71平面技术实现E-D栅极;2)选择性氧化工艺(SOP)适于获得高填料密度和减少表面台阶;3)采用硅栅极，反馈电容更小，封装密度更高;4)所有的掺杂剂均采用离子注入法沉积，提高了对阈值电压的控制。为了评估这些器件的基本电气特性，通过不同的工艺参数制备了19个牡环振荡器。图2显示了传输延迟时间与功耗的关系，其中参数随通道掺杂量、耗尽场效应管和电源电压的变化而变化。在非孵化区，DSA MOS场效应管的驱动能力小于负载场效应管，导致逆变器不工作。该策略显示了最小的功率延迟积(0.05 pJ)和最小的传播延迟时间(0.32 ns)。使用这个过程，开发了一个4096位完全解码的动态R/W随机存取存储器(图3)，使用最小5 p m作为基础。存储单元使用1tr /cell结构来避免Vth，以最小化由于高__引起的反向连接效应
{"title":"Fully ion implanted 4096-bit high speed DSA MOS RAM","authors":"K. Shimotori, K. Anami, Y. Nagayama, I. Okhura, M. Ohmori, T. Nakano, Y. Hayashi, Y. Tarui","doi":"10.1109/ISSCC.1977.1155678","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155678","url":null,"abstract":"DIFFUSION-SELF-ALIGNED (DM) M O S I C ~ ' , or D M O S ~ have received attention as subnanosecond and high density devices. In this paper, the experimental results of a DSA MOS memory fabricated by full ion implantation techniques to achieve better threshold voltage controllability will be dcscribed. Access time is 60 ns; power consumed is 950mW. Figure 1 shows cross section of the DSA E-D inverter. It is apparent from the figure, that the effective channel region of the DSA transistor is determined by the diffusion length difference between boron and arsenic layer. All dopants were deposited by ion implantatio-n method on P(71) Si substrate; resistivity was 100 \"200 Q-cm, crystal orientation (loo), respectively. The threshold voltage of the device was controlled within 1.20 ? 0.15V and the effective channel length was 0.4 pm. The gain factor was 5 times larger than that of the conventional NMOS3. Features of the DSA MOS process are: 1 ) E-D gate achieved by N-channel 71 planar technique; 2 ) selective oxidation process (SOP) adapted to obtain high packing density and to reduce surface steps; 3) Si gate also used for a smaller feedback capacitance and higher packing density; and 4) all dopants deposited by ion implantation method to improve control of threshold voltage. To evaluate the basic electrical characteristics of these devices, 1 9 stag: ring oscillators have been fabricated by varing process parameters. Figure 2 shows the propagation delay time versus power dissipation, where the parameters were varied for the amount of channel dope to the depletion FET and power supply voltages. In the unhatched region, the driving capability of the DSA MOS FET is smaller than that of the load FET, thus the inverter does not operate. The minimum power delay product (0.05 pJ) and the minimum propagation delay time (0.32 ns) are shown in the ploy. Using this process, a 4096-bit fully decoded dynamic R/W random access memory was developed (Figure 3) using a 5 p m minimum as a base. The memory cell uses a 1 Tr/cell structure to avoid Vth to minimize inverse connection effects due to high __","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"34 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120992882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155669
C. Shinn
AN ALL MONOLITHIC, dc to > I GI*, amplifier/Schmidt trigger with 8 mV rms input sensitivity has been designed using a junction-isolated 5 GHz fT process in spite of the inherent high capacitances. Included on a 1.39 x 1.59 mm chip are electronic gain control, 180’ phase switching, ECL line driver output, all biasing circuits and a one-shot LED driver. A functional block diagram is shown in Figure 1. The amplifier is composed of a cascade of three identical modified Gilbert gain cells’. The current gain of this type of circuit is set by the ratio of device input impedances which in turn are a function of their quiescent currents. Because the currents are added at the output of each stage, a cascade requires a geometric increase in the power dissipation for each additional stage. N t h even the first stage current constrained to be fairly high to obtain wide bandwidth, a cascade would be unreasonable. Modifying the gain cell by the addition of emitter resistors allows the input impedance and thus the current gain, to become independent of dc bias. Furthermore, this modification generally results in a substantial reduction in the mean squared output noise current (in2) since the expression is changed from:
尽管具有固有的高电容，但采用结隔离的5 GHz fT工艺设计了一种具有8 mV rms输入灵敏度的全单片直流到> I GI*放大器/施密特触发器。包含在1.39 x 1.59 mm芯片上的是电子增益控制，180 '相位开关，ECL线路驱动器输出，所有偏置电路和一个单镜头LED驱动器。功能框图如图1所示。该放大器由三个相同的改良吉尔伯特增益单元级联组成。这种类型电路的电流增益是由器件输入阻抗的比值决定的，而器件输入阻抗又是其静态电流的函数。由于电流是在每一级的输出处增加的，因此级联需要每增加一级的功耗呈几何级数增加。然而，即使将第一级电流约束得相当高以获得较宽的带宽，级联也是不合理的。通过添加射极电阻来修改增益单元，可以使输入阻抗和电流增益与直流偏置无关。此外，这种修改通常会导致均方输出噪声电流(in2)的大幅降低，因为表达式变为:
{"title":"Wideband DC-coupled amp/schmidt","authors":"C. Shinn","doi":"10.1109/ISSCC.1977.1155669","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155669","url":null,"abstract":"AN ALL MONOLITHIC, dc to > I GI*, amplifier/Schmidt trigger with 8 mV rms input sensitivity has been designed using a junction-isolated 5 GHz fT process in spite of the inherent high capacitances. Included on a 1.39 x 1.59 mm chip are electronic gain control, 180’ phase switching, ECL line driver output, all biasing circuits and a one-shot LED driver. A functional block diagram is shown in Figure 1. The amplifier is composed of a cascade of three identical modified Gilbert gain cells’. The current gain of this type of circuit is set by the ratio of device input impedances which in turn are a function of their quiescent currents. Because the currents are added at the output of each stage, a cascade requires a geometric increase in the power dissipation for each additional stage. N t h even the first stage current constrained to be fairly high to obtain wide bandwidth, a cascade would be unreasonable. Modifying the gain cell by the addition of emitter resistors allows the input impedance and thus the current gain, to become independent of dc bias. Furthermore, this modification generally results in a substantial reduction in the mean squared output noise current (in2) since the expression is changed from:","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129876986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155734
J. Heightley
{"title":"Aids to the layout of custom LSI","authors":"J. Heightley","doi":"10.1109/ISSCC.1977.1155734","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155734","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131002260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155702
H. Mukai, K. Kawarada, K. Kondo, K. Toyoda
A 1024-BIT ECL RAM with typical address access time of 7.5 ns, faster than previously-reported RAMS’ will bc‘discussed. Write cycle time of 1 0 11s and write-enable pulsewidth of 3.5 ns are also possible. The memory consists of four blocks of each 256 words x 1 bit, which can be independently selected by four block select terminals, and therefore, may be used as either a 256 words x 4 bits or a 1024 words x 1 bit device. New circuit techniques, involving especially address decoders and sense amplifiers, as well as passive isolation technology and shallow diffusion processing were most helpful in achieving improved speed performance; Figure 1. The decoding circuit links a feedback loop from the collector circuit to the base of the multi-emitter transistor in each AND gate to equalize dc current distribution to these AND gates via a single current switch; minized too is the effective input logic swing of these gates. Thus, current mode operation, through driving of plural AND gates by condensed switching current, results in a very short delay time of 2.5 ns from address input t o word driver output, according to computer simulation. The common-basemode transistor switches connected between bit lines and sense circuits and cross-coupling between truth and complement in each sensing circuit reduce the undesirable effects of stray capacitances, resulting in a high sensing speed. The bit line clamping circuit is effective in quick recovery of bit line potential. Combination of the passive isolation of IOP (Isolated by Oxide and Polysilicon) with V-groove and the shallow, selfaligning emitter diffusion technique of DOPOS2 (Doped Poly Silicon) has made it possible to fabricate high-speed switching transistors with low parasitic capacitances ( CEB = 0.03 pF, CCB = 0.10 pF and C c s = 0.20 pF), high hFE (about 100) and high fT (2.0 GHz). Moreover, the memory cell size is now 2756 pm2; 52 p m x 53 pm. Minimum emitter size of IOPDOPOS transistors in this device is 3 p m x 8 pm. The memory
{"title":"Ultra high speed 1K-bit RAM with 7.5 ns access time","authors":"H. Mukai, K. Kawarada, K. Kondo, K. Toyoda","doi":"10.1109/ISSCC.1977.1155702","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155702","url":null,"abstract":"A 1024-BIT ECL RAM with typical address access time of 7.5 ns, faster than previously-reported RAMS’ will bc‘discussed. Write cycle time of 1 0 11s and write-enable pulsewidth of 3.5 ns are also possible. The memory consists of four blocks of each 256 words x 1 bit, which can be independently selected by four block select terminals, and therefore, may be used as either a 256 words x 4 bits or a 1024 words x 1 bit device. New circuit techniques, involving especially address decoders and sense amplifiers, as well as passive isolation technology and shallow diffusion processing were most helpful in achieving improved speed performance; Figure 1. The decoding circuit links a feedback loop from the collector circuit to the base of the multi-emitter transistor in each AND gate to equalize dc current distribution to these AND gates via a single current switch; minized too is the effective input logic swing of these gates. Thus, current mode operation, through driving of plural AND gates by condensed switching current, results in a very short delay time of 2.5 ns from address input t o word driver output, according to computer simulation. The common-basemode transistor switches connected between bit lines and sense circuits and cross-coupling between truth and complement in each sensing circuit reduce the undesirable effects of stray capacitances, resulting in a high sensing speed. The bit line clamping circuit is effective in quick recovery of bit line potential. Combination of the passive isolation of IOP (Isolated by Oxide and Polysilicon) with V-groove and the shallow, selfaligning emitter diffusion technique of DOPOS2 (Doped Poly Silicon) has made it possible to fabricate high-speed switching transistors with low parasitic capacitances ( CEB = 0.03 pF, CCB = 0.10 pF and C c s = 0.20 pF), high hFE (about 100) and high fT (2.0 GHz). Moreover, the memory cell size is now 2756 pm2; 52 p m x 53 pm. Minimum emitter size of IOPDOPOS transistors in this device is 3 p m x 8 pm. The memory","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130349483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155633
M. Phan, J. Shier, A. Evans
IT HAS LONG BEEN recognized that the need for compact load devices is one of the main problems in building dense bipolar integrated circuits. In recent years several quite promising new approaches to this problem have been developed, including: (1) very high value P-type resistors made by ion implantation (2) the use of lateral PNP transistors to supply and limit the operating current ( 12L) and (3) various kinds of vacuumdeposited resistive materials. The JFET loads to be presented provide yet another way of achieving very compact load elements in bipolar integrated circuits. The JFET loads use the lightlydoped N-type channels which appear under the isolation oxide in an oxide-isolated structure employing an N-type epitaxial layer. These channels arise from the preferential segregation of the dopant during the growth of the isolation oxide’ and have been found to be stable and reproducible. The delineation of the load device is accomplished by a masked P type doping step made prior to epitaxial growth, with the P regions serving as channel stoppers between isolated devices. A load device is produced by simply omitting the channel stopper between two N regions to be connected to the load and thus is physically located in the isolation regions an aspect which substantially improves the circuit density by using space wasted in most bipolar structures; Figures 1 and 4. The load device is best described as a substrate-gate JFET (Figure 2) with many advantages: (1) it is very compact, equivalent resistances of 1 Mi?, being realized in 1 t o 2 mil2 area (including the channel stoppers), (2) i t behaves like a constant-current source, rather like the depletion loads u ed in MOS devices but without the need for gate metalization over it, (3) it connects readily to any part of a transistor collector region without the need for contacts or metalization, (4) its position under thick oxide minimizes parasitic capacitance and sensitivity to potentials of the overlying metalization, ( 5 ) the light doping level in substrate and load gives a low capacitance to substrate, and (6) the sheet resistance and nonlinear properties of these loads can be varied over a very broad range by adjusting process parameters. The process, which provides very shallow double-diffused NPN transistors with washed emitters, PtSi Schottky diodes, and high-beta vertical PNP transistors, lends itself particularly well to the use of a diode-coupled cell for the main storage flipflops in an all-TTL RAM design. As a result a 1024-bit TTL RAM was chosen for the initial design using the JFET load 1 Grove, A S . , Leistiko, 0. and Sah, C.T., “Redistribution of Acceptor and Donor Impurities During Thermal Oxidation of Silicon”, J. Applied Physics, Vol. 35, p. 2695; 1964. Lynes, D.J. and Hodges. D.A., “A Diode-Coupled Bipolar Transistor Memory Cell”, ISSCC Digest of Technical Papers, p. 44-45; Feb., 1970. 2 devices. These loads allowed the use of a compact, low-powerdissipation diode-coupled c
{"title":"A fast 1024-bit bipolar RAM using JFET load devices","authors":"M. Phan, J. Shier, A. Evans","doi":"10.1109/ISSCC.1977.1155633","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155633","url":null,"abstract":"IT HAS LONG BEEN recognized that the need for compact load devices is one of the main problems in building dense bipolar integrated circuits. In recent years several quite promising new approaches to this problem have been developed, including: (1) very high value P-type resistors made by ion implantation (2) the use of lateral PNP transistors to supply and limit the operating current ( 12L) and (3) various kinds of vacuumdeposited resistive materials. The JFET loads to be presented provide yet another way of achieving very compact load elements in bipolar integrated circuits. The JFET loads use the lightlydoped N-type channels which appear under the isolation oxide in an oxide-isolated structure employing an N-type epitaxial layer. These channels arise from the preferential segregation of the dopant during the growth of the isolation oxide’ and have been found to be stable and reproducible. The delineation of the load device is accomplished by a masked P type doping step made prior to epitaxial growth, with the P regions serving as channel stoppers between isolated devices. A load device is produced by simply omitting the channel stopper between two N regions to be connected to the load and thus is physically located in the isolation regions an aspect which substantially improves the circuit density by using space wasted in most bipolar structures; Figures 1 and 4. The load device is best described as a substrate-gate JFET (Figure 2) with many advantages: (1) it is very compact, equivalent resistances of 1 Mi?, being realized in 1 t o 2 mil2 area (including the channel stoppers), (2) i t behaves like a constant-current source, rather like the depletion loads u ed in MOS devices but without the need for gate metalization over it, (3) it connects readily to any part of a transistor collector region without the need for contacts or metalization, (4) its position under thick oxide minimizes parasitic capacitance and sensitivity to potentials of the overlying metalization, ( 5 ) the light doping level in substrate and load gives a low capacitance to substrate, and (6) the sheet resistance and nonlinear properties of these loads can be varied over a very broad range by adjusting process parameters. The process, which provides very shallow double-diffused NPN transistors with washed emitters, PtSi Schottky diodes, and high-beta vertical PNP transistors, lends itself particularly well to the use of a diode-coupled cell for the main storage flipflops in an all-TTL RAM design. As a result a 1024-bit TTL RAM was chosen for the initial design using the JFET load 1 Grove, A S . , Leistiko, 0. and Sah, C.T., “Redistribution of Acceptor and Donor Impurities During Thermal Oxidation of Silicon”, J. Applied Physics, Vol. 35, p. 2695; 1964. Lynes, D.J. and Hodges. D.A., “A Diode-Coupled Bipolar Transistor Memory Cell”, ISSCC Digest of Technical Papers, p. 44-45; Feb., 1970. 2 devices. These loads allowed the use of a compact, low-powerdissipation diode-coupled c","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128300408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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