Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155737
S. Gray
WHEN ACTIVE RADARS arc used as seekers in guided missiles, they typically require peak transmitter output power in kilowatts to achieve ranges of several kilometers. When solidstate implementation is also required, one approach is to transmit long, medium power pulses and to use pulse compression in the radar receiver to achieve high effective peak power. A recent application of this nature resulted in al7-GHz IMPATT power amplifier which will be described in this paper. The design called for an unconditionally-stable, pulsed amplifier providing 20-dB gain at an output level of 1 0 W. Pulsewidths of 1 0 ps, a 10% duty cycle, and a 500-MHz bandwidth were also required.
{"title":"A long pulse IMPATT amplifier for KU-band","authors":"S. Gray","doi":"10.1109/ISSCC.1977.1155737","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155737","url":null,"abstract":"WHEN ACTIVE RADARS arc used as seekers in guided missiles, they typically require peak transmitter output power in kilowatts to achieve ranges of several kilometers. When solidstate implementation is also required, one approach is to transmit long, medium power pulses and to use pulse compression in the radar receiver to achieve high effective peak power. A recent application of this nature resulted in al7-GHz IMPATT power amplifier which will be described in this paper. The design called for an unconditionally-stable, pulsed amplifier providing 20-dB gain at an output level of 1 0 W. Pulsewidths of 1 0 ps, a 10% duty cycle, and a 500-MHz bandwidth were also required.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"XX 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128837131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155701
R. McCharles, V. Saletore, W. Black, D. Hodges
ANALOG TO DIGITAL CONVERTERS perform digital logic, analog comparison and analog arithmetic. While digital logic and analog comparison are readily performed in LSI form, analog arithmetic has been largely excluded. For this reason, most single chip A/D converters use counting algorithms (such as dual slope) which are slow but which require only modest analog capability. .4 cyclic A/D converter’ can provide both a means of implcmenting successive approximation A/D converters and a means of performing general purpose analog arithmetic. This type of converter is ideal for realization using precision-ratioed capacitors A prototy e circuit using an analog CMOS process has been fabricated . The circuit features A/D conversion rates of 5 ps per bit, infinite resolution, 10 bits accuracy, and programmability, on a 3200 square mil die area. A simplified schematic of the A/D converter is shown in Figure 1. Two amplifiers, five ratio-matched capacitors ( 5 1 C ~ ) and two switches form a recirculating analog shift register wlth a gain of two. Three switches permit loading the register with an analog input and adding or subtracting the reference. A comparator to test the sign of output V, completes the circuit. A timing diagram showing the circuit in operation is shown in Figure 2. To start conversion the register is cleared by bringing both V1 and V2 high while the input is sampled by connecting C1 to Vin. This forces both V, and Yy to zero. During the second half of the initial cycle, C1 is connected t9 the analog ground and VI is brought low. This causes a charge of Cl*VIN to flow from C1 to C2. Since C1 and C2 are equal in value this will cause V, to be equal to the sampled value of VIN, and the comparator will indicate the sign of the sampled voltage. To determine the next bit V2 is brought low and VI is raised, while C1 is connected to ground (if the sign was positive) or to VREF (if the sign was negative). This causes the voltage Vx to be transferred to Vy, while 17, is forced to zero. At this point the charge in C1 is k CL*VREF, and the charge in Cg is C~*VIN. 2
模数转换器执行数字逻辑、模拟比较和模拟运算。虽然数字逻辑和模拟比较很容易在大规模集成电路形式中进行，但模拟运算在很大程度上被排除在外。出于这个原因，大多数单芯片A/D转换器使用计数算法(如双斜率)，这是缓慢的，但只需要适度的模拟能力。0.4循环A/D转换器可以提供一种实现连续逼近A/D转换器的方法和一种执行通用模拟算法的方法。这种类型的转换器是理想的实现使用精密比电容器。一个原型电路使用模拟CMOS工艺已经制作。该电路的特点是A/D转换速率为5ps / bit，无限分辨率，10位精度和可编程性，在3200平方毫米的芯片面积上。A/D转换器的简化原理图如图1所示。两个放大器，五个比率匹配电容器(51 C ~)和两个开关构成一个增益为2的循环模拟移位寄存器。三个开关允许加载寄存器与模拟输入和增加或减少参考。一个比较器来测试输出V的符号，完成电路。图2显示了电路运行的时序图。为了开始转换，通过将V1和V2都调高来清除寄存器，同时通过将C1连接到Vin来对输入进行采样。这使得V和Yy都趋近于零。在初始周期的后半段，C1连接到模拟地，将VI调低。这导致Cl*VIN电荷从C1流向C2。由于C1和C2的值相等，这将导致V等于VIN的采样值，比较器将指示采样电压的符号。为了确定下一个位，V2被调低，VI升高，而C1连接到地(如果符号为正)或VREF(如果符号为负)。这导致电压Vx被转移到Vy，而17，被强制为零。此时，C1中的电荷为k CL*VREF，而Cg中的电荷为C~*VIN。2
{"title":"An algorithmic analog-to-digital converter","authors":"R. McCharles, V. Saletore, W. Black, D. Hodges","doi":"10.1109/ISSCC.1977.1155701","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155701","url":null,"abstract":"ANALOG TO DIGITAL CONVERTERS perform digital logic, analog comparison and analog arithmetic. While digital logic and analog comparison are readily performed in LSI form, analog arithmetic has been largely excluded. For this reason, most single chip A/D converters use counting algorithms (such as dual slope) which are slow but which require only modest analog capability. .4 cyclic A/D converter’ can provide both a means of implcmenting successive approximation A/D converters and a means of performing general purpose analog arithmetic. This type of converter is ideal for realization using precision-ratioed capacitors A prototy e circuit using an analog CMOS process has been fabricated . The circuit features A/D conversion rates of 5 ps per bit, infinite resolution, 10 bits accuracy, and programmability, on a 3200 square mil die area. A simplified schematic of the A/D converter is shown in Figure 1. Two amplifiers, five ratio-matched capacitors ( 5 1 C ~ ) and two switches form a recirculating analog shift register wlth a gain of two. Three switches permit loading the register with an analog input and adding or subtracting the reference. A comparator to test the sign of output V, completes the circuit. A timing diagram showing the circuit in operation is shown in Figure 2. To start conversion the register is cleared by bringing both V1 and V2 high while the input is sampled by connecting C1 to Vin. This forces both V, and Yy to zero. During the second half of the initial cycle, C1 is connected t9 the analog ground and VI is brought low. This causes a charge of Cl*VIN to flow from C1 to C2. Since C1 and C2 are equal in value this will cause V, to be equal to the sampled value of VIN, and the comparator will indicate the sign of the sampled voltage. To determine the next bit V2 is brought low and VI is raised, while C1 is connected to ground (if the sign was positive) or to VREF (if the sign was negative). This causes the voltage Vx to be transferred to Vy, while 17, is forced to zero. At this point the charge in C1 is k CL*VREF, and the charge in Cg is C~*VIN. 2","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117060491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155732
W. Lattin
{"title":"Low end microprocessors: Will there be an industry standard?","authors":"W. Lattin","doi":"10.1109/ISSCC.1977.1155732","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155732","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121559629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155738
D. Buss, L. Terman
{"title":"Low cost electronic serial memories","authors":"D. Buss, L. Terman","doi":"10.1109/ISSCC.1977.1155738","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155738","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124409012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155642
H. Ishikawa, H. Kusakawa, K. Suyama, M. Fukuta
wave amplifiers, but for high speed switching circuits’. Some of the logic using normally-on type GaAs MESFETs have large power dissipation and complicated circuit construction. The normally-off type GaAs MESFET logic has not as yet been reported, even though it is expected to have some attractive features such as low power dissipation and simple circuit configuration. Figure 1 is a microphotograph of the buffered output 13-stage ring oscillator consisting of normally-off type GaAs MESFETs and epitaxial resistors. A cutaway view of the inverter used in the ring oscillator is shown in Figure 2. The devices were fabricated on a sulfur-doped N-type epitaxial layer grown by VPE onto a semi-insulating Cr-doped substrate. The do ing density and thickness of the epitaxial layer was 1 x 101’cm-3 and 0.1 pm, respectively. The N-type layer outside the active area was etched down to the semiinsulating substrate to isolate inverters from each other. A dual-metal system was used. 0.04-pm thick Au-Ge eutectic alloy and 0.4-pm thick Au were continuously deposited as the first metal layer and were alloyed at 450’C for 120 seconds to make ohmic contact. Next, O.5pm-thick Si02 film which was used for the isolation of the dual metal layers was deposited by Chemical Vapor Deposition (CVD). This film was etched selectively to open the gate windows and the contact holes to the first metal layer. The second metal layer made with Cr-Pt-Au was used for the Schottky gate and crossing over or connecting to the GaAs MESFETs are substantially useful not only for micro-
{"title":"Normally-off type GaAs MESFET for low power, high speed logic circuits","authors":"H. Ishikawa, H. Kusakawa, K. Suyama, M. Fukuta","doi":"10.1109/ISSCC.1977.1155642","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155642","url":null,"abstract":"wave amplifiers, but for high speed switching circuits’. Some of the logic using normally-on type GaAs MESFETs have large power dissipation and complicated circuit construction. The normally-off type GaAs MESFET logic has not as yet been reported, even though it is expected to have some attractive features such as low power dissipation and simple circuit configuration. Figure 1 is a microphotograph of the buffered output 13-stage ring oscillator consisting of normally-off type GaAs MESFETs and epitaxial resistors. A cutaway view of the inverter used in the ring oscillator is shown in Figure 2. The devices were fabricated on a sulfur-doped N-type epitaxial layer grown by VPE onto a semi-insulating Cr-doped substrate. The do ing density and thickness of the epitaxial layer was 1 x 101’cm-3 and 0.1 pm, respectively. The N-type layer outside the active area was etched down to the semiinsulating substrate to isolate inverters from each other. A dual-metal system was used. 0.04-pm thick Au-Ge eutectic alloy and 0.4-pm thick Au were continuously deposited as the first metal layer and were alloyed at 450’C for 120 seconds to make ohmic contact. Next, O.5pm-thick Si02 film which was used for the isolation of the dual metal layers was deposited by Chemical Vapor Deposition (CVD). This film was etched selectively to open the gate windows and the contact holes to the first metal layer. The second metal layer made with Cr-Pt-Au was used for the Schottky gate and crossing over or connecting to the GaAs MESFETs are substantially useful not only for micro-","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133564318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155647
H. Yamada, M. Katakura
LEVEL COMPRESSION-EXPANSION systems (compandors), are widely used for reducing noise in signal transmission’ 3 2 . However, the IC realization of the log linear transformation system has been considered difficult due to the requirement for high performance PNP transistors in these circuits. A system which incorporates an equivalent PNP transistor with high performance characteristics will be described.
{"title":"A monolithic IC for decibel-linear noise reduction","authors":"H. Yamada, M. Katakura","doi":"10.1109/ISSCC.1977.1155647","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155647","url":null,"abstract":"LEVEL COMPRESSION-EXPANSION systems (compandors), are widely used for reducing noise in signal transmission’ 3 2 . However, the IC realization of the log linear transformation system has been considered difficult due to the requirement for high performance PNP transistors in these circuits. A system which incorporates an equivalent PNP transistor with high performance characteristics will be described.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121661394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155678
K. Shimotori, K. Anami, Y. Nagayama, I. Okhura, M. Ohmori, T. Nakano, Y. Hayashi, Y. Tarui
DIFFUSION-SELF-ALIGNED (DM) M O S I C ~ ' , or D M O S ~ have received attention as subnanosecond and high density devices. In this paper, the experimental results of a DSA MOS memory fabricated by full ion implantation techniques to achieve better threshold voltage controllability will be dcscribed. Access time is 60 ns; power consumed is 950mW. Figure 1 shows cross section of the DSA E-D inverter. It is apparent from the figure, that the effective channel region of the DSA transistor is determined by the diffusion length difference between boron and arsenic layer. All dopants were deposited by ion implantatio-n method on P(71) Si substrate; resistivity was 100 "200 Q-cm, crystal orientation (loo), respectively. The threshold voltage of the device was controlled within 1.20 ? 0.15V and the effective channel length was 0.4 pm. The gain factor was 5 times larger than that of the conventional NMOS3. Features of the DSA MOS process are: 1 ) E-D gate achieved by N-channel 71 planar technique; 2 ) selective oxidation process (SOP) adapted to obtain high packing density and to reduce surface steps; 3) Si gate also used for a smaller feedback capacitance and higher packing density; and 4) all dopants deposited by ion implantation method to improve control of threshold voltage. To evaluate the basic electrical characteristics of these devices, 1 9 stag: ring oscillators have been fabricated by varing process parameters. Figure 2 shows the propagation delay time versus power dissipation, where the parameters were varied for the amount of channel dope to the depletion FET and power supply voltages. In the unhatched region, the driving capability of the DSA MOS FET is smaller than that of the load FET, thus the inverter does not operate. The minimum power delay product (0.05 pJ) and the minimum propagation delay time (0.32 ns) are shown in the ploy. Using this process, a 4096-bit fully decoded dynamic R/W random access memory was developed (Figure 3) using a 5 p m minimum as a base. The memory cell uses a 1 Tr/cell structure to avoid Vth to minimize inverse connection effects due to high __
扩散自对准(DM) M O SI C ~’或DM O S ~作为亚纳秒和高密度器件受到了广泛的关注。本文描述了采用全离子注入技术制备的DSA MOS存储器的实验结果，以获得更好的阈值电压可控性。访问时间为60ns;耗电量为950mW。图1为DSA E-D逆变器的横截面。从图中可以明显看出，DSA晶体管的有效通道区域是由硼层和砷层之间的扩散长度差决定的。采用离子注入法在P(71) Si衬底上沉积各掺杂剂;电阻率分别为100“200 Q-cm，晶体取向(loo)。设备阈值电压控制在1.20 ?0.15V，有效通道长度为0.4 pm。增益系数是传统NMOS3的5倍。DSA MOS工艺的特点是:1)采用n通道71平面技术实现E-D栅极;2)选择性氧化工艺(SOP)适于获得高填料密度和减少表面台阶;3)采用硅栅极，反馈电容更小，封装密度更高;4)所有的掺杂剂均采用离子注入法沉积，提高了对阈值电压的控制。为了评估这些器件的基本电气特性，通过不同的工艺参数制备了19个牡环振荡器。图2显示了传输延迟时间与功耗的关系，其中参数随通道掺杂量、耗尽场效应管和电源电压的变化而变化。在非孵化区，DSA MOS场效应管的驱动能力小于负载场效应管，导致逆变器不工作。该策略显示了最小的功率延迟积(0.05 pJ)和最小的传播延迟时间(0.32 ns)。使用这个过程，开发了一个4096位完全解码的动态R/W随机存取存储器(图3)，使用最小5 p m作为基础。存储单元使用1tr /cell结构来避免Vth，以最小化由于高__引起的反向连接效应
{"title":"Fully ion implanted 4096-bit high speed DSA MOS RAM","authors":"K. Shimotori, K. Anami, Y. Nagayama, I. Okhura, M. Ohmori, T. Nakano, Y. Hayashi, Y. Tarui","doi":"10.1109/ISSCC.1977.1155678","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155678","url":null,"abstract":"DIFFUSION-SELF-ALIGNED (DM) M O S I C ~ ' , or D M O S ~ have received attention as subnanosecond and high density devices. In this paper, the experimental results of a DSA MOS memory fabricated by full ion implantation techniques to achieve better threshold voltage controllability will be dcscribed. Access time is 60 ns; power consumed is 950mW. Figure 1 shows cross section of the DSA E-D inverter. It is apparent from the figure, that the effective channel region of the DSA transistor is determined by the diffusion length difference between boron and arsenic layer. All dopants were deposited by ion implantatio-n method on P(71) Si substrate; resistivity was 100 \"200 Q-cm, crystal orientation (loo), respectively. The threshold voltage of the device was controlled within 1.20 ? 0.15V and the effective channel length was 0.4 pm. The gain factor was 5 times larger than that of the conventional NMOS3. Features of the DSA MOS process are: 1 ) E-D gate achieved by N-channel 71 planar technique; 2 ) selective oxidation process (SOP) adapted to obtain high packing density and to reduce surface steps; 3) Si gate also used for a smaller feedback capacitance and higher packing density; and 4) all dopants deposited by ion implantation method to improve control of threshold voltage. To evaluate the basic electrical characteristics of these devices, 1 9 stag: ring oscillators have been fabricated by varing process parameters. Figure 2 shows the propagation delay time versus power dissipation, where the parameters were varied for the amount of channel dope to the depletion FET and power supply voltages. In the unhatched region, the driving capability of the DSA MOS FET is smaller than that of the load FET, thus the inverter does not operate. The minimum power delay product (0.05 pJ) and the minimum propagation delay time (0.32 ns) are shown in the ploy. Using this process, a 4096-bit fully decoded dynamic R/W random access memory was developed (Figure 3) using a 5 p m minimum as a base. The memory cell uses a 1 Tr/cell structure to avoid Vth to minimize inverse connection effects due to high __","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"34 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120992882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155729
L. Terman, W. Kosonocky
{"title":"Semiconductor RAMs: Limits to growth","authors":"L. Terman, W. Kosonocky","doi":"10.1109/ISSCC.1977.1155729","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155729","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115510271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155718
C. Séquin, M. Tompsett, D. Sealer, P. Suciu, P. Ryan
A SELF-CONTAINED charge-coupled 55-tap split-electrode filter will be described in this paper. The major problem that had to be solved was that of transforming the signal from the sense electrodes into a usable output signal with a large dynamic range and a minimal harmonic distortion. The factors that must be considered in formulating a solution to this problem are: (1) eliminating the effects of depletion capacitance, (2) detecting a difference signal in the presence of a large common mode signal and (3) preventing reset noise in the detection circuitry. A practical method to avoid the effects of depletion capacitance under the split sense electrodes is to keep these electrodes at a fixed potential during the sensing process by using a feedback loop around an operational amplifier as indicated in Figure 1. This sensing circuitry is optimally used in conjunction with a voltage input to the charge transfer channel, where the charge packets are metered under an MOS electrode, (MW), the geometry of which is the same as that of the sense electrodes, and which is also kept at the same potential VSE; Figure 1. The overall transfer characteristic from the voltage applied to the input diode, (and thus the interface potential in the metering well MW) to the amount of image charge produced on the sense electrodes (and hence the output voltage V O ~ T ) can then be expected to be linear. Various possible ways to clamp the sense electrodes to a given potential and to extract the desired output signal have been discussed earlier’’2. A novel approach to extract this difference signal in the presence of the considerably larger common mode signal is shown in Figure 2. One amplifier (AD) performs the differencing operation, while the other amplifier ( Ac) is used to suppress the common mode signal on the two sense busses. AC operates by comparing the arithmetic mean of the sense electrode potentials to the sense voltage reference VSE and feeds back the same error signal to both sense busses through capacitors CCt and Cc. The feedback signal around AD through CDwll maintain the balance between the two sense busses, and the combined
本文将介绍一种独立的电荷耦合55分接分电极滤波器。必须解决的主要问题是如何将来自传感电极的信号转换成具有大动态范围和最小谐波失真的可用输出信号。在制定这个问题的解决方案时必须考虑的因素是:(1)消除耗尽电容的影响;(2)在存在大共模信号时检测差分信号;(3)防止检测电路中的复位噪声。避免分裂感测电极下耗尽电容影响的一种实用方法是在感测过程中，通过在运算放大器周围使用反馈回路，使这些电极保持在固定电位，如图1所示。该传感电路最佳地与电荷转移通道的电压输入结合使用，其中电荷包在MOS电极下测量，(MW)，其几何形状与传感电极相同，并且也保持在相同的电位VSE;图1所示。从施加到输入二极管的电压(因此计量井中的界面电位为MW)到在感测电极上产生的图像电荷量(因此输出电压为V O ~ T)的总体转移特性可以预期为线性。各种可能的方法钳位感测电极到一个给定的电位，并提取所需的输出信号已在前面讨论过。图2显示了一种在较大的共模信号存在的情况下提取这种差分信号的新方法。一个放大器(AD)执行差分操作，而另一个放大器(Ac)用于抑制两个检测总线上的共模信号。AC的工作原理是将检测电极电位的算术平均值与检测电压参考VSE进行比较，并通过电容CCt和Cc将相同的误差信号反馈给两个检测母线，AD周围的反馈信号通过cdd保持两个检测母线之间的平衡，并结合起来
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Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155668
J. Schoeff
COMPANDED PULSE CODE MODULATED (PCM) transmission of voice signals has become standardized through widespread use of the Bell system p-law and the CCITT** A-law transfer characteristics. Until now, all codecs (eoder/decoders) for these communication systems have been fabricated in either discrete or hybrid form and have been relatively expensive. This paper will present a newly developed monolithic digital-to-analog converter specifically designed for compression and expansion of signals according to the existing PCM standard. This converter, however, is not limited to PCM communication, but may be used in other areas such as data acquisition, servo controls, data recording, telemetry, voice synthesis, log attenuation, secure communications, sonar, and many other applications which require a 12-bit plus sign dynamic range and the convenience of an 8-bit digital code. When used in a telecommunications application, the companding DAC is a complete PCM decoder, with metal options for p-law and A-law. A one-half step decision level for encoding is provided within the circuit and controlled with the encode/decode logic input. This current offsets the entire transfer characteristic one half step, regardless of the value of the output current. The outputs are multiplexed for time sharing of one DAC for both encode and decode operation. The DAC settling time is 500 ns, and i t will decode more than 32 PCM channels in 125 ps, which is the sampling period at 8 kHz. In a shared encoder it will convert eight channels, assuming a 1 0 ps sample and hold acquisition time. The outputs are high impedance, high compliance current sources and will interface with most balanced loads. The reference inputs will accept a fixed reference or a positive or negative multiplying input. The transfer characteristic of the companding DAC is shown in Figure 1. The output consists of eight positive chords and eight negative chords, each containing sixteen steps. The slopes of these chords are binarily related with the chord at the origin having steps equivalent in size to those in a 12-bit converter. The step size is a nearly constant 3.2% of reading throughout most of the dynamic range, which corresponds to approximately 0.3 dB per step. Each successive chord endpoint is 6 dB below the next higher endpoint for every chord in the A-law specification, and follows this for most chords in the p-law. The dynamic range, or ratio, of the full scale to the smallest step size is 72 dB for the p-law version and 66 dB for the A-law unit. The electrical specifications for the circuit are summarized in Table I.
通过广泛使用贝尔系统p-定律和CCITT** a -定律传输特性，压缩脉冲码调制(PCM)语音信号的传输已经标准化。到目前为止，用于这些通信系统的所有编解码器(编码器/解码器)都是以分立或混合形式制造的，并且相对昂贵。本文将介绍一种新开发的单片数模转换器，根据现有的PCM标准专门设计用于信号的压缩和扩展。然而，该转换器不仅限于PCM通信，还可用于其他领域，如数据采集，伺服控制，数据记录，遥测，语音合成，日志衰减，安全通信，声纳以及许多其他需要12位加号动态范围和8位数字代码的便利的应用。当用于电信应用时，扩展DAC是一个完整的PCM解码器，具有p律和a律金属选项。电路内提供用于编码的半步决策电平，并由编码/解码逻辑输入控制。无论输出电流的值是多少，该电流都会将整个传输特性偏移半步。输出多路复用，用于一个DAC的时间共享，用于编码和解码操作。DAC的建立时间为500ns，它将以125ps的速度解码超过32个PCM通道，这是8 kHz的采样周期。在共享编码器中，它将转换8个通道，假设10ps采样并保持采集时间。输出是高阻抗，高顺应电流源，并将与大多数平衡负载接口。参考输入将接受固定参考或正或负相乘输入。扩展DAC的传输特性如图1所示。输出由8个正和弦和8个负和弦组成，每个和弦包含16步。这些和弦的斜率与原点的和弦有二元关系，其步长与12位转换器中的步长相当。在大部分动态范围内，步长几乎是读数的3.2%，相当于每步约0.3 dB。在a律中，每个连续的和弦端点比下一个更高的端点低6db，在p律中，大多数和弦都遵循这一原则。满量程到最小步长的动态范围或比率，对于p律单元为72 dB，对于a律单元为66 dB。电路的电气规格概述在表1中。
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