Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155643
M. Klein
four-bit sequential approximation analog-to-digital unit integrated on a 6.25 mm square chip. It operates in liquid helium at 4.2K. Timing signals are supplied by external equip ment situated at room temperature for the experiment. Figure 1 shows a schematic diagram of the experimental chip. The analog input, which is unipolar and amplitude limited to 8 mA, is applied to a superconducting loop. Across this loop is a Josephson junction switch and the circuit performs the sample-and-hold function. The gate is held in the voltage state by a dc bias for acquisition of signal current from the external input, which is connected across the gate. A sample command pulse to a control line on the gate cancels the bias to return the gate to the superconducting state, trapping the acquired signal as a circulating super current in the loop and holding it for the duration of the A/D conversion cycle. Design considerations for the sample and hold circuit included: use of a large enough inductance so that a large number of flux quanta were stored per least significant bit (LSB); shaping of the junction to give a threshold characteristic capable of resolving an LSB; large enough junction to accept the maximum change between conversion cycles; critical damping of the circuit; junction recovery to the superconducting state at the end of the acquisition period in the presence of the largest rate of change of input signal.
{"title":"Analog digital converter using Josephson junctions","authors":"M. Klein","doi":"10.1109/ISSCC.1977.1155643","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155643","url":null,"abstract":"four-bit sequential approximation analog-to-digital unit integrated on a 6.25 mm square chip. It operates in liquid helium at 4.2K. Timing signals are supplied by external equip ment situated at room temperature for the experiment. Figure 1 shows a schematic diagram of the experimental chip. The analog input, which is unipolar and amplitude limited to 8 mA, is applied to a superconducting loop. Across this loop is a Josephson junction switch and the circuit performs the sample-and-hold function. The gate is held in the voltage state by a dc bias for acquisition of signal current from the external input, which is connected across the gate. A sample command pulse to a control line on the gate cancels the bias to return the gate to the superconducting state, trapping the acquired signal as a circulating super current in the loop and holding it for the duration of the A/D conversion cycle. Design considerations for the sample and hold circuit included: use of a large enough inductance so that a large number of flux quanta were stored per least significant bit (LSB); shaping of the junction to give a threshold characteristic capable of resolving an LSB; large enough junction to accept the maximum change between conversion cycles; critical damping of the circuit; junction recovery to the superconducting state at the end of the acquisition period in the presence of the largest rate of change of input signal.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126763111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155654
R. Pettengill, J. Meindl
THE STRINGENT REQUIREMENTS imposed on implantable telemetry systems often preclude continuous operation . In such cases, the operating life of battery powered implants must be extended by the use of a radio-controlled power switch, or command receiver, to disconnect the battery when physiological data are not needed. Micropower monolithic circuits for an implantable command receiver have been demonstrated, but their use has been limited by short range and availability problems . Continuous micropower operation limits this 1 5 PA receiver to a carrier frequency of approximately 1 MHz which results in a range of less than 3 m when a hand-held transmitter is used. By using a new minimum duty-cycle pulse powered command receiver, the carrier frequcncy can be increased to 30 MHz with virtually no increase in current drain compared with the theoretical 30 times increase which continuous powered operation requires. This results in a 1 0 times greater range of 30 m and markedly reduced frequency of false triggering with a receiver drawing only 20 pA of current. The range increase results from improved antenna efficiency and reduced antenna noise figure at the higher frequency3. Receiver availability is substantially enhanced through the use of a Kitchip requiring only one custom metal mask to implement the receiver using a dic with a fixed layout of monolithic elcmcnts4. A block diagram of the pulse powered receiver is shown in Figure 1, and its specifications are given in Table 1. The RF amplifier and detector (Figure 2 u ) are pulse powered reducing power consumption from 1 2 mW to 30 pW of power. While monolithic circuits can be built readily with useful gain at 30 MHz, the inductor tuning or feedback methods typically required to reduce power dissipation and bandwidth in a receiver are not practical in a monolithic realization. However, operation of the receiver in a pulse powcrcd or sampling mode allows the average power dissipation to be reduced5 along with signal bandwidth very easily. Figure 3 shows how this occurs. Previously this pulse-powered technique has been applied to receiver 1
{"title":"Monolithic circuits for a pulse-powered micropower command receiver","authors":"R. Pettengill, J. Meindl","doi":"10.1109/ISSCC.1977.1155654","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155654","url":null,"abstract":"THE STRINGENT REQUIREMENTS imposed on implantable telemetry systems often preclude continuous operation . In such cases, the operating life of battery powered implants must be extended by the use of a radio-controlled power switch, or command receiver, to disconnect the battery when physiological data are not needed. Micropower monolithic circuits for an implantable command receiver have been demonstrated, but their use has been limited by short range and availability problems . Continuous micropower operation limits this 1 5 PA receiver to a carrier frequency of approximately 1 MHz which results in a range of less than 3 m when a hand-held transmitter is used. By using a new minimum duty-cycle pulse powered command receiver, the carrier frequcncy can be increased to 30 MHz with virtually no increase in current drain compared with the theoretical 30 times increase which continuous powered operation requires. This results in a 1 0 times greater range of 30 m and markedly reduced frequency of false triggering with a receiver drawing only 20 pA of current. The range increase results from improved antenna efficiency and reduced antenna noise figure at the higher frequency3. Receiver availability is substantially enhanced through the use of a Kitchip requiring only one custom metal mask to implement the receiver using a dic with a fixed layout of monolithic elcmcnts4. A block diagram of the pulse powered receiver is shown in Figure 1, and its specifications are given in Table 1. The RF amplifier and detector (Figure 2 u ) are pulse powered reducing power consumption from 1 2 mW to 30 pW of power. While monolithic circuits can be built readily with useful gain at 30 MHz, the inductor tuning or feedback methods typically required to reduce power dissipation and bandwidth in a receiver are not practical in a monolithic realization. However, operation of the receiver in a pulse powcrcd or sampling mode allows the average power dissipation to be reduced5 along with signal bandwidth very easily. Figure 3 shows how this occurs. Previously this pulse-powered technique has been applied to receiver 1","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126813950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155664
Pang-Ting Ho, G. Swartz, A. Schwarzmann
{"title":"Low loss PIN diode for high power MIC phase shifter","authors":"Pang-Ting Ho, G. Swartz, A. Schwarzmann","doi":"10.1109/ISSCC.1977.1155664","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155664","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"XX 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131321114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155675
T. O'Connell, J. Hartman, E. Errett, G. Leach, W. Dunn
{"title":"A 4K static clocked and nonclocked RAM design","authors":"T. O'Connell, J. Hartman, E. Errett, G. Leach, W. Dunn","doi":"10.1109/ISSCC.1977.1155675","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155675","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132856809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155673
D. Chisholm
{"title":"Impact of LSI on the telecommunications network","authors":"D. Chisholm","doi":"10.1109/ISSCC.1977.1155673","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155673","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115575141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155709
W. Spence, G. Lockwood, M. Shen, M. Trudel
A WORD ALTERABLE ROM (1024x4 P-channel nonvolatile memory) will be described. It can be used as a block erasable programmable ROM or as a word alterable RAM. Erase and write times are variable depending on the application and data retentivity required. A prime objective is microprocessor system compatibility. All address, data, control and clock lines are TTL compatible with pull-up resistors t o +5V. Input address, data and control lines are latched. Data outputs hold for the duration of the Chip Enable clock and then return to an open circuit condition for operation on a common data bus. Access time is 650 ns.
{"title":"A word alterable ROM","authors":"W. Spence, G. Lockwood, M. Shen, M. Trudel","doi":"10.1109/ISSCC.1977.1155709","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155709","url":null,"abstract":"A WORD ALTERABLE ROM (1024x4 P-channel nonvolatile memory) will be described. It can be used as a block erasable programmable ROM or as a word alterable RAM. Erase and write times are variable depending on the application and data retentivity required. A prime objective is microprocessor system compatibility. All address, data, control and clock lines are TTL compatible with pull-up resistors t o +5V. Input address, data and control lines are latched. Data outputs hold for the duration of the Chip Enable clock and then return to an open circuit condition for operation on a common data bus. Access time is 650 ns.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121513798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155677
D. Estreich, R. Dutton
CONVENTIONAL integrated injection logicl~’ (12L) has the attractive features of high density, low power-delay product, and simple fabrication sequence. However, the NPN current gain falloff associated with narrow, high fanout 12L gates severely limits the maximum gate operational speed. Furthermore, high current effects reduce injector transport efficiency, thus, increasing the powerdelay product. Figure 1 shows a complete 12L macromodel which includes the NPN current gain falloff and injector high current effects. Lateral current transport between adjacent gates is included in the macromodel’. The macromodel is synthesized from standard circuit elements making it compatible with commonly used circuit simulators, and, except for the NPN base resistance, requires only readily measured electrical parameters for definition; Table I. Ebers-Moll equivalent circuits are used to model the NPN transistor action of each collector; Q 1 Qq in Figure 1 for a fanout of four gate. Modeling the high-current NPN current gain falloff characteristics requires proper partitioning of the NPN base recombination currents and inclusion of the base resistance. Figure 2(a) illustrates the partitioning of the NPN base region for a narrow, fanout of four gate with base contact nearest the injector end. Section A is the base contact region and sections B-E are the active regions. The fractional recombination current for each active section is modeled by the dc current gain of the NPN, whereas, for the base contact region, it is accounted for by the saturation current of diode DCN. Base current measurements are required for gates of differing fanout counts using a consistent set of layout rules and fabrication. Figure 2(b) shows the partitioned base region with injected current de current paths, assuming the injector to be located at the base contact end of the base region. Using the geometry of these shaded current paths and the base sheet resistance, the b a e resistance components may be determined. Base resistance components, RBI R B ~ , are included in the macromodel as -
传统的集成注射逻辑(12L)具有密度高、产品功耗低、制作流程简单等优点。然而，与窄的高扇出12L栅极相关的NPN电流增益衰减严重限制了栅极的最大工作速度。此外，高电流效应降低了注入器传输效率，从而增加了功率延迟积。图1显示了一个完整的12L宏模型，包括NPN电流增益衰减和注入器高电流效应。相邻栅极之间的横向电流传输包含在宏模型中。宏模型由标准电路元件合成，使其与常用的电路模拟器兼容，并且，除了NPN基极电阻外，只需要容易测量的电气参数即可定义;表1 . Ebers-Moll等效电路用于模拟每个集电极的NPN晶体管作用;q1 Qq在图1中为四门扇出。对大电流NPN电流增益衰减特性进行建模需要对NPN基极重组电流进行适当的划分，并包含基极电阻。图2(a)示出了NPN基区的划分，为一个狭窄的四栅极扇出，基触点最靠近喷射器端。截面A为基接触区域，截面B-E为活动区域。每个有源部分的分数级复合电流由NPN的直流增益来建模，而基极接触区域的分数级复合电流由二极管DCN的饱和电流来表示。使用一套一致的布局规则和制造，需要对不同扇出计数的门进行基本电流测量。图2(b)显示了带有注入电流去电流路径的划分基区，假设注入器位于基区的基极接触端。利用这些阴影电流路径的几何形状和基片电阻，可以确定b - a - e电阻分量。基电阻分量RBI RB ~以-形式包含在宏模型中
{"title":"Modeling I2L performance and operational limits","authors":"D. Estreich, R. Dutton","doi":"10.1109/ISSCC.1977.1155677","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155677","url":null,"abstract":"CONVENTIONAL integrated injection logicl~’ (12L) has the attractive features of high density, low power-delay product, and simple fabrication sequence. However, the NPN current gain falloff associated with narrow, high fanout 12L gates severely limits the maximum gate operational speed. Furthermore, high current effects reduce injector transport efficiency, thus, increasing the powerdelay product. Figure 1 shows a complete 12L macromodel which includes the NPN current gain falloff and injector high current effects. Lateral current transport between adjacent gates is included in the macromodel’. The macromodel is synthesized from standard circuit elements making it compatible with commonly used circuit simulators, and, except for the NPN base resistance, requires only readily measured electrical parameters for definition; Table I. Ebers-Moll equivalent circuits are used to model the NPN transistor action of each collector; Q 1 Qq in Figure 1 for a fanout of four gate. Modeling the high-current NPN current gain falloff characteristics requires proper partitioning of the NPN base recombination currents and inclusion of the base resistance. Figure 2(a) illustrates the partitioning of the NPN base region for a narrow, fanout of four gate with base contact nearest the injector end. Section A is the base contact region and sections B-E are the active regions. The fractional recombination current for each active section is modeled by the dc current gain of the NPN, whereas, for the base contact region, it is accounted for by the saturation current of diode DCN. Base current measurements are required for gates of differing fanout counts using a consistent set of layout rules and fabrication. Figure 2(b) shows the partitioned base region with injected current de current paths, assuming the injector to be located at the base contact end of the base region. Using the geometry of these shaded current paths and the base sheet resistance, the b a e resistance components may be determined. Base resistance components, RBI R B ~ , are included in the macromodel as -","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122576514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155712
Y. Takayama, K. Honjo, A. Higahisaka, F. Hasegawa
IN MICROWAVE circuit applications of high power GaAs FETs with as much as 1-W output, matching limitations for lowimpedance devices, resulting from fixed parasitic elements in mounting and packaging of device chips, are serious problems. To solve such matching limitations and achieve broadband power amplification, the introduction of internal matching networks seems effective. This paper will describe broadband internal matching developed for high-power GaAs MESFETs at C-band, adopting both small-signal and large-signal characterizations in the circuit design. The internally matched FET that has been developed is 4.5 mm in length, has a 1-W power output at 1-dB gain compression and a 1.8-W saturated power output with a linear gain of 6.5 dB from 4.6 to 7.6 GHz, without external matching. The FET has a two-cell single-chip structure which has 56 parallel-gates with four bonding pads, and four drain pads. The gate length is 1.3 p m and the total gate width is 5600 pm. To reduce bonding wire inductance for source grounding, the source electrode is grounded by metal thin films evaporated on the device periphery without bonding wires. An input-matching network of the lumped-element twosection low-pass type and an output-matching network of one-section semidistributed form were designed, as shown in Figure 1. For broadband power amplification, the design of the input and output networks was based on the use of measured small-signal S-parameters of the FET chip. Initial values for the input network elements were determined by defining a Chebyshev impedance-matching network of lowpass filter form, after canceling an input reactance with a series inductance at 6 GHz. Then, based on the initial circuit element values and the S-parameters, detailed fitting was performed by computer simulation. In this process of simulation, especially for the output network, to achieve broadband high-power saturation, large-signal matching was attempted by considering the increase of the optimum load conductance of the FET with the increase of input power drive level. With an equivalent load-pull characterization method’ developed in the laboratory, large-signal power-load characteristics of the FET with the internal matching networks were measured. It was confirmed, as shown in Figure 3, that the optimum load for power output approaches 5 0 o h m with the increase of input power level. In the figure, the bullets show small-signal output impedances and triangler/squares indicate optimum power load impedances in large-signal operation. Now, the small-signal optimum load impedance is the complex
{"title":"Internally matched microwave broadband linear power FET","authors":"Y. Takayama, K. Honjo, A. Higahisaka, F. Hasegawa","doi":"10.1109/ISSCC.1977.1155712","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155712","url":null,"abstract":"IN MICROWAVE circuit applications of high power GaAs FETs with as much as 1-W output, matching limitations for lowimpedance devices, resulting from fixed parasitic elements in mounting and packaging of device chips, are serious problems. To solve such matching limitations and achieve broadband power amplification, the introduction of internal matching networks seems effective. This paper will describe broadband internal matching developed for high-power GaAs MESFETs at C-band, adopting both small-signal and large-signal characterizations in the circuit design. The internally matched FET that has been developed is 4.5 mm in length, has a 1-W power output at 1-dB gain compression and a 1.8-W saturated power output with a linear gain of 6.5 dB from 4.6 to 7.6 GHz, without external matching. The FET has a two-cell single-chip structure which has 56 parallel-gates with four bonding pads, and four drain pads. The gate length is 1.3 p m and the total gate width is 5600 pm. To reduce bonding wire inductance for source grounding, the source electrode is grounded by metal thin films evaporated on the device periphery without bonding wires. An input-matching network of the lumped-element twosection low-pass type and an output-matching network of one-section semidistributed form were designed, as shown in Figure 1. For broadband power amplification, the design of the input and output networks was based on the use of measured small-signal S-parameters of the FET chip. Initial values for the input network elements were determined by defining a Chebyshev impedance-matching network of lowpass filter form, after canceling an input reactance with a series inductance at 6 GHz. Then, based on the initial circuit element values and the S-parameters, detailed fitting was performed by computer simulation. In this process of simulation, especially for the output network, to achieve broadband high-power saturation, large-signal matching was attempted by considering the increase of the optimum load conductance of the FET with the increase of input power drive level. With an equivalent load-pull characterization method’ developed in the laboratory, large-signal power-load characteristics of the FET with the internal matching networks were measured. It was confirmed, as shown in Figure 3, that the optimum load for power output approaches 5 0 o h m with the increase of input power level. In the figure, the bullets show small-signal output impedances and triangler/squares indicate optimum power load impedances in large-signal operation. Now, the small-signal optimum load impedance is the complex","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128449547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155699
P. Bura, R. Dikshit, P. Mercer
{"title":"All FET communications satellite transponder receiver","authors":"P. Bura, R. Dikshit, P. Mercer","doi":"10.1109/ISSCC.1977.1155699","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155699","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126268970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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