Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611475
Min-Chuan Chen, Weimin Wu, Jinian Bian
We present a special approach to solving satisfiability problem in RTL (register transfer level) circuit, which contains both Boolean logics and word-level arithmetics. In our approach, an ATPG (automatic test pattern generation) based satisfiability solver is implemented on RTL netlist model. As expert tool for circuits, our ATPG engine employs fast constraint propagation, where all the signals are treated as integers. For the undecided signals, we render a depth-first search. The huge search space is cut down by some heuristics. Experimental results on ITC benchmarks demonstrate the feasibility and efficiency of our techniques.
{"title":"RTL satisfiability solving using an ATPG based approach","authors":"Min-Chuan Chen, Weimin Wu, Jinian Bian","doi":"10.1109/ICASIC.2005.1611475","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611475","url":null,"abstract":"We present a special approach to solving satisfiability problem in RTL (register transfer level) circuit, which contains both Boolean logics and word-level arithmetics. In our approach, an ATPG (automatic test pattern generation) based satisfiability solver is implemented on RTL netlist model. As expert tool for circuits, our ATPG engine employs fast constraint propagation, where all the signals are treated as integers. For the undecided signals, we render a depth-first search. The huge search space is cut down by some heuristics. Experimental results on ITC benchmarks demonstrate the feasibility and efficiency of our techniques.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123178736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611474
Dongjun Lou, J.S. Yuan, Daguang Li, C. Jacobs
Bit-level hardware description language (HDL), such as Verilog or VHDL, has its interior problems to describe complex math formulas in register transaction level (RTL). Its Boolean solutions lead to the necessity of complex controls for math operations, and often result in poor performance for datapath verification. Instead of solving the problem at the bit-level, a method of SystemC reference model (SCRM) is proposed to aid conjunctions of bitvector manipulations in RTL into arithmetic number operations in SystemC, which helps to verify the datapath design automatically. The application experience of SCRM in our digital still camera SoC shows that it is much more efficient and thorough to verify the datapath with the assistance of cycle accurate SystemC models realtimely, than previously manual verification
{"title":"Datapath verification with SystemC reference model","authors":"Dongjun Lou, J.S. Yuan, Daguang Li, C. Jacobs","doi":"10.1109/ICASIC.2005.1611474","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611474","url":null,"abstract":"Bit-level hardware description language (HDL), such as Verilog or VHDL, has its interior problems to describe complex math formulas in register transaction level (RTL). Its Boolean solutions lead to the necessity of complex controls for math operations, and often result in poor performance for datapath verification. Instead of solving the problem at the bit-level, a method of SystemC reference model (SCRM) is proposed to aid conjunctions of bitvector manipulations in RTL into arithmetic number operations in SystemC, which helps to verify the datapath design automatically. The application experience of SCRM in our digital still camera SoC shows that it is much more efficient and thorough to verify the datapath with the assistance of cycle accurate SystemC models realtimely, than previously manual verification","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123273360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611253
Jian Gao, Jing Chen
The paper describes a 16-bit high-speed and low-power multiply-accumulate unit (MAC) designed for DSP processor. The extreme power reduction derives from the asynchronous interlocked pipeline technique MAC adopts. And the speed is greatly increased by introducing the complemented partial product word correction (CP-PWC) algorithm and 3D reduction method (TDM) in the partial product generation and reduction. MAC shows low power dissipation and high speed and the DSP processor embedded with MAC has been implemented in 0.18 CMOS technology.
{"title":"A novel asynchronous multiple function multiply-accumulator","authors":"Jian Gao, Jing Chen","doi":"10.1109/ICASIC.2005.1611253","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611253","url":null,"abstract":"The paper describes a 16-bit high-speed and low-power multiply-accumulate unit (MAC) designed for DSP processor. The extreme power reduction derives from the asynchronous interlocked pipeline technique MAC adopts. And the speed is greatly increased by introducing the complemented partial product word correction (CP-PWC) algorithm and 3D reduction method (TDM) in the partial product generation and reduction. MAC shows low power dissipation and high speed and the DSP processor embedded with MAC has been implemented in 0.18 CMOS technology.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123069983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611278
R. Agrawal, N. Gupta
Voice over Internet protocol (VoIP) is the transmission of voice over networks using the internet protocol. IP networks have become increasingly popular in the past few years, due to the exponential growth of the public internet leading the way in to the IP world. Long distance calls, especially international subscriber dialing (ISD), can be made significantly less expensive when supported by an IP network rather than by the PSTN. Any call made is supported by VoIP technology and it involves the transmission of many individual packets over an IP network. Thus the cost of VoIP calls in part depends on the number and size of packets that must be transmitted. So voice (source) compression technology is used to reduce the amount of bandwidth required in order to reduce cost and to reduce the delay impact from network. But, compression techniques increase the network impairments also. When packets are transmitted through network they are affected by impairments, like packet drop and end-to-end delay. The main agenda of VoIP service providers is to provide good quality of service (QoS). The objective of this research work done is to minimize, the error introduced in channel due to the above mentioned network impairments and hence improve the quality of sound, and also analyze the voice quality with and without use of channel coding scheme. There are two measuring techniques, subjective and objective. In subjective method we measure the mean opinion score (MOS) and use matching algorithms in objective methods to measure the difference between decoded outputs of source coding system and joint source-channel coding system. In this work, the objective method is used and it is observed that the performance of the system improves significantly
VoIP (Voice over Internet protocol)是一种利用Internet协议在网络上进行语音传输的技术。在过去的几年里，由于公共互联网的指数级增长引领了IP世界的发展，IP网络变得越来越流行。长途电话，特别是国际用户拨号(ISD)，如果由IP网络而不是PSTN支持，可以大大降低成本。任何呼叫都由VoIP技术支持，它涉及在IP网络上传输许多单独的数据包。因此，VoIP通话的费用部分取决于必须传输的数据包的数量和大小。因此，语音(源)压缩技术被用于减少所需的带宽，以降低成本和减少网络的延迟影响。但是，压缩技术也增加了网络损害。当数据包通过网络传输时，它们会受到损伤的影响，比如数据包丢失和端到端延迟。VoIP服务提供商的主要议程是提供良好的服务质量(QoS)。本研究工作的目的是尽量减少由于上述网络缺陷导致的信道误差，从而提高声音质量，并分析使用信道编码方案和不使用信道编码方案的语音质量。有两种测量技术，主观和客观。在主观方法中，我们测量平均意见分数(MOS)，在客观方法中，我们使用匹配算法来测量源编码系统和源信道联合编码系统的解码输出之间的差异。在这项工作中，采用了客观方法，观察到系统的性能有了明显的提高
{"title":"To improve the voice quality over IP using channel coding","authors":"R. Agrawal, N. Gupta","doi":"10.1109/ICASIC.2005.1611278","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611278","url":null,"abstract":"Voice over Internet protocol (VoIP) is the transmission of voice over networks using the internet protocol. IP networks have become increasingly popular in the past few years, due to the exponential growth of the public internet leading the way in to the IP world. Long distance calls, especially international subscriber dialing (ISD), can be made significantly less expensive when supported by an IP network rather than by the PSTN. Any call made is supported by VoIP technology and it involves the transmission of many individual packets over an IP network. Thus the cost of VoIP calls in part depends on the number and size of packets that must be transmitted. So voice (source) compression technology is used to reduce the amount of bandwidth required in order to reduce cost and to reduce the delay impact from network. But, compression techniques increase the network impairments also. When packets are transmitted through network they are affected by impairments, like packet drop and end-to-end delay. The main agenda of VoIP service providers is to provide good quality of service (QoS). The objective of this research work done is to minimize, the error introduced in channel due to the above mentioned network impairments and hence improve the quality of sound, and also analyze the voice quality with and without use of channel coding scheme. There are two measuring techniques, subjective and objective. In subjective method we measure the mean opinion score (MOS) and use matching algorithms in objective methods to measure the difference between decoded outputs of source coding system and joint source-channel coding system. In this work, the objective method is used and it is observed that the performance of the system improves significantly","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125817094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611362
Ting-Hua Yun, Li Yin, S. Tang, Jianhui Wu
A CMOS IF VGA used for DVB-C receivers is presented in this paper. The VGA core is based on current-steering structure, and several optimization methods are used to improve the linearity and stability. A novel CMOS exponential voltage generator is designed to realize the linear-in-dB control characteristic. The simulation results based on 0.25 mum CMOS process indicate that the VGA can provide 40dB gain control range, the IIP3 at the minimum gain setting 17.2 dBm, and the minimum NF 7.8 dB. The overall current dissipation is less than 23 mA at 3.3V supply voltage
本文介绍了一种用于DVB-C接收机的CMOS中频VGA电路。VGA核心基于电流转向结构，采用了多种优化方法来提高其线性度和稳定性。设计了一种新型的CMOS指数电压发生器，实现了其在db中的线性控制特性。基于0.25 μ m CMOS工艺的仿真结果表明，VGA可提供40dB增益控制范围，IIP3最小增益设置为17.2 dBm，最小NF为7.8 dB。在3.3V电源电压下，整体电流损耗小于23ma
{"title":"A 40dB, 100MHz CMOS IF variable gain amplifier for DVB-C receivers","authors":"Ting-Hua Yun, Li Yin, S. Tang, Jianhui Wu","doi":"10.1109/ICASIC.2005.1611362","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611362","url":null,"abstract":"A CMOS IF VGA used for DVB-C receivers is presented in this paper. The VGA core is based on current-steering structure, and several optimization methods are used to improve the linearity and stability. A novel CMOS exponential voltage generator is designed to realize the linear-in-dB control characteristic. The simulation results based on 0.25 mum CMOS process indicate that the VGA can provide 40dB gain control range, the IIP3 at the minimum gain setting 17.2 dBm, and the minimum NF 7.8 dB. The overall current dissipation is less than 23 mA at 3.3V supply voltage","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124988324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611314
Zhang Xun, Wang Peng, Jin Dong-ming
A novel domain adaptive fuzzy logic controller is presented in this paper, which adds a domain adaptive structure on the architecture of an original fuzzy logic controller. It saves the hardware consumption, and accelerates the system convergence. The domain mapping fuzzy logic controller is successfully applied to control the inverted pendulum on a hardware test-bed. The theory and optimization of the method are also discussed. According to this strategy, a circuit can generate domain mapping gene is realized by CSMC 0.6mum mixed-signal technology. This approach provides a valuable theory basement to the implement of self-adaptive fuzzy controller hardware chip
{"title":"VLSI architectures of domain adaptive fuzzy logic system","authors":"Zhang Xun, Wang Peng, Jin Dong-ming","doi":"10.1109/ICASIC.2005.1611314","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611314","url":null,"abstract":"A novel domain adaptive fuzzy logic controller is presented in this paper, which adds a domain adaptive structure on the architecture of an original fuzzy logic controller. It saves the hardware consumption, and accelerates the system convergence. The domain mapping fuzzy logic controller is successfully applied to control the inverted pendulum on a hardware test-bed. The theory and optimization of the method are also discussed. According to this strategy, a circuit can generate domain mapping gene is realized by CSMC 0.6mum mixed-signal technology. This approach provides a valuable theory basement to the implement of self-adaptive fuzzy controller hardware chip","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121478481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611441
Xiangyuan Liu, Shuming Chen
Interconnection techniques play an important role in the growth of semiconductor industry into future generations. A novel hybrid insertion strategy based on repeaters and low-swing differential-signaling circuits for global interconnect is presented in this paper. It takes advantage of those circuits on driving long wires in different length, and optimally inserts them along the wires. Simulation results using HSPICE for 0.18mum process show that delay, energy, energy-delay-product (EDP) and area are considerably decreased compared with other strategies available. Moreover, it is very suitable for integration in an EDA tool flow and helpful to the reuse of low-swing differential-signaling circuits
{"title":"Interconnect delay optimization using a novel hybrid insertion strategy","authors":"Xiangyuan Liu, Shuming Chen","doi":"10.1109/ICASIC.2005.1611441","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611441","url":null,"abstract":"Interconnection techniques play an important role in the growth of semiconductor industry into future generations. A novel hybrid insertion strategy based on repeaters and low-swing differential-signaling circuits for global interconnect is presented in this paper. It takes advantage of those circuits on driving long wires in different length, and optimally inserts them along the wires. Simulation results using HSPICE for 0.18mum process show that delay, energy, energy-delay-product (EDP) and area are considerably decreased compared with other strategies available. Moreover, it is very suitable for integration in an EDA tool flow and helpful to the reuse of low-swing differential-signaling circuits","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125121252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611261
Wang Xuejing, Ye Fan, R. Junyan
An optimum design of decision feedback equalizer (DFE) used in Ethernet is presented. This paper proposes two improving measures for physical implementation - the hybrid form and the coefficient updating unit sharing. According to the results of synthesis using SMIC, 0.18/spl mu/m CMOS process, the speed, area and power consumption of the improved DFE is optimized by 16%, 36% and 39% compared with the transposed form implementation.
提出了一种用于以太网的决策反馈均衡器的优化设计方法。本文提出了物理实现的两种改进措施——混合形式和系数更新单元共享。根据采用中芯0.18/spl μ m CMOS工艺合成的结果，改进后的DFE与转置形式实现相比，速度、面积和功耗分别优化了16%、36%和39%。
{"title":"An optimization of VLSI architecture for DFE used in Ethernet","authors":"Wang Xuejing, Ye Fan, R. Junyan","doi":"10.1109/ICASIC.2005.1611261","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611261","url":null,"abstract":"An optimum design of decision feedback equalizer (DFE) used in Ethernet is presented. This paper proposes two improving measures for physical implementation - the hybrid form and the coefficient updating unit sharing. According to the results of synthesis using SMIC, 0.18/spl mu/m CMOS process, the speed, area and power consumption of the improved DFE is optimized by 16%, 36% and 39% compared with the transposed form implementation.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114021455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611289
Lin Yi-fan, Zeng Xiao-yang, Wu Min, Chen Jun, Bao Rencheng
With the rapid development on the software-hardware co-verification of SoC, FPGA verification has become more and more critical for VLSI design, and it requires much more portion of time within the life circle of chip development. The time spent on the FPGA verification should be reduced to achieve a more efficient time-to-market for the IC product. Therefore, several strategies using both dynamic and static methods to execute this verification are proposed in this paper. By using a variety of techniques such as software static breakpoint monitoring and interrupt vectors remapping, the software verification is accelerated. A bus analyzer is adopted to provide real-time bus monitoring with a vivid evaluation of the system performance. In this paper, experiments show that above methods have greatly enhanced the efficiency and speed of the FPGA co-verification process
{"title":"New methods of FPGA co-verification for system on chip (SoC)","authors":"Lin Yi-fan, Zeng Xiao-yang, Wu Min, Chen Jun, Bao Rencheng","doi":"10.1109/ICASIC.2005.1611289","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611289","url":null,"abstract":"With the rapid development on the software-hardware co-verification of SoC, FPGA verification has become more and more critical for VLSI design, and it requires much more portion of time within the life circle of chip development. The time spent on the FPGA verification should be reduced to achieve a more efficient time-to-market for the IC product. Therefore, several strategies using both dynamic and static methods to execute this verification are proposed in this paper. By using a variety of techniques such as software static breakpoint monitoring and interrupt vectors remapping, the software verification is accelerated. A bus analyzer is adopted to provide real-time bus monitoring with a vivid evaluation of the system performance. In this paper, experiments show that above methods have greatly enhanced the efficiency and speed of the FPGA co-verification process","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131587608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611419
Wu Chao, Wang Hong, Y. Shi-yuan
IEEE P1500 is a standard under development which intends to improve ease of test reuse and test integration with respect to the core-based SoCs. This paper proposes a P1500-compliant wrapper and TAM controller design scheme. Area overhead and power consumption are taken into account in our scheme. Some experiment results based on a sample SoC are reported, showing the effectiveness of the proposed approach in terms of area overhead
{"title":"A P1500-compliant wrapper and TAM controller co-design scheme","authors":"Wu Chao, Wang Hong, Y. Shi-yuan","doi":"10.1109/ICASIC.2005.1611419","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611419","url":null,"abstract":"IEEE P1500 is a standard under development which intends to improve ease of test reuse and test integration with respect to the core-based SoCs. This paper proposes a P1500-compliant wrapper and TAM controller design scheme. Area overhead and power consumption are taken into account in our scheme. Some experiment results based on a sample SoC are reported, showing the effectiveness of the proposed approach in terms of area overhead","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131610793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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