Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611497
Dong-sheng Yang, Xin-zhi Shi, Gaofeng Wang
High-level synthesis is highly demanded for managing the complexity of mixed-signal system designs. However, synthesis methods are currently in their infancy before the VHDL-AMS. The absence of a high-level specification notation is an important limitation for the development of efficient synthesis methods. VHDL-AMS which is built on IEEE Std. 1076-1993 (VHDL) is the IEEE 1076.1-1999 language, a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems. This paper introduces the modeling characteristics supported by VHDL-AMS, analyzes modeling methodology of the mixed-signal system and some issues about modeling methods. Finally the paper builds the mixed-signal system modeling and simulation through examples
{"title":"Mixed-signal system modeling methodology with VHDL-AMS","authors":"Dong-sheng Yang, Xin-zhi Shi, Gaofeng Wang","doi":"10.1109/ICASIC.2005.1611497","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611497","url":null,"abstract":"High-level synthesis is highly demanded for managing the complexity of mixed-signal system designs. However, synthesis methods are currently in their infancy before the VHDL-AMS. The absence of a high-level specification notation is an important limitation for the development of efficient synthesis methods. VHDL-AMS which is built on IEEE Std. 1076-1993 (VHDL) is the IEEE 1076.1-1999 language, a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems. This paper introduces the modeling characteristics supported by VHDL-AMS, analyzes modeling methodology of the mixed-signal system and some issues about modeling methods. Finally the paper builds the mixed-signal system modeling and simulation through examples","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123224604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611332
Qianneng Zhou, Mingyan Yu, Jianguo Ma, Y. Ye
This paper presents a novel on-chip DC-DC voltage down converter (VDC): a temperature-independence reference voltage generator and a voltage-up converter. The architecture of the proposed VDC is simple, and can be fabricated by conventional CMOS technology. For 5 V to 3.3 V conversions, it provides an output voltage insusceptible to external supply-voltage bouncing, temperature variation, and load current variation. A temperature dependency of only 0.65 mV//spl deg/C and a voltage deviation within /spl plusmn/0.16% for /spl plusmn/10% variation of external supply voltage are achieved. The voltage is stabilized with /spl plusmn/17 mV for load current varying from 0 to 100 mA.
{"title":"On-chip DC-DC voltage down converter for low-power IC chip","authors":"Qianneng Zhou, Mingyan Yu, Jianguo Ma, Y. Ye","doi":"10.1109/ICASIC.2005.1611332","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611332","url":null,"abstract":"This paper presents a novel on-chip DC-DC voltage down converter (VDC): a temperature-independence reference voltage generator and a voltage-up converter. The architecture of the proposed VDC is simple, and can be fabricated by conventional CMOS technology. For 5 V to 3.3 V conversions, it provides an output voltage insusceptible to external supply-voltage bouncing, temperature variation, and load current variation. A temperature dependency of only 0.65 mV//spl deg/C and a voltage deviation within /spl plusmn/0.16% for /spl plusmn/10% variation of external supply voltage are achieved. The voltage is stabilized with /spl plusmn/17 mV for load current varying from 0 to 100 mA.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115539522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611496
Lai Xin-quan, L. Gang, Guo Jianping, Cao Yu
The use of behavioral modeling technique is applied to the stability analysis of the voltage mode PWM DC-DC converter. The behavioral models of its building blocks are developed with Verilog-AMS. The guidelines for structure and component values of the compensation network are presented. Simulation results are performed to verify the proposed models and the stability of the compensated system
{"title":"Stability Analysis of C- C Converter sing Behavioral Modeling Technique","authors":"Lai Xin-quan, L. Gang, Guo Jianping, Cao Yu","doi":"10.1109/ICASIC.2005.1611496","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611496","url":null,"abstract":"The use of behavioral modeling technique is applied to the stability analysis of the voltage mode PWM DC-DC converter. The behavioral models of its building blocks are developed with Verilog-AMS. The guidelines for structure and component values of the compensation network are presented. Simulation results are performed to verify the proposed models and the stability of the compensated system","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122134547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611311
Bin Sheng, Wen Gao, Di Wu
AVS is Chinese new audio and video coding standard. A pipeline-based architecture of inverse quantizer for AVS video standard is proposed in this paper. Due to using one-pass processing for run length decoding, inverse scan and inverse quantization, the architecture can save many buffers, which are used to store intermediate results during multi-pass processing. Furthermore, the processing speed is up to one coefficient per clock cycle. This architecture has been described in Verilog HDL, simulated with VCS digital simulator, and synthesized using 0.18mum CMOS cells library by Synopsys design compiler. The circuit totally costs about 13.7k logic gates when running at 200MHz. Simulation results show that the architecture can support real-time inverse quantization for HDTV (1280times720, 60fps) video. This architecture has been implemented in a single chip HDTV decoder for AVS video and audio
AVS是中国新的音视频编码标准。针对AVS视频标准，提出了一种基于流水线的逆量化器结构。由于该结构对码长解码、反扫描和反量化采用一遍处理，因此可以节省大量缓冲区，用于存储多遍处理时的中间结果。此外，每个时钟周期的处理速度高达一个系数。该体系结构用Verilog HDL语言进行了描述，用VCS数字模拟器进行了仿真，并用Synopsys设计编译器使用0.18 μ m CMOS单元库进行了合成。当电路运行在200MHz时，总共花费约13.7k逻辑门。仿真结果表明，该结构能够支持HDTV (1280times720, 60fps)视频的实时逆量化。该架构已在AVS视频和音频的单芯片HDTV解码器中实现
{"title":"An implemented VLSI architecture of inverse quantizer for AVS HDTV video decoder","authors":"Bin Sheng, Wen Gao, Di Wu","doi":"10.1109/ICASIC.2005.1611311","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611311","url":null,"abstract":"AVS is Chinese new audio and video coding standard. A pipeline-based architecture of inverse quantizer for AVS video standard is proposed in this paper. Due to using one-pass processing for run length decoding, inverse scan and inverse quantization, the architecture can save many buffers, which are used to store intermediate results during multi-pass processing. Furthermore, the processing speed is up to one coefficient per clock cycle. This architecture has been described in Verilog HDL, simulated with VCS digital simulator, and synthesized using 0.18mum CMOS cells library by Synopsys design compiler. The circuit totally costs about 13.7k logic gates when running at 200MHz. Simulation results show that the architecture can support real-time inverse quantization for HDTV (1280times720, 60fps) video. This architecture has been implemented in a single chip HDTV decoder for AVS video and audio","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129338753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611482
Xin-zhi Shi, Dong-sheng Yang, Gaofeng Wang
A novel approach for transient analysis of coupled transmission line circuits based on the generalized inverse matrix Fade approximation (GIMPA) is presented. The numerical result proved that this approach is efficient and accurate for treating coupled, nonuniform, lossy, and dispersive transmission line circuits
{"title":"A novel method to simulating transient response of interconnects","authors":"Xin-zhi Shi, Dong-sheng Yang, Gaofeng Wang","doi":"10.1109/ICASIC.2005.1611482","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611482","url":null,"abstract":"A novel approach for transient analysis of coupled transmission line circuits based on the generalized inverse matrix Fade approximation (GIMPA) is presented. The numerical result proved that this approach is efficient and accurate for treating coupled, nonuniform, lossy, and dispersive transmission line circuits","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"613 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124629659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611267
Mei Xiao-Lu
The leading zero anticipation (LZA) is vital in the floating-point fused multiply-add (FMA) units. The general LZA algorithms can only deal with 2 operands. It increases the critical path delay of high performance floating-point FMA units. The paper presents a novel LZA algorithm to deal with 3 operands directly and implemented the 106-bit leading zero anticipator in the high performance floating-point FMA with the general LZA algorithm and the proposed LZA algorithm respectively. Compared with the general leading zero anticipator, the proposed leading zero anticipator can reduce the delay of the critical path by 16.67% and reduce the area by 19.63% approximately.
{"title":"Leading zero anticipation for latency improvement in floating-point fused multiply-add units","authors":"Mei Xiao-Lu","doi":"10.1109/ICASIC.2005.1611267","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611267","url":null,"abstract":"The leading zero anticipation (LZA) is vital in the floating-point fused multiply-add (FMA) units. The general LZA algorithms can only deal with 2 operands. It increases the critical path delay of high performance floating-point FMA units. The paper presents a novel LZA algorithm to deal with 3 operands directly and implemented the 106-bit leading zero anticipator in the high performance floating-point FMA with the general LZA algorithm and the proposed LZA algorithm respectively. Compared with the general leading zero anticipator, the proposed leading zero anticipator can reduce the delay of the critical path by 16.67% and reduce the area by 19.63% approximately.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124641490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611395
Tuo Wu, Hongyi Chen, Dahong Qian
The electrostatic capacitive microactuator has a critical minimum gap due to potential pull-in and tip-in phenomena. Since constant charge drive permits more stable operation range than constant voltage drive, current drive based on charge drive is attractive owing to its good controllability. Due to quasistatic precondition, a method of pulsed multilevel current drive is adopted to boost the refreshing frequency and charge level. An 80 times 80-actuator array with a refreshing frequency of 10 kHz and an 8-bit charge level is realized with this method
{"title":"Pulsed multilevel current drive circuitry with LDMOS for monolithic deformable mirror","authors":"Tuo Wu, Hongyi Chen, Dahong Qian","doi":"10.1109/ICASIC.2005.1611395","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611395","url":null,"abstract":"The electrostatic capacitive microactuator has a critical minimum gap due to potential pull-in and tip-in phenomena. Since constant charge drive permits more stable operation range than constant voltage drive, current drive based on charge drive is attractive owing to its good controllability. Due to quasistatic precondition, a method of pulsed multilevel current drive is adopted to boost the refreshing frequency and charge level. An 80 times 80-actuator array with a refreshing frequency of 10 kHz and an 8-bit charge level is realized with this method","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126989368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611426
Junni Zou, R. Lin, Minglai Liu
This paper presents the field programmable gate array (FPGA) design and implementation of the OLT used for Ethernet passive optical network (EPON). To reduce working frequency of the FPGA, the byte-to-word conversion is proposed. Propagation delays are equalized by ranging procedure so as to avoid data collision. VLAN solution is illustrated in detail to guarantee data segregation and priority scheduling. A fast CAM scheme is introduced to finish search operation in one clock cycle. Experimental results show that the proposed system can function properly in a low cost FPGA
{"title":"Design and FPGA implementation of OLT for EPON","authors":"Junni Zou, R. Lin, Minglai Liu","doi":"10.1109/ICASIC.2005.1611426","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611426","url":null,"abstract":"This paper presents the field programmable gate array (FPGA) design and implementation of the OLT used for Ethernet passive optical network (EPON). To reduce working frequency of the FPGA, the byte-to-word conversion is proposed. Propagation delays are equalized by ranging procedure so as to avoid data collision. VLAN solution is illustrated in detail to guarantee data segregation and priority scheduling. A fast CAM scheme is introduced to finish search operation in one clock cycle. Experimental results show that the proposed system can function properly in a low cost FPGA","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124181498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
IEEE 802.15.3a is assumed to be candidate MAC protocol for emerging UWB techniques. To make MAC system flexible, configurable and easy to upgrade, we tried to make most of MAC functionalities as software/firmware process running in CPU for controlling UWB network card and maintaining high-data-rate WPAN network. But 480Mbps data rate requires some MAC functionality to respond in several microseconds and it is beyond the capability of current software without any hardware preprocessing. After carefully analyzing the bottleneck of timing requirements, we put forward an optimized MAC hardware protocol accelerator and integrated it in our flexible HW/SW system. Performance analysis shows that the throughput, delay etc. were greatly improved
{"title":"Flexible platform design of IEEE 802.15.3a MAC over UWB with optimized protocol accelerator","authors":"Yu Cai, Yaohui Wu, Hui Li, Feng Liang, Zucheng Zhou","doi":"10.1109/ICASIC.2005.1611292","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611292","url":null,"abstract":"IEEE 802.15.3a is assumed to be candidate MAC protocol for emerging UWB techniques. To make MAC system flexible, configurable and easy to upgrade, we tried to make most of MAC functionalities as software/firmware process running in CPU for controlling UWB network card and maintaining high-data-rate WPAN network. But 480Mbps data rate requires some MAC functionality to respond in several microseconds and it is beyond the capability of current software without any hardware preprocessing. After carefully analyzing the bottleneck of timing requirements, we put forward an optimized MAC hardware protocol accelerator and integrated it in our flexible HW/SW system. Performance analysis shows that the throughput, delay etc. were greatly improved","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114629614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611401
Zhiqiang Gao, Jianguo Ma, Mingyan Yu, Y. Ye
This paper presents a 6th order RF bandpass filter using low-voltage based on active inductor. In the filter, a design technique for a high-Q CMOS active inductor operating in the RF-band is described. Simulated performance presented is shown that the center frequency of filter using a 0.25-mum CMOS process can be operated at the 2.05-2.45 GHz frequency band under a 1.8V power supply and suitable for multiband wireless applications and RF system on-chip
提出了一种基于有源电感的低压六阶射频带通滤波器。在滤波器中，描述了工作在射频波段的高q CMOS有源电感的设计技术。仿真结果表明，在1.8V电源下，采用0.25 μ m CMOS工艺的滤波器中心频率可工作在2.05 ~ 2.45 GHz频段，适用于多频段无线应用和片上射频系统
{"title":"A CMOS RF bandpass filter based on the active inductor","authors":"Zhiqiang Gao, Jianguo Ma, Mingyan Yu, Y. Ye","doi":"10.1109/ICASIC.2005.1611401","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611401","url":null,"abstract":"This paper presents a 6th order RF bandpass filter using low-voltage based on active inductor. In the filter, a design technique for a high-Q CMOS active inductor operating in the RF-band is described. Simulated performance presented is shown that the center frequency of filter using a 0.25-mum CMOS process can be operated at the 2.05-2.45 GHz frequency band under a 1.8V power supply and suitable for multiband wireless applications and RF system on-chip","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116266480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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