Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611251
P. Corsonello, S. Perri, M. Margala
Power analysis is a powerful technique which extracts secret information from smart cards during the execution of their internal computations. For this reason, protecting smart cards against power attacks is of particular concern. In this paper, we propose a new hardware countermeasure, which decorrelates the power consumed by any digital circuit from the data internally elaborated. The new strategy is based on a new charge-pump subsystem and can be used with any logic design style
{"title":"A ew Charge-Pump based Countermeasure against ifferential Power Analysis","authors":"P. Corsonello, S. Perri, M. Margala","doi":"10.1109/ICASIC.2005.1611251","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611251","url":null,"abstract":"Power analysis is a powerful technique which extracts secret information from smart cards during the execution of their internal computations. For this reason, protecting smart cards against power attacks is of particular concern. In this paper, we propose a new hardware countermeasure, which decorrelates the power consumed by any digital circuit from the data internally elaborated. The new strategy is based on a new charge-pump subsystem and can be used with any logic design style","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121569870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611402
Hu Jianyun, He Yan, M. Hao
A high efficient rectifier circuit eliminating threshold voltage drop is presented. Based on conventional full wave bridge rectifier circuit, this rectifier circuit uses bootstrapped circuit technique, so it conquers the problem of threshold voltage drop in conventional rectifier circuit. The characteristic of high efficiency and compatibility with standard CMOS process make the rectifier circuit suitable for RFID transponders where high efficient rectifier circuit is much required
{"title":"High efficient rectifier circuit eliminating threshold voltage drop for RFID transponders","authors":"Hu Jianyun, He Yan, M. Hao","doi":"10.1109/ICASIC.2005.1611402","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611402","url":null,"abstract":"A high efficient rectifier circuit eliminating threshold voltage drop is presented. Based on conventional full wave bridge rectifier circuit, this rectifier circuit uses bootstrapped circuit technique, so it conquers the problem of threshold voltage drop in conventional rectifier circuit. The characteristic of high efficiency and compatibility with standard CMOS process make the rectifier circuit suitable for RFID transponders where high efficient rectifier circuit is much required","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126462044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611412
E. Totev, C. Verhoeven
A simplified measurement procedure is proposed in the determination of out of band signal sensitivity of negative feedback amplifiers. Generally, radiation measurements are best able to emulate practical situations, but are cumbersome and difficult to set up. In the case of negative feedback amplifiers, however, direct injection at the input appears to adequately characterise the device under test. This is verified by carrying out irradiation and injection measurements of a family of operational amplifiers and comparing the relative sensitivities to out of band interference thus obtained
{"title":"Out of band interference measurement of negative feedback amplifiers","authors":"E. Totev, C. Verhoeven","doi":"10.1109/ICASIC.2005.1611412","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611412","url":null,"abstract":"A simplified measurement procedure is proposed in the determination of out of band signal sensitivity of negative feedback amplifiers. Generally, radiation measurements are best able to emulate practical situations, but are cumbersome and difficult to set up. In the case of negative feedback amplifiers, however, direct injection at the input appears to adequately characterise the device under test. This is verified by carrying out irradiation and injection measurements of a family of operational amplifiers and comparing the relative sensitivities to out of band interference thus obtained","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115962547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Featuring a direct-conversion architecture, a 2.4-GHz radio-frequency (RF) transmitter frontend for 802.11b wireless LAN (WLAN) is implemented in 0.18-mum CMOS technology. Direct-conversion architecture minimizes the on-and-off-chip components required and provides a low-cost and low-power solution. The transmitter incorporates two low-pass filters (LPFs), a single-sideband (SSB) mixer, a power amplifier driver and a divide-by-two circuit for quadrature LO generation. The transmitter provides a gain control of 12 dB in 3-dB steps and an output 1-dB compression of 7.7 dBm while delivering a nominal output power of 0 dBm. The chip consumes 40 mA from a 1.8-V supply and occupies an area of 2.5 times 2 mm2 including pads
采用直接转换架构，用于802.11b无线局域网(WLAN)的2.4 ghz射频(RF)发射器前端采用0.18 μ m CMOS技术实现。直接转换架构最大限度地减少了所需的片内和片外组件，并提供了低成本和低功耗的解决方案。发射机包含两个低通滤波器(lpf)、一个单边带混频器(SSB)、一个功率放大器驱动器和一个用于正交LO产生的除以二电路。发射机在3db步进中提供12db的增益控制和7.7 dBm的1db输出压缩，同时提供0 dBm的标称输出功率。该芯片从1.8 v电源消耗40 mA，占地2.5乘以2 mm2(包括焊盘)
{"title":"A 2.4-GHz Fully CMOS Integrated Transmitter for 802.1lb Wireless LAN","authors":"Jirou He, Xiaoping Gao, Weilun Shen, Xiaofeng Yi, Yumei Huang, Zhiliang Hong","doi":"10.1109/ICASIC.2005.1611330","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611330","url":null,"abstract":"Featuring a direct-conversion architecture, a 2.4-GHz radio-frequency (RF) transmitter frontend for 802.11b wireless LAN (WLAN) is implemented in 0.18-mum CMOS technology. Direct-conversion architecture minimizes the on-and-off-chip components required and provides a low-cost and low-power solution. The transmitter incorporates two low-pass filters (LPFs), a single-sideband (SSB) mixer, a power amplifier driver and a divide-by-two circuit for quadrature LO generation. The transmitter provides a gain control of 12 dB in 3-dB steps and an output 1-dB compression of 7.7 dBm while delivering a nominal output power of 0 dBm. The chip consumes 40 mA from a 1.8-V supply and occupies an area of 2.5 times 2 mm2 including pads","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131917239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611262
Jae-Gon Lee, Hyung-Ock Kim, Sangkwon Na, Young-Il Kim, C. Kyung
This paper presents a mechanism which enables verification of algorithmic-level SoC model against actual target environment. By dividing algorithmic SoC model into functional sub-model and interface sub-model and to model the behavior of the latter with FPGA-based in-circuit emulator, we can verify the behavior of the former against actual target environment. The proposed mechanism also include a debugging environment for both functional sub-model and interface sub-model, which enables simultaneous debugging of both hardware and software components of the target SoC model. We implemented H. 264 video encoder and decoder model with the proposed method and verified it against actual target environment.
{"title":"iSAVE: In-System Algorithm Verifier for Early-stage SoC Verification against Actual Target Environment","authors":"Jae-Gon Lee, Hyung-Ock Kim, Sangkwon Na, Young-Il Kim, C. Kyung","doi":"10.1109/ICASIC.2005.1611262","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611262","url":null,"abstract":"This paper presents a mechanism which enables verification of algorithmic-level SoC model against actual target environment. By dividing algorithmic SoC model into functional sub-model and interface sub-model and to model the behavior of the latter with FPGA-based in-circuit emulator, we can verify the behavior of the former against actual target environment. The proposed mechanism also include a debugging environment for both functional sub-model and interface sub-model, which enables simultaneous debugging of both hardware and software components of the target SoC model. We implemented H. 264 video encoder and decoder model with the proposed method and verified it against actual target environment.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132459002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611449
Xiaopeng Dong, Inhwan Seo, W. Kao
The use of metal fill insertion to create a uniform interconnect layout pattern that minimizes topographical variation is a widely adopted practice for nanometer technologies. This paper presents new advances and considerations to achieve maximum metal density uniformity while minimizing impact on chip timing by using timing aware methods. It also describes a full comprehensive metal fill methodology which includes metal fill insertion, metal fill trimming and metal density verification. Finally some new customer requested features such as staggered pattern metal fill and power strapping are also described
{"title":"New metal fill considerations for nanometer technologies","authors":"Xiaopeng Dong, Inhwan Seo, W. Kao","doi":"10.1109/ICASIC.2005.1611449","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611449","url":null,"abstract":"The use of metal fill insertion to create a uniform interconnect layout pattern that minimizes topographical variation is a widely adopted practice for nanometer technologies. This paper presents new advances and considerations to achieve maximum metal density uniformity while minimizing impact on chip timing by using timing aware methods. It also describes a full comprehensive metal fill methodology which includes metal fill insertion, metal fill trimming and metal density verification. Finally some new customer requested features such as staggered pattern metal fill and power strapping are also described","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131479049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611329
Gu Xiaofeng, Lai Xin-quan, L. Yushan, W. Jianping, Zhang Jie
Comparators using hysteresis were widely used in IC design. The paper first introduces the design of the conventional comparator using hysteresis and its disadvantage for the low-threshold compare. Then a novel low-threshold comparator using hysteresis is developed. The threshold and width of the new comparator can be reduced to the mV range, the resolution and the dynamic characteristics are also good. Finally, a typical application of the new comparator using hysteresis is given for the AC-DC control circuit. Its threshold is 50mV and width is 20mV
{"title":"Design and application of the novel low-threshold comparator using hysteresis","authors":"Gu Xiaofeng, Lai Xin-quan, L. Yushan, W. Jianping, Zhang Jie","doi":"10.1109/ICASIC.2005.1611329","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611329","url":null,"abstract":"Comparators using hysteresis were widely used in IC design. The paper first introduces the design of the conventional comparator using hysteresis and its disadvantage for the low-threshold compare. Then a novel low-threshold comparator using hysteresis is developed. The threshold and width of the new comparator can be reduced to the mV range, the resolution and the dynamic characteristics are also good. Finally, a typical application of the new comparator using hysteresis is given for the AC-DC control circuit. Its threshold is 50mV and width is 20mV","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132258516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611470
Shaohe Wu, Min-Chuan Chen, Weimin Wu, Jinian Bian
We propose a hybrid approach to RTL property checking that combines ATPG and ILP techniques. A special ATPG engine is designed for Boolean logic in our solver. And we use an ILP tool to solve the word-level arithmetic operator. This method is more unified and efficient than those using pure bit-level tools (such as grasp, chaff etc) or pure word-level tools (such as omega, CPLEX etc). The experiments on some public benchmarks and special circuit demonstrate the big advantage in time consumption of our approach
{"title":"RTL property checking technology based on ATPG and ILP","authors":"Shaohe Wu, Min-Chuan Chen, Weimin Wu, Jinian Bian","doi":"10.1109/ICASIC.2005.1611470","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611470","url":null,"abstract":"We propose a hybrid approach to RTL property checking that combines ATPG and ILP techniques. A special ATPG engine is designed for Boolean logic in our solver. And we use an ILP tool to solve the word-level arithmetic operator. This method is more unified and efficient than those using pure bit-level tools (such as grasp, chaff etc) or pure word-level tools (such as omega, CPLEX etc). The experiments on some public benchmarks and special circuit demonstrate the big advantage in time consumption of our approach","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132278759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611338
Jinbao Wei, Haigang Yang, Hongguang Sun, Z. Lin, S. Xia
ISFET is a potentiometric sensor that is easily adapted for a wide range of chemical, biochemical and biomedical measurements. This article presents an ISFET sensor system-on-chip including the ISFET/REFET (reference FET) pair and ISFET/REFET amplifiers, bias current generator, as well as a reference electrode structure, all integrated on the same chip based on CMOS technology. The sensor chip is fabricated in a standard 0.35/spl mu/m 4-metal and 2-poly layer CMOS process (chartered semiconductor) to which extra post processing steps are added for depositing membranes. The chip operates at 3.3V and the total die area is 5 mm. Finally the performance of the integrated sensor interface circuit is measured and analyzed.
{"title":"A fully CMOS-integrated pH-ISFET interface circuit","authors":"Jinbao Wei, Haigang Yang, Hongguang Sun, Z. Lin, S. Xia","doi":"10.1109/ICASIC.2005.1611338","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611338","url":null,"abstract":"ISFET is a potentiometric sensor that is easily adapted for a wide range of chemical, biochemical and biomedical measurements. This article presents an ISFET sensor system-on-chip including the ISFET/REFET (reference FET) pair and ISFET/REFET amplifiers, bias current generator, as well as a reference electrode structure, all integrated on the same chip based on CMOS technology. The sensor chip is fabricated in a standard 0.35/spl mu/m 4-metal and 2-poly layer CMOS process (chartered semiconductor) to which extra post processing steps are added for depositing membranes. The chip operates at 3.3V and the total die area is 5 mm. Finally the performance of the integrated sensor interface circuit is measured and analyzed.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132694795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611265
Sang-Heon Lee, Jae-Gon Lee, Seonpil Kim, Woong Hwangbo, C. Kyung
It is important in SoC design that the design and verification can be done easily and quickly. And RT-level simulation in verification methods is still necessary, but the usage is limited by its slow speed. Therefore we propose a SoC verification environment in which hardware parts are accelerated in FPGA and cores are modeled with ISS. To connect ISS in high abstraction level with emulator in pin-level accuracy, bus functional model (BFM) is used. For hardware debugging, bus monitor is designed. By post-processing the data obtained by bus monitoring, debugging and performance estimation are possible. For easy and quick design and verification, we developed a tool which creates configurable bus architectures automatically. With this, the design time from specification to FPGA based prototyping can be reduced remarkably. Thus fast verification and design space exploration are possible. AMBA is chosen as the SoC bus protocol.
{"title":"SoC design environment with automated configurable bus generation for rapid prototyping","authors":"Sang-Heon Lee, Jae-Gon Lee, Seonpil Kim, Woong Hwangbo, C. Kyung","doi":"10.1109/ICASIC.2005.1611265","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611265","url":null,"abstract":"It is important in SoC design that the design and verification can be done easily and quickly. And RT-level simulation in verification methods is still necessary, but the usage is limited by its slow speed. Therefore we propose a SoC verification environment in which hardware parts are accelerated in FPGA and cores are modeled with ISS. To connect ISS in high abstraction level with emulator in pin-level accuracy, bus functional model (BFM) is used. For hardware debugging, bus monitor is designed. By post-processing the data obtained by bus monitoring, debugging and performance estimation are possible. For easy and quick design and verification, we developed a tool which creates configurable bus architectures automatically. With this, the design time from specification to FPGA based prototyping can be reduced remarkably. Thus fast verification and design space exploration are possible. AMBA is chosen as the SoC bus protocol.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"163 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127373759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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