Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611289
Lin Yi-fan, Zeng Xiao-yang, Wu Min, Chen Jun, Bao Rencheng
With the rapid development on the software-hardware co-verification of SoC, FPGA verification has become more and more critical for VLSI design, and it requires much more portion of time within the life circle of chip development. The time spent on the FPGA verification should be reduced to achieve a more efficient time-to-market for the IC product. Therefore, several strategies using both dynamic and static methods to execute this verification are proposed in this paper. By using a variety of techniques such as software static breakpoint monitoring and interrupt vectors remapping, the software verification is accelerated. A bus analyzer is adopted to provide real-time bus monitoring with a vivid evaluation of the system performance. In this paper, experiments show that above methods have greatly enhanced the efficiency and speed of the FPGA co-verification process
{"title":"New methods of FPGA co-verification for system on chip (SoC)","authors":"Lin Yi-fan, Zeng Xiao-yang, Wu Min, Chen Jun, Bao Rencheng","doi":"10.1109/ICASIC.2005.1611289","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611289","url":null,"abstract":"With the rapid development on the software-hardware co-verification of SoC, FPGA verification has become more and more critical for VLSI design, and it requires much more portion of time within the life circle of chip development. The time spent on the FPGA verification should be reduced to achieve a more efficient time-to-market for the IC product. Therefore, several strategies using both dynamic and static methods to execute this verification are proposed in this paper. By using a variety of techniques such as software static breakpoint monitoring and interrupt vectors remapping, the software verification is accelerated. A bus analyzer is adopted to provide real-time bus monitoring with a vivid evaluation of the system performance. In this paper, experiments show that above methods have greatly enhanced the efficiency and speed of the FPGA co-verification process","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131587608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611419
Wu Chao, Wang Hong, Y. Shi-yuan
IEEE P1500 is a standard under development which intends to improve ease of test reuse and test integration with respect to the core-based SoCs. This paper proposes a P1500-compliant wrapper and TAM controller design scheme. Area overhead and power consumption are taken into account in our scheme. Some experiment results based on a sample SoC are reported, showing the effectiveness of the proposed approach in terms of area overhead
{"title":"A P1500-compliant wrapper and TAM controller co-design scheme","authors":"Wu Chao, Wang Hong, Y. Shi-yuan","doi":"10.1109/ICASIC.2005.1611419","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611419","url":null,"abstract":"IEEE P1500 is a standard under development which intends to improve ease of test reuse and test integration with respect to the core-based SoCs. This paper proposes a P1500-compliant wrapper and TAM controller design scheme. Area overhead and power consumption are taken into account in our scheme. Some experiment results based on a sample SoC are reported, showing the effectiveness of the proposed approach in terms of area overhead","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131610793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611472
Ruijing Shen, Xiangqing He, Liu Yang
For a successful analog/mixed signal design, various layout constraints have to be seriously addressed, which is one of the reasons why automatic design of analog layouts is intrinsically more difficult than that of digital layouts. Since feedback has long been a mysterious effect in virtually all analog integrated circuits, improving on constraint file can be done according to feedback information. In this paper, the technique of feedback circuit extraction (FCE) is presented, which is the transformation of feedback design descriptions from circuit level to functional level. Novelly, the algorithm of FCE utilizes the direction of signal flow to extract detailed information of intentional feedback network
{"title":"Extraction of feedback information from circuit netlists","authors":"Ruijing Shen, Xiangqing He, Liu Yang","doi":"10.1109/ICASIC.2005.1611472","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611472","url":null,"abstract":"For a successful analog/mixed signal design, various layout constraints have to be seriously addressed, which is one of the reasons why automatic design of analog layouts is intrinsically more difficult than that of digital layouts. Since feedback has long been a mysterious effect in virtually all analog integrated circuits, improving on constraint file can be done according to feedback information. In this paper, the technique of feedback circuit extraction (FCE) is presented, which is the transformation of feedback design descriptions from circuit level to functional level. Novelly, the algorithm of FCE utilizes the direction of signal flow to extract detailed information of intentional feedback network","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128068614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611307
Xu Ma, Jian Gao, Jing Chen
This paper presents a high-performance low-power 2D IDCT processor for video applications. Based on multiply-accumulator architecture, the processor can meet the high-speed requirement of HDTV. To save power consumption, the processor employs asynchronous pipeline in which local clocks are enabled only when there is an operation to perform. Compared with conventional synchronous pipelined design, the proposed design exhibits an average power saving of 40%.
{"title":"A high-performance low-power 2D 8/spl times/8 IDCT processor with asynchronous pipeline","authors":"Xu Ma, Jian Gao, Jing Chen","doi":"10.1109/ICASIC.2005.1611307","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611307","url":null,"abstract":"This paper presents a high-performance low-power 2D IDCT processor for video applications. Based on multiply-accumulator architecture, the processor can meet the high-speed requirement of HDTV. To save power consumption, the processor employs asynchronous pipeline in which local clocks are enabled only when there is an operation to perform. Compared with conventional synchronous pipelined design, the proposed design exhibits an average power saving of 40%.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133316994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611252
Z. Qi, Hang Li, S.X.-D. Tan, Yici Cai, Xianlong Hong
Excessive power supply noise increases propagation delay of switching gates and reduces noise margin of the circuit. Adding on-chip decoupling capacitors (decaps) is an effective way to reduce voltage noise in a on-chip power delivery system. In this paper, we propose an efficient and novel algorithm to allocate decaps in an area efficient way. The new algorithm applies the sequence of linear programming based approach to searching the minimum decap area to reduce voltage drop below user specified threshold. We show existing sensitivity based decap allocation algorithms tend to over estimate the decap areas due to nonlinear sensitivity dependence on decap values. Experimental results show that the proposed algorithm uses significantly less decap area than the existing conjugate gradient based approach but with similar CPU runtimes
{"title":"On-chip decoupling capacitor budgeting by sequence of linear programming","authors":"Z. Qi, Hang Li, S.X.-D. Tan, Yici Cai, Xianlong Hong","doi":"10.1109/ICASIC.2005.1611252","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611252","url":null,"abstract":"Excessive power supply noise increases propagation delay of switching gates and reduces noise margin of the circuit. Adding on-chip decoupling capacitors (decaps) is an effective way to reduce voltage noise in a on-chip power delivery system. In this paper, we propose an efficient and novel algorithm to allocate decaps in an area efficient way. The new algorithm applies the sequence of linear programming based approach to searching the minimum decap area to reduce voltage drop below user specified threshold. We show existing sensitivity based decap allocation algorithms tend to over estimate the decap areas due to nonlinear sensitivity dependence on decap values. Experimental results show that the proposed algorithm uses significantly less decap area than the existing conjugate gradient based approach but with similar CPU runtimes","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131990246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611359
Mao Jingwen, Chen Tingqian, Chen Cheng, R. Junyan, Yang Li
A low power and high precision CMOS bandgap voltage reference circuit is presented. Prototype of the circuit is fabricated using the 0.18 mum CMOS process. The power supply is only 1.5 V. It fulfills the first order PTAT (proportion to absolute temperature) temperature curvature compensation with a good PSRR (power supply rejection ratio). The measured results of this circuit show that the PSRR is 47 dB. The output voltage varies from 1.114 V to 1.117 V which is constant within 0.269% over the temperature range of 0~80 degC. The power dissipation is 0.22 mW at 1.5 V and the active area is 0.057 mm2
{"title":"CMOS 1.5V bandgap voltage reference","authors":"Mao Jingwen, Chen Tingqian, Chen Cheng, R. Junyan, Yang Li","doi":"10.1109/ICASIC.2005.1611359","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611359","url":null,"abstract":"A low power and high precision CMOS bandgap voltage reference circuit is presented. Prototype of the circuit is fabricated using the 0.18 mum CMOS process. The power supply is only 1.5 V. It fulfills the first order PTAT (proportion to absolute temperature) temperature curvature compensation with a good PSRR (power supply rejection ratio). The measured results of this circuit show that the PSRR is 47 dB. The output voltage varies from 1.114 V to 1.117 V which is constant within 0.269% over the temperature range of 0~80 degC. The power dissipation is 0.22 mW at 1.5 V and the active area is 0.057 mm2","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130339789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611245
S. Leibson
SOCs solve complex, data-intensive application problems by delivering high performance with good power-efficiency. Configurable, application-specific processor cores used as task blocks in an SOC deliver hardware-like performance and programmability, which reduces design effort and risk when compared to manual RTL block-design techniques.
{"title":"SOC logic development using configurable, application-specific processors","authors":"S. Leibson","doi":"10.1109/ICASIC.2005.1611245","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611245","url":null,"abstract":"SOCs solve complex, data-intensive application problems by delivering high performance with good power-efficiency. Configurable, application-specific processor cores used as task blocks in an SOC deliver hardware-like performance and programmability, which reduces design effort and risk when compared to manual RTL block-design techniques.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124523439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611327
Qin Song, Wu Xiaobo, Yan Xiaolang
A novel minimum-voltage active-clamping (MVAC) PFC controller was developed, which is capable of providing effective control scheme to the MVAC PFC converter to suppress the reverse-recovery current of the boost diode and minimize the voltage stress on switch devices. The corresponding control strategy was proposed and implemented in its design. To reduce the ripple currents in output capacitor, the leading-edge modulation was employed. And programmable turn-on delay time was adopted to realize zero-voltage-switching (ZVS) operation. The IC was designed and simulated in 1.5 /spl mu/m BCD (bipolar-CMOS-DMOS) process. The simulation results showed that the expected specifications were achieved.
{"title":"A novel minimum-voltage active-clamping PFC controller","authors":"Qin Song, Wu Xiaobo, Yan Xiaolang","doi":"10.1109/ICASIC.2005.1611327","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611327","url":null,"abstract":"A novel minimum-voltage active-clamping (MVAC) PFC controller was developed, which is capable of providing effective control scheme to the MVAC PFC converter to suppress the reverse-recovery current of the boost diode and minimize the voltage stress on switch devices. The corresponding control strategy was proposed and implemented in its design. To reduce the ripple currents in output capacitor, the leading-edge modulation was employed. And programmable turn-on delay time was adopted to realize zero-voltage-switching (ZVS) operation. The IC was designed and simulated in 1.5 /spl mu/m BCD (bipolar-CMOS-DMOS) process. The simulation results showed that the expected specifications were achieved.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124882137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611315
Yizhen Zhang, Chao Xu, L. Chen
This paper presents a flexible dual-symbol coding arithmetic coder (MQ coder) architecture design for the parallel coding engines of embedded block coding with optimization truncation (EBCOT) tier-1 in JPEG2000. The flexible MQ coder (FMQ) can encode two symbols simultaneously per clock cycle by using the optimized combination method. It increases the throughput rate of the arithmetic coding, which can match the high throughput rate of the parallel context modeling modules. Experimental results show that one FMQ are able to handle two bit-planes/data-pairs for the bit-plane parallel EBCOT coding engine, and the computation time is decreased about 24% compared with the engine by using the regular MQ coder
{"title":"A dual-symbol coding arithmetic coder architecture design for high speed EBCOT coding engine in JPEG2000","authors":"Yizhen Zhang, Chao Xu, L. Chen","doi":"10.1109/ICASIC.2005.1611315","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611315","url":null,"abstract":"This paper presents a flexible dual-symbol coding arithmetic coder (MQ coder) architecture design for the parallel coding engines of embedded block coding with optimization truncation (EBCOT) tier-1 in JPEG2000. The flexible MQ coder (FMQ) can encode two symbols simultaneously per clock cycle by using the optimized combination method. It increases the throughput rate of the arithmetic coding, which can match the high throughput rate of the parallel context modeling modules. Experimental results show that one FMQ are able to handle two bit-planes/data-pairs for the bit-plane parallel EBCOT coding engine, and the computation time is decreased about 24% compared with the engine by using the regular MQ coder","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125216605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611361
Wenyu Xiao, Zhiliang Chen
Organic light emitting display (OLED) is a new type of flat-panel display (FPD). And the research on the mix-signal driver chip for OLED is still going on. A single-chip passive-matrix OLED driver for 96 (RGB) times 64-pixel panel is presented in this paper. This driver chip has a 256-step contrast control and a 65k-color control. It consists of a digital controller, a SRAM as display data memory, a built-in DC-DC boost converter, an oscillator, 3 (RGB) reference current generators, 64 common drivers, and 96 times 3 segment drivers. The segment drivers use the pulse amplitude modulation (PAM) method to modulate grayscales and the voltage pre-charge technology to pre-charge the OLED pixels. This chip is a typical current-drive circuit. Simulation and analysis of its power consumption indicate that it is necessary for us to research the circuit design of the drivers and display mechanism (including pre-charge and discharge) further
{"title":"A mixed-signal driver chip for 65K-color passive-matrix OLED","authors":"Wenyu Xiao, Zhiliang Chen","doi":"10.1109/ICASIC.2005.1611361","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611361","url":null,"abstract":"Organic light emitting display (OLED) is a new type of flat-panel display (FPD). And the research on the mix-signal driver chip for OLED is still going on. A single-chip passive-matrix OLED driver for 96 (RGB) times 64-pixel panel is presented in this paper. This driver chip has a 256-step contrast control and a 65k-color control. It consists of a digital controller, a SRAM as display data memory, a built-in DC-DC boost converter, an oscillator, 3 (RGB) reference current generators, 64 common drivers, and 96 times 3 segment drivers. The segment drivers use the pulse amplitude modulation (PAM) method to modulate grayscales and the voltage pre-charge technology to pre-charge the OLED pixels. This chip is a typical current-drive circuit. Simulation and analysis of its power consumption indicate that it is necessary for us to research the circuit design of the drivers and display mechanism (including pre-charge and discharge) further","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132418337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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