Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611477
G. Suzuki
The Elmore base delay calculation method has long been in use, but this method cannot meet accuracy demands of current designs using deep sub-micron processes. On the other hand, SPICE can provide high accuracy, but it is very time consuming. Therefore, a novel, highly accurate and high-speed delay analysis method is proposed: MOR (model order reduction). We applied it in interconnect signal analysis to evaluate its performance
{"title":"VLSI interconnect signal analysis using a projection framework method","authors":"G. Suzuki","doi":"10.1109/ICASIC.2005.1611477","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611477","url":null,"abstract":"The Elmore base delay calculation method has long been in use, but this method cannot meet accuracy demands of current designs using deep sub-micron processes. On the other hand, SPICE can provide high accuracy, but it is very time consuming. Therefore, a novel, highly accurate and high-speed delay analysis method is proposed: MOR (model order reduction). We applied it in interconnect signal analysis to evaluate its performance","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115334639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611392
Lai Xin-quan, Yu Weixue, Ligang, Cao Yu
Based on the power-up/power-down control, the paper describes a low quiescent current and reset time adjustable power-on reset (POR) circuit, which is integrated in a regulator. Compared with the conventional RC reset circuit, it can provide more accurate reset pulse at slow power up and twinkling power down. And when the chip works properly, parts of the power-on reset circuit are shut down, then the quiescent current of the POR is reduced by 12muA. In addition, the power-on reset time can be adjusted based on different applications
{"title":"A low quiescent current and reset time adjustable power-on reset circuit","authors":"Lai Xin-quan, Yu Weixue, Ligang, Cao Yu","doi":"10.1109/ICASIC.2005.1611392","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611392","url":null,"abstract":"Based on the power-up/power-down control, the paper describes a low quiescent current and reset time adjustable power-on reset (POR) circuit, which is integrated in a regulator. Compared with the conventional RC reset circuit, it can provide more accurate reset pulse at slow power up and twinkling power down. And when the chip works properly, parts of the power-on reset circuit are shut down, then the quiescent current of the POR is reduced by 12muA. In addition, the power-on reset time can be adjusted based on different applications","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"401 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115919065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611295
F. Wang, Yunyong Yu, Xiaofang Hou, Hao Min, D. Hou
In this paper we proposed a design of a Java co-processor for a 32-bit RISC system to improve its performance, as the software only Java interpreter is more time-consuming. Our work includes the hardware/software co-design of the Java Card Virtual Machine (JCVM) and the details of its hardware implementation. The JCVM translates the Java bytecodes (JBCs) into the native RISC instructions and then passes them to the RISC core. A 16-byte pre-fetch FIFO and the folding mechanism are applied to further speedup the translation.
{"title":"AR AR /SO T AR CO- SI O A AVA CO-PROC SSOR OR A 3 -BIT RISC S ST MA T IMP M TATIO O T AR AR PARTITIO","authors":"F. Wang, Yunyong Yu, Xiaofang Hou, Hao Min, D. Hou","doi":"10.1109/ICASIC.2005.1611295","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611295","url":null,"abstract":"In this paper we proposed a design of a Java co-processor for a 32-bit RISC system to improve its performance, as the software only Java interpreter is more time-consuming. Our work includes the hardware/software co-design of the Java Card Virtual Machine (JCVM) and the details of its hardware implementation. The JCVM translates the Java bytecodes (JBCs) into the native RISC instructions and then passes them to the RISC core. A 16-byte pre-fetch FIFO and the folding mechanism are applied to further speedup the translation.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124265605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611293
Yangbo Wu, Huiying Dong, Yi Wang, Jianping Hu
Complementary pass-transistor adiabatic logic (CPAL) circuits can be driven by two-phase or four-phase power-clocks. CPAL circuits have more efficient energy transfer and recovery, as the non-adiabatic energy loss of output loads has been completely eliminated using complementary pass-transistor logic for evaluation and transmission gates for energy-recovery. In this paper, the design of adiabatic asynchronous sequential circuits based on the two-phase CPAL is presented. A practical sequential system realized with two-phase CPAL circuits is demonstrated. A two-phase nonoverlap sinusoidal power clock circuit for the two-phase CPAL is also presented
{"title":"Low-power adiabatic sequential circuits using two-phase power-clock supply","authors":"Yangbo Wu, Huiying Dong, Yi Wang, Jianping Hu","doi":"10.1109/ICASIC.2005.1611293","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611293","url":null,"abstract":"Complementary pass-transistor adiabatic logic (CPAL) circuits can be driven by two-phase or four-phase power-clocks. CPAL circuits have more efficient energy transfer and recovery, as the non-adiabatic energy loss of output loads has been completely eliminated using complementary pass-transistor logic for evaluation and transmission gates for energy-recovery. In this paper, the design of adiabatic asynchronous sequential circuits based on the two-phase CPAL is presented. A practical sequential system realized with two-phase CPAL circuits is demonstrated. A two-phase nonoverlap sinusoidal power clock circuit for the two-phase CPAL is also presented","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124542400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611516
Zhou Jiliu, Pu Yifei, Yuan Xiao, Liao Ke
In the first, the paper puts forward a frac12 order H type analog fractance circuit. In the second, it further puts forward any fractional order H type analog fractance circuit for any order fractional calculus. In the last, it is proved to performance correctly and efficiently by computer simulation and circuit analog. The result educing by the paper is the basis for further theoretic research and engineering implement to structure fractance circuit for any order fractional calculus
{"title":"Any fractional order H type analog fractance circuit","authors":"Zhou Jiliu, Pu Yifei, Yuan Xiao, Liao Ke","doi":"10.1109/ICASIC.2005.1611516","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611516","url":null,"abstract":"In the first, the paper puts forward a frac12 order H type analog fractance circuit. In the second, it further puts forward any fractional order H type analog fractance circuit for any order fractional calculus. In the last, it is proved to performance correctly and efficiently by computer simulation and circuit analog. The result educing by the paper is the basis for further theoretic research and engineering implement to structure fractance circuit for any order fractional calculus","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114340333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611476
Markus Wedler, D. Stoffel, W. Kunz
This paper provides an overview on recently developed model generation techniques for SAT-based property checking. To overcome limitations of SAT-based property checking, we suggest to tailor synthesis procedures in the frontend of the property checker towards the verification algorithms used in the backend. This paradigm has been applied to two different design categories. As a first example, for control intensive designs with many interacting state machines, appropriate state encoding can facilitate the representation of state sets. As a second example, for arithmetic datapath verification, we suggest to synthesize an arithmetic bit level description to enable normalization techniques in the backend. We demonstrate the usefulness of our approach by means of industrial test cases.
{"title":"Frontend model generation for SAT-based property checking","authors":"Markus Wedler, D. Stoffel, W. Kunz","doi":"10.1109/ICASIC.2005.1611476","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611476","url":null,"abstract":"This paper provides an overview on recently developed model generation techniques for SAT-based property checking. To overcome limitations of SAT-based property checking, we suggest to tailor synthesis procedures in the frontend of the property checker towards the verification algorithms used in the backend. This paradigm has been applied to two different design categories. As a first example, for control intensive designs with many interacting state machines, appropriate state encoding can facilitate the representation of state sets. As a second example, for arithmetic datapath verification, we suggest to synthesize an arithmetic bit level description to enable normalization techniques in the backend. We demonstrate the usefulness of our approach by means of industrial test cases.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114390203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes an improved version of the Tenca-Todorov-Koc word based radix-8 Montgomery multiplier. It uses radix-16 for fast without adding any hardware, and adjusting the data-path to get shorter critical path, and requires half of FIFO memory. This design is reconfigurable to accept any input precision as the Tenca-Todorov-Koc's design. An ASIC implementation in 0.25 mum CMOS standard cell technology can perform 2048-bit modular exponentiation in 28ms under 125MHz clock period
本文描述了基于Tenca-Todorov-Koc字的基数-8蒙哥马利乘法器的改进版本。它在不增加任何硬件的情况下使用基数16来实现快速，并调整数据路径以获得更短的关键路径，并且需要一半的FIFO内存。该设计可重新配置，以接受任何输入精度作为Tenca-Todorov-Koc的设计。采用0.25 μ m CMOS标准单元技术的ASIC实现在125MHz时钟周期下可在28ms内完成2048位模块幂运算
{"title":"High speed radix-16 design of a scalable Montgomery multiplier","authors":"Yibo Fan, Xiaoyang Zeng, Yu Yu, G. Wang, Huang Deng, Qianling Zhang","doi":"10.1109/ICASIC.2005.1611286","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611286","url":null,"abstract":"This paper describes an improved version of the Tenca-Todorov-Koc word based radix-8 Montgomery multiplier. It uses radix-16 for fast without adding any hardware, and adjusting the data-path to get shorter critical path, and requires half of FIFO memory. This design is reconfigurable to accept any input precision as the Tenca-Todorov-Koc's design. An ASIC implementation in 0.25 mum CMOS standard cell technology can perform 2048-bit modular exponentiation in 28ms under 125MHz clock period","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122100076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611369
Yong-ping Dai, Weidong Geng, Yan-yan Liu, Sun Zhonglin
8-bit gamma compensated digital data driver was integrated in LCoS silicon backplane. We have applied conventional register ladder D/A converter with 4 points reference voltage for LCoS displaying (VGA). The LCoS microdisplay operating with fields sequential color (FSC) mode has been developed in the Microdisplay lab of Nankai University, and the data driver can realize 256 level gray scales. In this paper, the concept that utilizes cascaded resistor strings delivers a static voltage output were shown in detail.
{"title":"LCoS chip with integrated 8-bit gamma compensated digital data driver","authors":"Yong-ping Dai, Weidong Geng, Yan-yan Liu, Sun Zhonglin","doi":"10.1109/ICASIC.2005.1611369","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611369","url":null,"abstract":"8-bit gamma compensated digital data driver was integrated in LCoS silicon backplane. We have applied conventional register ladder D/A converter with 4 points reference voltage for LCoS displaying (VGA). The LCoS microdisplay operating with fields sequential color (FSC) mode has been developed in the Microdisplay lab of Nankai University, and the data driver can realize 256 level gray scales. In this paper, the concept that utilizes cascaded resistor strings delivers a static voltage output were shown in detail.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117154880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611241
D. Sylvester
Design for manufacturability (DFM) is one of the foremost concerns in the semiconductor industry today. This work describes a few of the key issues facing circuit designers and tool developers in the DFM space and points to future areas of research interest. In particular, we show that comprehending and exploiting systematic pattern dependencies can be a powerful knob to improve performance under variability. Furthermore, we describe a cost-driven approach to mask-level correction that points to new areas of research that would allow design rules to vary depending on context and/or instance criticality. This and other opportunities in DFM research are summarized
{"title":"Design for manufacturability: challenges and opportunities","authors":"D. Sylvester","doi":"10.1109/ICASIC.2005.1611241","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611241","url":null,"abstract":"Design for manufacturability (DFM) is one of the foremost concerns in the semiconductor industry today. This work describes a few of the key issues facing circuit designers and tool developers in the DFM space and points to future areas of research interest. In particular, we show that comprehending and exploiting systematic pattern dependencies can be a powerful knob to improve performance under variability. Furthermore, we describe a cost-driven approach to mask-level correction that points to new areas of research that would allow design rules to vary depending on context and/or instance criticality. This and other opportunities in DFM research are summarized","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124488394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611303
J. Zhou, Xiao-Gang Jiang, Hui-Huang Chen
In the computing system, division is normally programmed as an multiplication operation following with a multiplicative inversion process. It is the most time consuming operation in the computing of elliptic curve cryptography (ECC) for portable applications. This paper introduces a new architecture for hardware implementation of computing division based on the binary extended Euclidean algorithm. With the new architecture, ECC can be implemented with low power consumption and more computing efficiency for application in real-time system. In order to show the advantages, we also detail on the modified algorithm of our new architecture and compare the synthesis results of hardware implementations
{"title":"An efficient architecture for computing division over GF(/sup 2/m) in elliptic curve cryptography","authors":"J. Zhou, Xiao-Gang Jiang, Hui-Huang Chen","doi":"10.1109/ICASIC.2005.1611303","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611303","url":null,"abstract":"In the computing system, division is normally programmed as an multiplication operation following with a multiplicative inversion process. It is the most time consuming operation in the computing of elliptic curve cryptography (ECC) for portable applications. This paper introduces a new architecture for hardware implementation of computing division based on the binary extended Euclidean algorithm. With the new architecture, ECC can be implemented with low power consumption and more computing efficiency for application in real-time system. In order to show the advantages, we also detail on the modified algorithm of our new architecture and compare the synthesis results of hardware implementations","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132386551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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